JPH07147298A - Mounting structure of semiconductor device and mounting method therefor - Google Patents

Abstract

PURPOSE:To prevent a tool from contacting with a temporary fixed or connected semiconductor chip when the semiconductor chip is temporary fixed or connected in a semiconductor device to be mounted by a face-down method. CONSTITUTION:After a semiconductor chip 1 of which the thickness of the semiconductor substrate is thin is mounted on a wiring board 3, a semiconductor chip 2 is mounted of which the thickness of the semiconductor substrate is thick. Thus, highly reliable and high density mounting is made possible.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting structure of a semiconductor device, and more particularly to a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down manner and a mounting method thereof.

[0002]

2. Description of the Related Art As a semiconductor device mounting method for connecting a semiconductor chip to a wiring board in a face-down manner, a semiconductor chip is connected to a chip electrode of the semiconductor chip through bumps formed by plating, ball bonding, or the like. There are a method of pressing and connecting a semiconductor chip with an anisotropic conductive film sandwiched between wiring boards, a method of arranging conductive particles on a chip electrode or a substrate electrode and pressing the semiconductor chip to connect. In any of these methods, a tool is applied from the back surface of the semiconductor chip when the semiconductor chip is temporarily fixed to the semiconductor substrate or when the semiconductor chip is connected to the wiring substrate.

When mounting a plurality of semiconductor chips,
According to the conventional technology, the thickness of the semiconductor substrate of the semiconductor chip, the connection structure for connecting the chip electrode of the semiconductor chip and the substrate electrode of the wiring board, and the wiring board for connecting the semiconductor chip are not particularly changed. After the connection, the height from the reference surface to the back surface of the semiconductor chip was the same.

[0004]

In recent years, in order to mount a plurality of semiconductor chips at a high density and in view of electrical characteristics, there is a great demand for reducing the distance between adjacent semiconductor chips.

However, if the heights from the reference surface of the wiring board to the back surface of the semiconductor chip after connection are the same as before, the second semiconductor adjacent to the first semiconductor chip that has already been temporarily fixed or connected is used. When attempting to temporarily fix or connect the semiconductor chip described above, the following problems occur.

As shown in FIG. 7 (a), the tool 4 also contacts the back surface 1r of the first semiconductor chip 1, and the first semiconductor chip 1 is displaced due to some normal blurring.

As shown in FIG. 7 (b), the tool 4 contacts the back surface 1r of the first semiconductor chip 1 and the first semiconductor chip 1 is tilted due to a slight blur which is usually generated.

As shown in FIG. 7 (c), the tool 4 also contacts the back surface 1r of the first semiconductor chip 1 and the first semiconductor chip 1 may be cracked or chipped due to slight deviations that normally occur. Damage occurs.

As shown in FIG. 7 (d), since the tool 4 is in contact with the back surface 1r of the first semiconductor chip 1, heat, load, ultrasonic waves, etc. from the tool 4 are generated by the first tool. The semiconductor chip 1 is also applied, so that heat, load, ultrasonic waves, etc. are not sufficiently applied to the second semiconductor chip 2, and the connection of the second semiconductor chip 2 becomes insufficient.

As shown in FIG. 7 (e), since the tool 4 is in contact with the back surface 1r of the first semiconductor chip 1, heat, load, ultrasonic waves, etc. from the tool 4 are the first. For example, in the case of connection using Au and Sn or the like on the semiconductor chip 1, metal diffusion proceeds too much due to heat applied to the first semiconductor chip 1 and the connection of the first semiconductor chip 1 deteriorates. .

As shown in FIG. 7 (f), the tool 4 is in contact with the back surface 1r of the first semiconductor chip 1, so that heat, load, ultrasonic waves, etc. from the tool 4 are generated by the first tool. For example, an element 1x made of a material that is weak against heat when applied to the semiconductor chip 1.
And the like were not affected by the heat for connecting the first semiconductor chip 1, but the heat for connecting the second semiconductor chip 2 was further applied. 1x electrical characteristics deteriorate.

For this reason, some methods have been attempted to make the pressing surface of the tool the same size as the semiconductor chip, but it is necessary to manufacture the tool according to various sizes of the semiconductor chip, which increases the cost. In addition, since the tool must be replaced for each semiconductor chip, the number of working steps increases and the running cost increases. Also, if the size of the semiconductor chip is reduced to a certain extent or more, suction holes, heaters, load sensors, etc. cannot be provided on the tool,
It is impossible to make such a tool. In addition, when the tool pressing surface has the same size as the semiconductor chip, unless the tool and the semiconductor chip are sufficiently aligned, as shown in FIG. Damage such as cracks and chipping occurs.
This also applies when the size of the pressing surface of the tool is smaller than that of the semiconductor chip. As described above, it has been difficult to meet the demand for reducing the distance from the semiconductor chip.

[0013]

According to a first aspect of the present invention, there is provided a semiconductor device mounting structure in which a plurality of semiconductor chips are connected to a wiring board by a face-down method. The height from the reference surface of the wiring board to the back surface of the second semiconductor chip is higher than the height from the back surface of the semiconductor chip, and from the height from the reference surface of the wiring board to the main surface of the first semiconductor chip. Also has a high height from the reference surface of the wiring board to the main surface of the second semiconductor chip and is connected to the wiring board.

According to a second aspect of the present invention, in a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board by a face-down method, from a reference surface of the wiring board to a back surface of the first semiconductor chip. The height from the reference surface of the wiring board to the main surface of the second semiconductor chip is higher than the height, and the connection is made on the wiring board.

According to a third aspect of the present invention, in a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board by a face-down method, from a reference surface of the wiring board to a back surface of the first semiconductor chip. The wiring board is higher than the height from the reference surface of the wiring board to the main surface of the second semiconductor chip, and the second semiconductor chip partially overlaps with the first semiconductor chip. It is characterized by being connected above.

The present invention according to claim 4 provides the invention according to claim 1,
In the mounting method of the semiconductor device described in 2 or 3,
After connecting the first semiconductor chip to the wiring board, the second semiconductor chip is connected to the wiring board.

[0017]

According to the present invention, when attempting to temporarily fix or connect a second semiconductor chip next to a first semiconductor chip that has already been temporarily fixed or connected, the first semiconductor chip is removed from the reference surface of the wiring board. Since the height from the reference surface of the wiring substrate to the back surface of the second semiconductor chip is lower than the height from the reference surface of the wiring board to the back surface of the first semiconductor chip, a tool for connecting the second semiconductor chip to the back surface of the first semiconductor chip. Le never touches.

[0018]

Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment FIGS. 1A to 1E are sectional views showing main steps of a first embodiment of the present invention. Here, a case is shown in which a plurality of semiconductor chips having bumps formed on chip electrodes are mounted on a wiring board.

First, the wiring board 3 on which the wiring 3w, the electrodes 3e, etc. are formed is prepared (FIG. 1A). Here, the AIN substrate 3 on which the wiring 3w and the electrode 3e are formed is used.
Any of WB, a glass substrate, or the like may be used.

Next, the first semiconductor chip 1 in which the thickness of the semiconductor substrate 1s is made thinner than the thickness of the semiconductor substrate 2s of the second semiconductor chip 2 described later is prepared, and the chip of the first semiconductor chip 1 is prepared. The electrode 1e and the corresponding substrate electrode 3e of the wiring board 3 are aligned (FIG. 1 (b)). here,
Au is used for the chip electrode 1e using the GaAs semiconductor substrate 1s.
Although the semiconductor chip 1 on which the bumps 1a are formed is used, it is also possible to use a semiconductor chip on which solder bumps, Cu ball bumps, or the like are formed.

Next, the first semiconductor chip 1 is attached to the wiring board 3
(Fig. 1 (c)). Here, the tool 4 is used for connection while being heated while being heated, but ultrasonic waves may be further applied.

Next, the second semiconductor chip 2 in which the thickness of the semiconductor substrate 2s is made thicker than the thickness of the semiconductor substrate 1s of the first semiconductor chip 1 is prepared, and the chip electrode 2e of the second semiconductor chip 2 is prepared. And the corresponding substrate electrode 3e of the wiring substrate 3 are aligned (FIG. 1 (d)).

Finally, the second semiconductor chip 2 is connected to the wiring board 3 (FIG. 1 (e)). Here, connection was performed in the same manner as in FIG. At this time, the reference plane 3 of the wiring board 3
Height H ₂ from a to the back surface 2r of the second semiconductor chip ₂
Is the first semiconductor chip 1 from the reference surface 3a of the wiring board 3.
Since the height is higher than the height H ₁ to the back surface 1r of the tool 4, even if the pressing surface of the tool 4 for pressing the second semiconductor chip 2 extends beyond the second semiconductor chip 2, the tool 4 is not the first. It does not hit the semiconductor chip 1.

Second Embodiment FIGS. 2A to 2E are sectional views showing main steps of a second embodiment of the present invention. Here, as a connection structure for connecting the chip electrode of the semiconductor chip and the substrate electrode of the wiring board,
The case where a semiconductor chip in which conductive particles are arranged on chip electrodes and a semiconductor chip connected to a wiring board via an anisotropic conductive film are mounted on the wiring board is shown.

First, the wiring board 3 on which the wiring 3w, the electrodes 3e, etc. are formed is prepared (FIG. 2A). Here, the glass substrate 3 on which the wiring 3w and the electrode 3e are formed is used.
Any of WB, a ceramic substrate, etc. may be used.

Next, the first semiconductor chip 1 in which the small-diameter conductive particles 1a are arranged on the chip electrode 1e is prepared, and the chip electrode 1e of the first semiconductor chip 1 and the corresponding substrate electrode 3e of the wiring board 3 are prepared. Are aligned (FIG. 2 (b)). Here, the silicon semiconductor substrate 1s is used, and the chip electrode 1
A semiconductor chip 1 was used in which conductive particles 1a obtained by coating a resin with Au were placed. The conductive particles are arranged by applying a photosensitive resin to a silicon wafer having electrodes formed thereon, irradiating the resin other than the electrode portion with UV to cure the conductive particles, and spraying the conductive particles, followed by washing, Since only the uncured electrode part has adhesiveness, the conductive particles adhere to only the electrode part and the conductive particles do not adhere to other parts. Resin is also U
It is a method of curing by V irradiation.

Next, the first semiconductor chip 1 is attached to the wiring board 3
(Fig. 2 (c)). Here, the semiconductor chip 1
Alternatively, an appropriate amount of the photosensitive resin 1a ′ may be dropped onto the wiring board 3, and the tool 4 may press the semiconductor chip 1 against the wiring board 3 to make U
V irradiation is performed. The wiring substrate 3 used here is one that transmits UV light.

Next, the second semiconductor chip 2 is prepared, and the chip electrode 2e of the second semiconductor chip 2 and the corresponding substrate electrode 3e of the wiring board 3 are aligned (FIG. 2).
(D)).

Finally, the second semiconductor chip 2 is connected to the wiring board 3 (FIG. 2 (e)). Here, a connection is made between the second semiconductor chip 2 and the wiring board 3 by applying a load with a tool 4 via an anisotropic conductive film 2a ″ made of a connection structure 2a and a resin 2a ′. At this time, the first
After the connection of the conductive particles 1a used as the connection structure of the semiconductor chip 1 of FIG.
₁ is smaller than the thickness d _{2 of} the anisotropic conductive film 2a ″ used as the connection structure of the second semiconductor chip 2 after the connection, and the distance from the reference surface 3a of the wiring substrate 3 to the first semiconductor chip 1 distance h ₁ to the element surface 1f of smaller spacing h ₂ from the reference surface 3a of the wiring board 3 to the second element surface 2f of the semiconductor chip 2. That is, the second semiconductor from the reference surface 3a of the wiring board 3 The height H ₂ to the back surface 2r of the chip 2 is
The height from the reference surface 3a of the wiring board 3 to the back surface 1r of the first semiconductor chip 1 is higher than the height H ₁ , and the pressing surface of the tool 4 for pressing the second semiconductor chip 2 is the second semiconductor chip. The tool 4 does not hit the first semiconductor chip 1 even if the tool 4 is out of the range.

In the above-described embodiment, different connection structures for connecting the chip electrode of the semiconductor chip and the substrate electrode of the wiring board are used for the first chip and the second chip. You may use the method of changing the size, thickness, etc. of the connection structure by using the connection structure of, or by using the connection structure of the same kind and the same size, one side by high load etc. It is also possible to use a method of changing the connection condition of crushing considerably and crushing the other weakly by a low load or the like.

Third Embodiment FIGS. 3A to 3F are sectional views showing main steps of a third embodiment of the present invention. Here, a case is shown in which a plurality of semiconductor chips having bumps formed on chip electrodes are mounted on a wiring board.

First, the area 3h of the wiring board 3 for connecting the second semiconductor chip 2 is made higher than the reference surface 3a of the wiring board 3, and the wiring board 3 in which the wiring 3w, the electrode 3e, etc. are formed.
Are prepared (FIG. 3 (a)). Here, the insulating resin 3x is applied and cured in the area 3h of the wiring board 3 connecting the second semiconductor chip 2 to a height higher than the reference surface 3a of the wiring board 3 to form the wiring 3w and the electrode 3e. Although PWB3 was used, any ceramic substrate, glass substrate, or the like in which paste is thickened and co-fired may be used in this area.

Next, the first semiconductor chip 1 is prepared, and the chip electrode 1e of the first semiconductor chip 1 and the board electrode 3e corresponding to the wiring board 3 are aligned with each other (FIG. 3B).
Here, the semiconductor chip 1 in which the silicon semiconductor substrate 1s is used and the solder bumps 1a are formed on the chip electrodes 1e is used.

Next, the first semiconductor chip 1 is attached to the wiring board 3
Temporarily fix to (Fig. 3 (c)). Here, the tool 4 is used to temporarily press the semiconductor chip 1 against the wiring board 3 to temporarily fix it.

Next, a second semiconductor chip 2 having substantially the same thickness as the first semiconductor chip 2 is prepared, and the second semiconductor chip 2 is prepared.
Of the chip electrode 2e and the corresponding substrate electrode 3e of the wiring board 3
And are aligned (FIG. 3 (d)).

Next, the second semiconductor chip 2 is attached to the wiring board 3
Temporarily fix to (Fig. 3 (e)). Here, it is temporarily fixed in the same manner as in FIG. At this time, the area 3h of the wiring board 3 connecting the second semiconductor chip 2 is higher than the reference surface 3a of the wiring board 3, and therefore, from the reference surface 3a of the wiring board 3 to the back surface 2r of the second semiconductor chip 2. Height H
_{Since 2} is higher than the height H ₁ from the reference surface 3a of the wiring board 3 to the back surface 1r of the first semiconductor chip 1, the pressing surface of the tool 4 for pressing the second semiconductor chip 2 is the second semiconductor. The tool 4 does not hit the first semiconductor chip 1 even if the tool 4 protrudes from the chip 2. Finally the wiring board 3
Is reflowed to connect with the semiconductor chip (see FIG. 3).
(F)).

In the above-described embodiment, the wiring board in which the area of the wiring board to which the second semiconductor chip is connected is made higher than the reference plane of the wiring board is used. On the contrary, the first semiconductor chip is connected. A wiring board in which the area of the wiring board is lower than the reference plane of the wiring board may be used.

Further, in the above-mentioned embodiment, the solder bump is used as the connection structure, and the first bump is used to reduce the number of steps.
The semiconductor chip is temporarily fixed, the second semiconductor chip is temporarily fixed, and the first and second semiconductor chips are collectively connected by reflow. The first semiconductor chip is temporarily fixed and reflowed. The steps may be performed in the order of temporary fixing of the second semiconductor chip and connection by reflow.

Fourth Embodiment FIGS. 4A to 4C are sectional views showing main steps of an embodiment of the present invention. In the first to third embodiments described above, two semiconductor chips have been described, but here, the case of mounting using more semiconductor chips is shown. Further, the height of each semiconductor chip from the reference surface of the wiring board may be variously changed. There is a relationship of D ₁ <D ₂ <D ₃ among the thicknesses D ₁ , D ₂ and D ₃ of the semiconductor substrate, and the connection structures are made to have substantially the same size.

Firstly, the first thickness of the semiconductor substrate 1s is D ₁
The semiconductor chip group 1 is connected to the wiring board 3 (see FIG. 4).
(A)).

Next, the second semiconductor substrate 2s whose thickness is D ₁
The semiconductor chip group 2 is connected to the wiring board 3 (see FIG. 4).
(B)).

At this time, since there is a relation of D ₁ <D ₂ ,
The height from the reference surface 3a of the wiring board 3 to the back surfaces of the first and second semiconductor chips has a relationship of H ₁ <H ₂ , and the tool 4 for pressing the second semiconductor chip 2 is the first semiconductor chip. It does not hit 1.

Finally, the semiconductor substrate 5s has a _third thickness D 3
The semiconductor chip group 5 is connected to the wiring board 3 (see FIG. 4).
(C)). At this time, since the relationship of D ₁ <D ₂ <D ₃ is satisfied, the first, second and third parts from the reference surface 3 a of the wiring board 3
The height of each semiconductor chip to the back surface is H ₁ <
Since H ₂ <H ₃ , the tool 4 for pressing the third semiconductor chip 5 does not hit the first semiconductor chip 1 and the second semiconductor chip 2.

Fifth Embodiment FIG. 5 shows a sectional view of a semiconductor device according to a fifth embodiment of the present invention. Here, the first semiconductor chip 1 is mounted on the lower portion 3l of the wiring substrate 3 which is formed in a concave shape with respect to the reference surface 3a, and the back surface 1r thereof is mounted on the wiring substrate 3 by the second semiconductor chip 2. It is lower than the element surface 2f. The mounting method at this time can be any of the methods described in the first to fourth embodiments. In this case, the connection structure 2a is not directly short-circuited with the adjacent connection structure 1a even if the connection structure 2a is crushed, which is suitable for high-density mounting.

Sixth Embodiment FIG. 6 shows a sectional view and a plan view of a semiconductor device according to a sixth embodiment of the present invention. Here, the first semiconductor chip 1 is mounted on the reference surface 3a of the wiring board 3, and the second semiconductor chip 2 is mounted on the higher portion 3h of the wiring board 3 which is convexly formed than the reference surface 3a. Has been done. The back surface 1r of the semiconductor chip 1 is mounted lower than the element surface 2f of the semiconductor chip 2, and, as is clear from the drawing, the semiconductor chips are mounted so as to overlap each other when viewed in the planar direction. This case is particularly suitable for high-density mounting.

The present invention is not limited to the above embodiment, but various modifications can be made within the scope of the claims.

[0048]

As described above, according to the present invention, when the semiconductor chip is temporarily fixed or connected to the wiring board,
The height from the reference surface of the wiring board to the back surface of the semiconductor chip is different in the mounting structure of the adjacent semiconductor chips, and the second semiconductor chip is temporarily mounted next to the first semiconductor chip which is already temporarily fixed or connected. When attempting to stop or connect, the height from the reference surface of the wiring board to the back surface of the first semiconductor chip is lower than the height from the reference surface of the wiring board to the back surface of the second semiconductor chip. , First
The tool for connecting the second semiconductor chip does not come into contact with the back surface of the semiconductor chip. Therefore, it is possible to reduce the distance between adjacent semiconductor chips without changing the tool, and as a result, it is possible to improve the mounting density and electrical characteristics with high reliability.

Further, when the height to the back surface of the first semiconductor chip is set lower than the height to the element surface of the second semiconductor chip, a better effect can be obtained.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of main steps in a first embodiment.

FIG. 2 is a cross-sectional view of main steps in a second embodiment.

FIG. 3 is a sectional view of a main process in the third embodiment.

FIG. 4 is a sectional view of a main process in the fourth embodiment.

FIG. 5 is a sectional view of a semiconductor device according to a fifth embodiment.

FIG. 6 is a sectional view (a) and a plan view (b) of a semiconductor device according to a sixth embodiment.

FIG. 7 is a diagram for explaining a problem of the conventional technique.

FIG. 8 is a diagram for explaining a problem of another conventional technique.

[Explanation of symbols]

1 1st semiconductor chip 1s 1st semiconductor chip semiconductor substrate 1r 1st semiconductor chip back surface 1f 1st semiconductor chip element surface 1e 1st semiconductor chip chip electrode 1a 1st semiconductor chip connection structure Body 2 Second semiconductor chip 2s Semiconductor substrate of second semiconductor chip 2r Back surface of second semiconductor chip 2f Element surface of second semiconductor chip 2e Chip electrode of second semiconductor chip 2a Connection of second semiconductor chip Structure 3 Wiring board 3a Wiring board reference surface 3h Wiring board higher than reference surface 3l Wiring board lower than reference surface 3w Wiring board wiring 3e Wiring board substrate electrode 4 Tool 5 Third semiconductor chip 5s Semiconductor substrate of third semiconductor chip 5r Back surface of third semiconductor chip H Height from reference surface of wiring board to back surface of semiconductor chip Thickness after connection of the connecting structure of thickness d semiconductor chip height D semiconductor chip of the semiconductor substrate from the reference plane of the h wiring substrate to the element surface of the semiconductor chip

Claims (4)

[Claims] 1. In a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board by a face-down method, a reference of the wiring board is higher than a height from a reference surface of the wiring board to a back surface of the first semiconductor chip. The height from the surface to the back surface of the second semiconductor chip is high, and the height from the reference surface of the wiring board to the second semiconductor chip is higher than the height from the reference surface of the wiring board to the main surface of the first semiconductor chip. A mounting structure of a semiconductor device, characterized in that it has a high height to a main surface and is connected to the wiring board. 2. In a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down method, a reference of the wiring board is higher than a height from a reference surface of the wiring board to a back surface of the first semiconductor chip. A mounting structure of a semiconductor device, characterized in that the height from the surface to the main surface of the second semiconductor chip is high and is connected to the wiring board. 3. In a mounting structure of a semiconductor device in which a plurality of semiconductor chips are connected to a wiring board in a face-down method, a reference of the wiring board is higher than a height from a reference surface of the wiring board to a back surface of the first semiconductor chip. The height from the surface to the main surface of the second semiconductor chip is high, and the second semiconductor chip is partially connected to the wiring board so that the second semiconductor chip partially overlaps the first semiconductor chip. And a semiconductor device mounting structure. 4. The method of mounting a semiconductor device according to claim 1, 2, or 3, wherein the first semiconductor chip is connected to a wiring board, and then the second semiconductor chip is connected to the wiring board. A characteristic method of mounting a semiconductor device.