JPH04323838A - Method of mounting semiconductor element - Google Patents
Method of mounting semiconductor elementInfo
- Publication number
- JPH04323838A JPH04323838A JP9246891A JP9246891A JPH04323838A JP H04323838 A JPH04323838 A JP H04323838A JP 9246891 A JP9246891 A JP 9246891A JP 9246891 A JP9246891 A JP 9246891A JP H04323838 A JPH04323838 A JP H04323838A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- adhesive
- circuit board
- bump
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000000034 method Methods 0.000 title claims abstract description 25
- 239000000853 adhesive Substances 0.000 claims abstract description 28
- 230000001070 adhesive effect Effects 0.000 claims abstract description 28
- 125000006850 spacer group Chemical group 0.000 claims abstract description 11
- 238000009792 diffusion process Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004840 adhesive resin Substances 0.000 description 2
- 229920006223 adhesive resin Polymers 0.000 description 2
- 238000001723 curing Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
Abstract
Description
【0001】0001
【産業上の利用分野】本発明は、ワイヤレスボンディン
グ法による回路基板上への半導体素子(ICチップ)の
実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor element (IC chip) on a circuit board using a wireless bonding method.
【0002】0002
【従来の技術】従来、このような分野の技術としては、
例えば特開昭62−244142号に記載されるものが
あった。図3は従来の半導体素子のAuバンプの形成工
程断面図である。まず、図3(a)に示すように、半導
体素子1上に、例えばAlから成る電極パッド2、及び
パッシベーション膜3を形成する。[Prior Art] Conventionally, technologies in this field include:
For example, there was one described in JP-A-62-244142. FIG. 3 is a cross-sectional view of a conventional process for forming Au bumps on a semiconductor device. First, as shown in FIG. 3A, electrode pads 2 made of, for example, Al and a passivation film 3 are formed on a semiconductor element 1.
【0003】次に、この上に、図3(b)に示すように
、例えば真空蒸着法等により、Ti−Pt,Au等を順
次積層し、拡散制御層4、バンプ接合層5を形成する。
次に、その上に、図3(c)に示すように、液状フォト
レジスト6をスピナ等で塗布し、半導体素子1の配線に
おける電極パッド2の上部のみ、所望の大きさのバンプ
径をパターニング開孔する。Next, as shown in FIG. 3(b), Ti--Pt, Au, etc. are sequentially laminated thereon by, for example, vacuum evaporation to form a diffusion control layer 4 and a bump bonding layer 5. . Next, as shown in FIG. 3(c), a liquid photoresist 6 is applied using a spinner or the like, and a bump diameter of a desired size is patterned only on the upper part of the electrode pad 2 in the wiring of the semiconductor element 1. Open a hole.
【0004】次に、図3(d)に示すように、このフォ
トレジスト6をめっきマスクとし、拡散制御層4、バン
プ接合層5を電解めっきの一方の陰極として開孔し、露
出したパッド上部のバンプ接合層5上のみ選択的にバン
プ7(ここではAu)を析出させる。その後、図3(e
)に示すように、フォトレジスト6を除去し、バンプ7
をマスクとしてパッド上部以外の拡散制御層4、バンプ
接合層5をエッチング除去する。なお、必要な場合には
拡散制御層4の接触抵抗の低減を目的として熱処理を行
なう。Next, as shown in FIG. 3(d), using this photoresist 6 as a plating mask, holes are opened in the diffusion control layer 4 and the bump bonding layer 5 as one cathode for electrolytic plating, and the exposed upper part of the pad is opened. The bumps 7 (here, Au) are selectively deposited only on the bump bonding layer 5. After that, Fig. 3(e)
), the photoresist 6 is removed and the bump 7 is removed.
Using this as a mask, the diffusion control layer 4 and bump bonding layer 5 other than the upper part of the pad are removed by etching. Note that, if necessary, heat treatment is performed for the purpose of reducing the contact resistance of the diffusion control layer 4.
【0005】このようにして形成されたバンプを有する
半導体素子を回路基板へ実装する工程について図4を用
いて説明する。まず、図4(a)に示すように、バンプ
7を有する半導体素子8を用意する。次に、図4(b)
に示すように、バンプ7上に、例えばAgペースト9の
ような導電性接着樹脂を塗布する。The process of mounting a semiconductor element having bumps formed in this way onto a circuit board will be described with reference to FIG. First, as shown in FIG. 4(a), a semiconductor element 8 having bumps 7 is prepared. Next, Figure 4(b)
As shown in FIG. 2, a conductive adhesive resin such as Ag paste 9 is applied onto the bumps 7.
【0006】次いで、図4(c)に示すように、回路基
板10上の回路基板電極11の上にバンプ7がくるよう
に位置合わせをして、加圧しながら若干の熱をかけて、
Agペースト9を硬化させる。このようにして、Agペ
ースト9を介してバンプ7と回路基板電極11は接続さ
れ、半導体素子の実装工程が完了する。Next, as shown in FIG. 4(c), the bumps 7 are aligned so that they are above the circuit board electrodes 11 on the circuit board 10, and a little heat is applied while applying pressure.
The Ag paste 9 is cured. In this way, the bumps 7 and the circuit board electrodes 11 are connected via the Ag paste 9, and the semiconductor element mounting process is completed.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上記し
たようにバンプ上面がAgペースト9により半球状とな
るためバンプ7と回路基板電極11を接合するに際し、
バンプ7と回路基板電極11との接合面積のバラツキ、
接合時のAgペーストの広がりによる接合不良発生の原
因となっていた。また、隣接するバンプと短絡する恐れ
があるため、パッドピッチの縮小化の障害となっていた
。[Problems to be Solved by the Invention] However, as described above, since the top surface of the bump is made into a hemispherical shape by the Ag paste 9, when bonding the bump 7 and the circuit board electrode 11,
Variations in the bonding area between the bumps 7 and the circuit board electrodes 11;
Spreading of the Ag paste during bonding caused bonding failures. In addition, there is a risk of short-circuiting with adjacent bumps, which has been an obstacle to reducing the pad pitch.
【0008】本発明は、上記問題点を除去し、接合時の
接着剤の広がりによる接続不良の発生を防ぎ、かつパッ
ドピッチの縮小化を図り得る半導体素子の実装方法を提
供することを目的とする。SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device mounting method that can eliminate the above-mentioned problems, prevent connection failures due to spread of adhesive during bonding, and reduce pad pitch. do.
【0009】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために、ワイヤレスボンディング法による回路基
板上への半導体素子の実装方法において、接着剤にスペ
ーサを入れる工程と、その接着剤を半導体素子のバンプ
表面に塗布する工程と、その接着剤を介して回路基板上
に半導体素子を実装する工程とを施すようにしたもので
ある。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for mounting a semiconductor element on a circuit board using a wireless bonding method, which includes a step of inserting a spacer into an adhesive, and a step of adding a spacer to an adhesive. The adhesive is applied to the bump surface of a semiconductor element, and the semiconductor element is mounted on a circuit board using the adhesive.
【0010】0010
【作用】本発明によれば、ワイヤレスボンディング法に
よる回路基板上への半導体素子の実装方法において、接
着剤にスペーサを入れ、その接着剤を半導体素子のバン
プ表面に塗布し、その接着剤を介して回路基板の電極上
に半導体素子のバンプを接続し、回路基板上へ半導体素
子を実装する。[Operation] According to the present invention, in a method for mounting a semiconductor element on a circuit board using the wireless bonding method, a spacer is inserted into an adhesive, the adhesive is applied to the bump surface of the semiconductor element, and the adhesive is applied to the bump surface of the semiconductor element. Then, the bumps of the semiconductor element are connected to the electrodes of the circuit board, and the semiconductor element is mounted on the circuit board.
【0011】従って、接合時の接着剤の広がりによる接
続不良の発生を防ぐとともに、パッドピッチの縮小化を
図ることができる。[0011] Therefore, it is possible to prevent connection failures due to spread of adhesive during bonding, and to reduce the pad pitch.
【0012】0012
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図1は本発明の実施例を示すワ
イヤレスボンディング法による半導体素子の実装工程断
面図である。まず、図1(a)に示すように、バンプ2
2が形成された半導体素子21を、導電接着樹脂、例え
ばAgペースト23にスペーサ24(数千Å〜数μm)
をまぜた接着剤25上に位置させる。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of a mounting process of a semiconductor element by a wireless bonding method, showing an embodiment of the present invention. First, as shown in FIG. 1(a), bump 2
The semiconductor element 21 on which 2 is formed is bonded to a conductive adhesive resin such as Ag paste 23 with spacers 24 (several thousand Å to several μm).
Place it on top of the mixed adhesive 25.
【0013】次に、図1(b)に示すように、バンプ2
2表面上に接着剤25を付着させる。この時、バンプ2
2表面以外の部分に接着剤25がつかないようにする。
次に、図1(c)に示すように、接着剤25のついた半
導体素子21を周知の方法にて位置合わせをして、回路
基板26上の電極27上にバンプ22を位置決めする。Next, as shown in FIG. 1(b), the bump 2
Adhesive 25 is applied onto the 2 surfaces. At this time, bump 2
2. Prevent the adhesive 25 from getting on parts other than the surface. Next, as shown in FIG. 1C, the semiconductor element 21 with the adhesive 25 attached thereto is aligned using a well-known method, and the bumps 22 are positioned on the electrodes 27 on the circuit board 26.
【0014】次に、図1(d)に示すように、回路基板
26上の電極27上に、接着剤25のついた半導体素子
21のバンプ22を加圧しながら熱を加えて硬化させる
。このように構成することにより、図2(b)に示すよ
うに、回路基板の電極とバンプは、Agペーストを介し
て、確実に電気的接続を行うことができ、回路基板への
半導体素子の実装を行うことができる。ここで、接着剤
25はスペーサ24を混入させているため、スペーサ2
4を入れない従来の場合と比較して、広がり幅が小さく
なる。Next, as shown in FIG. 1(d), the bumps 22 of the semiconductor element 21 with the adhesive 25 on them are hardened by applying heat while pressurizing them onto the electrodes 27 on the circuit board 26. With this configuration, as shown in FIG. 2(b), the electrodes and bumps of the circuit board can be reliably electrically connected via the Ag paste, and the semiconductor element can be connected to the circuit board. Implementation can be done. Here, since the adhesive 25 contains the spacer 24, the spacer 24
Compared to the conventional case where 4 is not included, the spread width is smaller.
【0015】図2は半導体素子の実装時における接合部
の拡大断面図であり、図2(a)は従来の半導体素子の
接続断面図、図2(b)は本発明における半導体素子の
接続断面図である。図2(a)において、Agペースト
9の広がり幅をa、バンプ底面と電極上面の間隔(また
は高さ)をa′とする。図2(b)おいて、接着剤25
の広がり幅をb、バンプ底面と電極上面の間隔(または
高さ)をb′とする。FIG. 2 is an enlarged cross-sectional view of a bonding part during mounting of a semiconductor element, FIG. 2(a) is a cross-sectional view of a conventional semiconductor element, and FIG. 2(b) is a cross-sectional view of a semiconductor element according to the present invention. It is a diagram. In FIG. 2A, the spread width of the Ag paste 9 is a, and the distance (or height) between the bottom surface of the bump and the top surface of the electrode is a'. In FIG. 2(b), the adhesive 25
The width of the bump is b, and the distance (or height) between the bottom surface of the bump and the top surface of the electrode is b'.
【0016】図2(b)の接着剤25にはスペーサ24
を混入させているため、上記四つのパラメータの間には
、
a>b・・・・・(1)
a′<b′・・・(2)
の不等式が成り立つ。この不等式が成り立つならば、接
合不良発生は減少し、パッドピッチはより縮小化できる
。A spacer 24 is attached to the adhesive 25 in FIG. 2(b).
are mixed, the following inequalities hold between the above four parameters: a>b...(1) a'<b'...(2). If this inequality holds true, the occurrence of bonding defects will be reduced and the pad pitch can be further reduced.
【0017】なお、使用する接着剤及び硬化方法は、上
記熱硬化形以外、例えば紫外線硬化型を用いても、同様
の作用効果を奏することができる。また、本発明は上記
実施例に限定されるものではなく、本発明の趣旨に基づ
いて種々の変形が可能であり、これらを本発明の範囲か
ら排除するものではない。[0017] The adhesive and curing method used may be other than the above-mentioned thermosetting type, for example, an ultraviolet curing type may be used to achieve the same effect. Further, the present invention is not limited to the above embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【0018】[0018]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、次のような効果を奏することができる。回路基
板上の半導体素子の実装方法において、半導体素子のバ
ンプと回路基板の電極とを接続するにあたり、例えばA
gペーストのような接着剤にスペーサを混入させたもの
をバンプ表面に塗布して、接続を行うようにしたので、
接合時の接着剤の広がりによる接続不良の発生を防ぐこ
とができる。As described in detail above, according to the present invention, the following effects can be achieved. In a method for mounting a semiconductor element on a circuit board, when connecting bumps on the semiconductor element and electrodes on the circuit board, for example, A
I applied an adhesive such as g-paste mixed with a spacer to the bump surface to make the connection.
It is possible to prevent connection failures due to spread of adhesive during bonding.
【0019】また、パッドピッチの縮小化を図ることが
できる。Furthermore, the pad pitch can be reduced.
【図1】本発明の実施例を示すワイヤレスボンディング
法による半導体素子の実装工程断面図である。FIG. 1 is a cross-sectional view of a semiconductor element mounting process by a wireless bonding method showing an embodiment of the present invention.
【図2】半導体素子の実装時における接合部の拡大断面
図である。FIG. 2 is an enlarged cross-sectional view of a bonding portion when a semiconductor element is mounted.
【図3】従来の半導体素子のAuバンプの形成工程断面
図である。FIG. 3 is a cross-sectional view of a conventional process for forming Au bumps on a semiconductor device.
【図4】従来のバンプを有する半導体素子の回路基板へ
の実装工程断面図である。FIG. 4 is a cross-sectional view of a conventional mounting process of a semiconductor element having bumps on a circuit board.
21 半導体素子 22 バンプ 23 Agペースト 24 スペーサ 25 接着剤 26 回路基板 27 電極 21 Semiconductor device 22 Bump 23 Ag paste 24 Spacer 25 Adhesive 26 Circuit board 27 Electrode
Claims (1)
基板上への半導体素子の実装方法において、(a)接着
剤にスペーサを入れる工程と、(b)その接着剤を半導
体素子のバンプ表面に塗布する工程と、(c)その接着
剤を介して回路基板上に半導体素子を実装する工程とを
施すことを特徴とする半導体素子の実装方法。1. A method for mounting a semiconductor element on a circuit board using a wireless bonding method, comprising: (a) adding a spacer to an adhesive; (b) applying the adhesive to a bump surface of a semiconductor element. (c) mounting the semiconductor element on a circuit board via the adhesive.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9246891A JPH04323838A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9246891A JPH04323838A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04323838A true JPH04323838A (en) | 1992-11-13 |
Family
ID=14055174
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9246891A Withdrawn JPH04323838A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04323838A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5838061A (en) * | 1996-03-11 | 1998-11-17 | Lg Semicon Co., Ltd. | Semiconductor package including a semiconductor chip adhesively bonded thereto |
US5965866A (en) * | 1995-04-05 | 1999-10-12 | Orga Kartensysteme Gmbh | Pass card having a semiconductor chip module attached by a microencapsulated adhesive |
US6720645B2 (en) * | 2002-05-16 | 2004-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor device |
-
1991
- 1991-04-24 JP JP9246891A patent/JPH04323838A/en not_active Withdrawn
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5965866A (en) * | 1995-04-05 | 1999-10-12 | Orga Kartensysteme Gmbh | Pass card having a semiconductor chip module attached by a microencapsulated adhesive |
US5838061A (en) * | 1996-03-11 | 1998-11-17 | Lg Semicon Co., Ltd. | Semiconductor package including a semiconductor chip adhesively bonded thereto |
US6720645B2 (en) * | 2002-05-16 | 2004-04-13 | Oki Electric Industry Co., Ltd. | Semiconductor device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980711 |