JPH04323840A - Method of mounting semiconductor element - Google Patents
Method of mounting semiconductor elementInfo
- Publication number
- JPH04323840A JPH04323840A JP3092471A JP9247191A JPH04323840A JP H04323840 A JPH04323840 A JP H04323840A JP 3092471 A JP3092471 A JP 3092471A JP 9247191 A JP9247191 A JP 9247191A JP H04323840 A JPH04323840 A JP H04323840A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- semiconductor element
- bump
- forming
- adhesive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 238000000034 method Methods 0.000 title claims abstract description 40
- 239000000853 adhesive Substances 0.000 claims abstract description 19
- 230000001070 adhesive effect Effects 0.000 claims abstract description 19
- 239000002904 solvent Substances 0.000 claims abstract description 5
- 238000002844 melting Methods 0.000 abstract 1
- 230000008018 melting Effects 0.000 abstract 1
- 230000015572 biosynthetic process Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- YMWUJEATGCHHMB-UHFFFAOYSA-N Dichloromethane Chemical compound ClCCl YMWUJEATGCHHMB-UHFFFAOYSA-N 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 238000007740 vapor deposition Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000002313 adhesive film Substances 0.000 description 1
- 239000004840 adhesive resin Substances 0.000 description 1
- 229920006223 adhesive resin Polymers 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000007738 vacuum evaporation Methods 0.000 description 1
- 125000000391 vinyl group Chemical group [H]C([*])=C([H])[H] 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
Abstract
Description
【０００１】0001
【産業上の利用分野】本発明は、ワイヤレスボンディン
グ法による回路基板上への半導体素子（ＩＣチップ）の
実装方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of mounting a semiconductor element (IC chip) on a circuit board using a wireless bonding method.
【０００２】0002
【従来の技術】従来、このような分野の技術としては、
例えば特開昭６２−２４４１４２号に記載されるものが
あった。図３は従来の半導体素子のＡｕバンプの形成工
程断面図である。まず、図３（ａ）に示すように、半導
体素子１上に、例えばＡｌから成る電極パッド２、及び
パッシベーション膜３を形成する。[Prior Art] Conventionally, technologies in this field include:
For example, there was one described in JP-A-62-244142. FIG. 3 is a cross-sectional view of a conventional process for forming Au bumps on a semiconductor device. First, as shown in FIG. 3A, electrode pads 2 made of, for example, Al and a passivation film 3 are formed on a semiconductor element 1.
【０００３】次に、この上に、図３（ｂ）に示すように
、例えば真空蒸着法等により、Ｔｉ−Ｐｔ，Ａｕ等を順
次積層し、拡散制御層４、バンプ接合層５を形成する。
次に、その上に、図３（ｃ）に示すように、液状フォト
レジスト６をスピナ等で塗布し、半導体素子１の配線に
おける電極パッド２の上部のみ、所望の大きさのバンプ
径をパターニング開孔する。Next, as shown in FIG. 3(b), Ti--Pt, Au, etc. are sequentially laminated thereon by, for example, vacuum evaporation to form a diffusion control layer 4 and a bump bonding layer 5. . Next, as shown in FIG. 3(c), a liquid photoresist 6 is applied using a spinner or the like, and a bump diameter of a desired size is patterned only on the upper part of the electrode pad 2 in the wiring of the semiconductor element 1. Open a hole.
【０００４】次に、図３（ｄ）に示すように、このフォ
トレジスト６をめっきマスクとし、拡散制御層４、バン
プ接合層５を電解めっきの一方の陰極として開孔し、露
出したパッド上部のバンプ接合層５上のみ選択的にバン
プ７（ここではＡｕ）を析出させる。この後、図３（ｅ
）に示すように、フォトレジスト６を除去し、バンプ７
をマスクとしてパッド上部以外の拡散制御層４、バンプ
接合層５をエッチング除去する。なお、必要な場合には
拡散制御層４の接触抵抗の低減を目的として熱処理を行
なう。Next, as shown in FIG. 3(d), using this photoresist 6 as a plating mask, holes are opened in the diffusion control layer 4 and the bump bonding layer 5 as one cathode for electrolytic plating, and the exposed upper part of the pad is opened. The bumps 7 (here, Au) are selectively deposited only on the bump bonding layer 5. After this, Figure 3 (e
), the photoresist 6 is removed and the bump 7 is removed.
Using this as a mask, the diffusion control layer 4 and bump bonding layer 5 other than the upper part of the pad are removed by etching. Note that, if necessary, heat treatment is performed for the purpose of reducing the contact resistance of the diffusion control layer 4.
【０００５】このようにして形成されたバンプを有する
半導体素子を回路基板へ実装する工程について図４を用
いて説明する。まず、図４（ａ）に示すように、バンプ
７を有する半導体素子８を用意する。次に、図４（ｂ）
に示すように、バンプ７上に、例えばＡｇペースト９の
ような導電性接着樹脂を塗布する。The process of mounting a semiconductor element having bumps formed in this way onto a circuit board will be described with reference to FIG. First, as shown in FIG. 4(a), a semiconductor element 8 having bumps 7 is prepared. Next, Figure 4(b)
As shown in FIG. 2, a conductive adhesive resin such as Ag paste 9 is applied onto the bumps 7.
【０００６】次いで、図４（ｃ）に示すように、回路基
板１０上の回路基板電極１１の上にバンプ７がくるよう
に位置合わせをして、加圧しながら若干の熱をかけて、
Ａｇペースト９を硬化させる。このようにして、Ａｇペ
ースト９を介してバンプ７と回路基板電極１１は接続さ
れ、半導体素子の実装工程が完了する。Next, as shown in FIG. 4(c), the bumps 7 are aligned so that they are above the circuit board electrodes 11 on the circuit board 10, and a little heat is applied while applying pressure.
The Ag paste 9 is cured. In this way, the bumps 7 and the circuit board electrodes 11 are connected via the Ag paste 9, and the semiconductor element mounting process is completed.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、上記し
たようにバンプ上面がＡｇペースト９により半球状とな
るため、バンプ７と回路基板１０の回路基板電極１１を
接合するに際し、バンプ７と回路基板１０の回路基板電
極１１との接合面積のバラツキ、接合時のＡｇペースト
９の広がりによる接合不良発生の原因となっていた。ま
た、隣接するバンプと短絡する恐れがあるため、パッド
ピッチの縮小化の障害となっていた。[Problems to be Solved by the Invention] However, as described above, the upper surface of the bump is made into a hemispherical shape by the Ag paste 9, so when bonding the bump 7 and the circuit board electrode 11 of the circuit board 10, it is difficult to This was due to variations in the bonding area with the circuit board electrodes 11 and the spread of the Ag paste 9 during bonding, causing bonding failures. In addition, there is a risk of short-circuiting with adjacent bumps, which has been an obstacle to reducing the pad pitch.
【０００８】本発明は、上記問題点を除去し、接合時の
接着剤の広がりによる接続不良の発生を防ぐとともに、
パッドピッチの縮小化を図り得る半導体素子の実装方法
を提供することを目的とする。The present invention eliminates the above-mentioned problems, prevents the occurrence of connection failures due to the spread of adhesive during bonding, and
It is an object of the present invention to provide a method for mounting a semiconductor element that can reduce the pad pitch.
【０００９】[0009]
【課題を解決するための手段】本発明は、上記目的を達
成するために、ワイヤレスボンディング法による回路基
板上への半導体素子の実装方法において、回路基板に回
路基板電極を形成する工程と、その上にフィルムを形成
する工程と、半導体素子にバンプを形成する工程と、バ
ンプ先端にフィルムを溶かす溶剤を混ぜた接着剤を塗布
し、半導体素子と回路基板を接続するようにしたもので
ある。[Means for Solving the Problems] In order to achieve the above object, the present invention provides a method for mounting a semiconductor element on a circuit board by a wireless bonding method, which includes a step of forming a circuit board electrode on the circuit board, and a step of forming a circuit board electrode on the circuit board. The process involves forming a film on the semiconductor element, forming bumps on the semiconductor element, and applying an adhesive mixed with a solvent that dissolves the film to the tips of the bumps to connect the semiconductor element and the circuit board.
【００１０】また、回路基板に回路基板電極を形成する
工程と、その上に前記回路基板電極に対応する部位に導
電部を有するフィルムを形成する工程と、半導体素子に
バンプを形成する工程と、該バンプ先端に接着剤を塗布
する工程と、半導体素子と回路基板を接続する工程とを
施すようにしたものである。[0010] Also, a step of forming a circuit board electrode on the circuit board, a step of forming a film having a conductive portion at a portion corresponding to the circuit board electrode thereon, and a step of forming a bump on the semiconductor element, The process includes a process of applying an adhesive to the tips of the bumps and a process of connecting the semiconductor element and the circuit board.
【００１１】[0011]
【作用】本発明によれば、上記したように構成すること
により、回路基板は絶縁性フィルムで覆われ、半導体素
子のバンプと回路基板電極とは確実に接続を行なうこと
ができると共に、パッドピッチの縮小化を図ることがで
きる。また、半導体素子のバンプと回路基板電極との接
続部分の周囲は絶縁体の壁が形成されることにより、接
続部における接着剤の流れ出しを防止することができる
。[Operation] According to the present invention, with the above-described structure, the circuit board is covered with an insulating film, and the bumps of the semiconductor element and the circuit board electrodes can be reliably connected, and the pad pitch is It is possible to reduce the size of the image. Further, by forming an insulating wall around the connecting portion between the bump of the semiconductor element and the circuit board electrode, it is possible to prevent the adhesive from flowing out at the connecting portion.
【００１２】0012
【実施例】以下、本発明の実施例について図面を参照し
ながら詳細に説明する。図１は本発明の実施例を示す半
導体素子の実装工程断面図である。まず、図１（ａ）に
示すように、回路基板２１上に回路基板電極２２を形成
する。形成方法としては、スパッタリング、蒸着、ＣＶ
Ｄ等の装置によって成膜を行い、ホトリソ工程により加
工を行なう。Embodiments Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a cross-sectional view of a semiconductor device mounting process showing an embodiment of the present invention. First, as shown in FIG. 1(a), a circuit board electrode 22 is formed on a circuit board 21. As shown in FIG. Formation methods include sputtering, vapor deposition, CV
Film formation is performed using a device such as D, and processing is performed using a photolithography process.
【００１３】次いで、図１（ｂ）に示すように、例えば
、ビニールのような絶縁性フィルム２３を回路基板２１
全面に形成する。形成方法としはスパッタリング、蒸着
、ＣＶＤ等の装置により形成しても良いし、印刷法にて
形成しても良い。厚さは数千Å〜数十μｍである。次に
、図１（ｃ）に示すように、半導体素子２４に、例えば
、前記した従来の図３に示す方法により、バンプ２５を
形成する。このバンプの高さは、絶縁性フィルム２３の
高さよりより大きい。Next, as shown in FIG. 1(b), an insulating film 23 made of vinyl, for example, is attached to the circuit board 21.
Form on the entire surface. As for the formation method, it may be formed by a device such as sputtering, vapor deposition, or CVD, or it may be formed by a printing method. The thickness is from several thousand Å to several tens of μm. Next, as shown in FIG. 1C, bumps 25 are formed on the semiconductor element 24 by, for example, the above-described conventional method shown in FIG. The height of this bump is greater than the height of the insulating film 23.
【００１４】次いで、図１（ｄ）に示すように、接着剤
２６をバンプ先端に均一につける。ここで、接着剤２６
には、熱硬化型接着剤に絶縁性フィルム２３を溶かす塩
化メチレン等を混ぜておく。次に、図１（ｅ）に示すよ
うに、半導体素子２４と回路基板２１の位置合わせを行
い、バンプ２５が回路基板の回路基板電極２２上にくる
ようにする。Next, as shown in FIG. 1(d), adhesive 26 is applied uniformly to the tip of the bump. Here, the adhesive 26
In this step, methylene chloride or the like that dissolves the insulating film 23 is mixed into the thermosetting adhesive. Next, as shown in FIG. 1E, the semiconductor element 24 and the circuit board 21 are aligned so that the bumps 25 are placed on the circuit board electrodes 22 of the circuit board.
【００１５】次に、図１（ｆ）に示すように、加圧する
と共に、熱を加えることにより、半導体素子の実装工程
が完了する。このように構成することにより、図２に示
すように、絶縁性フィルム２３はバンプ２５により潰さ
れて、バンプ２５と回路基板２１上の回路基板電極２２
とは電気的に接続される。ここで、ａは絶縁性フィルム
２３の高さ、ｂはバンプ２５の高さを示し、ａ＞ｂの関
係が成り立つ。Next, as shown in FIG. 1(f), the semiconductor element mounting process is completed by applying pressure and heat. With this configuration, as shown in FIG. 2, the insulating film 23 is crushed by the bumps 25, and the bumps 25 and the circuit board electrodes 22 on the circuit board 21
is electrically connected to. Here, a represents the height of the insulating film 23, b represents the height of the bump 25, and the relationship a>b holds true.
【００１６】次に、本発明の他の実施例について図５を
参照しながら説明する。図５は本発明の他の実施例を示
す半導体素子の実装工程断面図である。まず、図５（ａ
）に示すように、回路基板３１上に電極３２を形成する
。次に、図５（ｂ）に示すように、例えば、所定の箇所
に導電性を有する導電部３４が形成された絶縁性フィル
ム３３、例えば、導電性を有し、かつ粘着性のある例え
ばのりに金属を混ぜたような導電部３４と、それ以外の
部分は絶縁性フィルム３３を基板上に形成する。形成方
法は、蒸着、スパッタ等で成膜し、フォトリソ加工を２
回行なっても良いし、厚膜印刷を２回行なっても良い。Next, another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a cross-sectional view of a semiconductor device mounting process showing another embodiment of the present invention. First, Figure 5 (a
), an electrode 32 is formed on a circuit board 31. Next, as shown in FIG. 5(b), for example, an insulating film 33 having a conductive part 34 formed at a predetermined location, for example, an adhesive film 33 having conductivity and adhesive, for example, is applied. A conductive portion 34 made of a mixture of metal and an insulating film 33 is formed on the substrate. The formation method is to form a film by vapor deposition, sputtering, etc., and then photolithography process.
The printing may be performed twice, or the thick film printing may be performed twice.
【００１７】次いで、図５（ｃ）に示すように、半導体
素子３５にバンプ３６を形成する。このバンプ３６の高
さは、絶縁性フィルム３３の高さよりは大きい。次いで
、図５（ｄ）に示すように、半導体素子３５のバンプ３
６表面に接着剤３７をバンプ先端に均一につける。次い
で、図５（ｅ）に示すように、半導体素子３５と回路基
板３１の位置合わせを行い、バンプ３６が回路基板の回
路基板電極３２上にくるようにする。Next, as shown in FIG. 5(c), bumps 36 are formed on the semiconductor element 35. The height of this bump 36 is greater than the height of the insulating film 33. Next, as shown in FIG. 5(d), the bumps 3 of the semiconductor element 35 are
6. Apply adhesive 37 evenly to the tip of the bump on the surface. Next, as shown in FIG. 5E, the semiconductor element 35 and the circuit board 31 are aligned so that the bumps 36 are placed on the circuit board electrodes 32 of the circuit board.
【００１８】次に、図５（ｆ）に示すように、加圧する
と共に、熱を加えることにより、半導体素子の実装工程
が完了する。このように構成することにより、図６に示
すように、半導体素子３５のバンプ３６と回路基板３１
の回路基板電極３２とは電気的に確実に接続することが
できる。ここで、ａ′は絶縁性フィルム３３の高さ、ｂ
′はバンプ３６の高さを示しており、ａ′＞ｂ′の関係
が成り立つ。Next, as shown in FIG. 5(f), the semiconductor element mounting process is completed by applying pressure and heat. With this configuration, as shown in FIG. 6, the bumps 36 of the semiconductor element 35 and the circuit board 31
The circuit board electrode 32 can be electrically connected reliably. Here, a' is the height of the insulating film 33, and b
' indicates the height of the bump 36, and the relationship a'>b' holds true.
【００１９】なお、上記実施例において使用した熱硬化
型樹脂接着剤に代えて紫外線硬化型樹脂等を用いても同
様の効果を奏することができる。また、上記した各実施
例においてバンプと回路基板電極の接合部分の回りには
、絶縁性フィルムの壁が形成されるために、導電性接着
剤の流れ出しを防ぐことができる。Note that the same effect can be obtained by using an ultraviolet curable resin or the like in place of the thermosetting resin adhesive used in the above embodiments. Further, in each of the above-described embodiments, a wall of an insulating film is formed around the bonding portion between the bump and the circuit board electrode, so that it is possible to prevent the conductive adhesive from flowing out.
【００２０】なお、本発明は上記実施例に限定されるも
のではなく、本発明の趣旨に基づいて種々の変形が可能
であり、これらを本発明の範囲から排除するものではな
い。It should be noted that the present invention is not limited to the above-mentioned embodiments, and various modifications can be made based on the spirit of the present invention, and these are not excluded from the scope of the present invention.
【００２１】[0021]
【発明の効果】以上、詳細に説明したように、本発明に
よれば、次のような効果を奏することができる。ワイヤ
レスボンディング法による回路基板上への半導体素子の
実装方法において、回路基板に電極を形成し、その上に
絶縁性フィルムを形成し、半導体素子にバンプを形成し
、該バンプ先端にフィルムを溶かす溶剤を混ぜた接着剤
を塗布し、半導体素子と回路基板を接続する。また、回
路基板に電極を形成し、その上に前記電極に対応する部
位に導電部を有するフィルムを形成し、半導体素子にバ
ンプを形成し、該バンプ先端にフィルムを溶かす溶剤を
混ぜた接着剤を塗布し、半導体素子と回路基板を接続す
るようにしたので、回路基板は絶縁性フィルムで覆われ
、半導体素子のバンプと回路基板電極とは確実に接続を
行なうことができると共に、パッドピッチの縮小化を図
ることができる。As described in detail above, according to the present invention, the following effects can be achieved. In a method for mounting a semiconductor element on a circuit board using the wireless bonding method, an electrode is formed on the circuit board, an insulating film is formed on the electrode, a bump is formed on the semiconductor element, and a solvent is used to dissolve the film at the tip of the bump. Apply a mixture of adhesives and connect the semiconductor element and circuit board. In addition, an electrode is formed on a circuit board, a film having a conductive part is formed on the circuit board at a portion corresponding to the electrode, a bump is formed on the semiconductor element, and an adhesive mixed with a solvent that dissolves the film is applied to the tip of the bump. The circuit board is covered with an insulating film, and the bumps on the semiconductor element and the circuit board electrodes can be reliably connected, and the pad pitch can be adjusted. It is possible to reduce the size.
【００２２】また、半導体素子のバンプと回路基板電極
との接続部分の周囲は絶縁体の壁が形成されることによ
り、接続部の接着剤の流れ出しを防止することができる
。Furthermore, by forming an insulating wall around the connecting portion between the bump of the semiconductor element and the circuit board electrode, it is possible to prevent the adhesive at the connecting portion from flowing out.
【図１】本発明の実施例を示す半導体素子の実装工程断
面図である。FIG. 1 is a cross-sectional view of a semiconductor device mounting process showing an embodiment of the present invention.
【図２】本発明の実施例を示す半導体素子の接続部分の
拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a connecting portion of a semiconductor element showing an embodiment of the present invention.
【図３】従来の半導体素子のＡｕバンプの形成工程断面
図である。FIG. 3 is a cross-sectional view of a conventional process for forming Au bumps on a semiconductor device.
【図４】従来のバンプを有する半導体素子の回路基板へ
の実装工程断面図である。FIG. 4 is a cross-sectional view of a conventional mounting process of a semiconductor element having bumps on a circuit board.
【図５】本発明の他の実施例を示す半導体素子の実装工
程断面図である。FIG. 5 is a cross-sectional view of a semiconductor device mounting process showing another embodiment of the present invention.
【図６】本発明の他の実施例を示す半導体素子の接続部
分の拡大断面図である。FIG. 6 is an enlarged sectional view of a connecting portion of a semiconductor element showing another embodiment of the present invention.
２１，３１ 回路基板 ２２，３２ 回路基板電極 ２３，３３ 絶縁性フィルム ２４，３５ 半導体素子 ２５，３６ バンプ ２６，３７ 接着剤 ３３ 絶縁性フィルム ３４ 導電部 21, 31 Circuit board 22, 32 Circuit board electrode 23, 33 Insulating film 24, 35 Semiconductor element 25, 36 Bump 26, 37 Adhesive 33 Insulating film 34 Conductive part
Claims (2)
基板上への半導体素子の実装方法において、（ａ）回路
基板に回路基板電極を形成する工程と、（ｂ）その上に
フィルムを形成する工程と、（ｃ）半導体素子にバンプ
を形成する工程と、（ｄ）該バンプ先端にフィルムを溶
かす溶剤を混ぜた接着剤を塗布する工程と、（ｅ）前記
半導体素子と前記回路基板を接続する工程とを施すこと
を特徴とする半導体素子の実装方法。1. A method for mounting a semiconductor element on a circuit board using a wireless bonding method, comprising: (a) forming a circuit board electrode on the circuit board; (b) forming a film thereon; c) forming a bump on the semiconductor element; (d) applying an adhesive mixed with a solvent that dissolves the film to the tip of the bump; and (e) connecting the semiconductor element and the circuit board. 1. A method for mounting a semiconductor element, characterized in that:
基板上への半導体素子の実装方法において、（ａ）回路
基板に回路基板電極を形成する工程と、（ｂ）その上に
前記回路基板電極に対応する部位に導電部を有するフィ
ルムを形成する工程と、（ｃ）半導体素子にバンプを形
成する工程と、（ｄ）該バンプ先端に接着剤を塗布する
工程と、（ｅ）前記半導体素子と前記回路基板を接続す
る工程とを施すことを特徴とする半導体素子の実装方法
。2. A method for mounting a semiconductor element on a circuit board using a wireless bonding method, comprising: (a) forming a circuit board electrode on the circuit board; and (b) forming a portion corresponding to the circuit board electrode thereon. (c) forming a bump on the semiconductor element; (d) applying an adhesive to the tip of the bump; (e) the semiconductor element and the circuit board; 1. A method for mounting a semiconductor element, comprising: connecting a semiconductor element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3092471A JPH04323840A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3092471A JPH04323840A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04323840A true JPH04323840A (en) | 1992-11-13 |
Family
ID=14055248
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3092471A Withdrawn JPH04323840A (en) | 1991-04-24 | 1991-04-24 | Method of mounting semiconductor element |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04323840A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002180A (en) * | 1996-07-30 | 1999-12-14 | Micron Technology, Inc. | Multi chip module with conductive adhesive layer |
-
1991
- 1991-04-24 JP JP3092471A patent/JPH04323840A/en not_active Withdrawn
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6002180A (en) * | 1996-07-30 | 1999-12-14 | Micron Technology, Inc. | Multi chip module with conductive adhesive layer |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Application deemed to be withdrawn because no request for examination was validly filed |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19980711 |