WO2000057469A1 - Structure for mounting semiconductor device and mounting method - Google Patents

Structure for mounting semiconductor device and mounting method Download PDF

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Publication number
WO2000057469A1
WO2000057469A1 PCT/JP2000/001791 JP0001791W WO0057469A1 WO 2000057469 A1 WO2000057469 A1 WO 2000057469A1 JP 0001791 W JP0001791 W JP 0001791W WO 0057469 A1 WO0057469 A1 WO 0057469A1
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WO
WIPO (PCT)
Prior art keywords
semiconductor device
electrode
mounting
circuit board
circuit
Prior art date
Application number
PCT/JP2000/001791
Other languages
French (fr)
Japanese (ja)
Inventor
Noboru Taguchi
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Publication of WO2000057469A1 publication Critical patent/WO2000057469A1/en

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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

An anisotropically conductive resin (20) mixed with conductive particles (18) is interposed between a semiconductor device (10) comprising a semiconductor chip (2) provided with thereon electrode pads (14) and an insulating film (16) having openings (16a) over the electrode pads (14) and a circuit board (26) comprising circuit electrodes (28). The conductive particles (18) are diffusion-bonded to the electrode pads (14) and the circuit electrodes (28). Thus the semiconductor device (10) is surface-mounted on the circuit board (26).

Description

明 細 書 半導体装置の実装構造および実装方法  Description Semiconductor device mounting structure and mounting method
技 術 分 野 Technical field
この発明は、 異方性導電樹脂を用いて半導体装置を回路基板上に接続して固定し た半導体装置の実装構造と、それを実装するための半導体装置の実装方法に関する。 背 景 技 術  The present invention relates to a semiconductor device mounting structure in which a semiconductor device is connected and fixed on a circuit board using an anisotropic conductive resin, and a semiconductor device mounting method for mounting the same. Background technology
従来から、 集積回路 （ I C ) や大規模集積回路 （L S I ) などを構成する表面実 装型の半導体装置が広く用いられている。 表面実装型の半導体装置は、 一般に各種 電子機器のプリント配線基板や液晶表示パネルのガラス基板等の回路基板に実装す る際に、 その配線パターンと電気的および機械的に接続するため表面に多数の突起 電極 （バンプ） が列設されている。  2. Description of the Related Art Surface-mounted semiconductor devices that constitute integrated circuits (IC) and large-scale integrated circuits (LSI) have been widely used. Generally, surface mount type semiconductor devices are mounted on a circuit board such as a printed wiring board of various electronic devices or a glass substrate of a liquid crystal display panel, so that a large number of semiconductor devices are electrically and mechanically connected to the wiring pattern. The projection electrodes (bumps) are arranged in rows.
そこで、 突起電極が形成された従来の半導体装置の構造及びその製造方法と、 そ の実装方法について、 第 7図〜第 1 3図の断面図を用いて説明する。  Therefore, the structure of a conventional semiconductor device having a bump electrode formed thereon, its manufacturing method, and its mounting method will be described with reference to the cross-sectional views of FIGS. 7 to 13. FIG.
第 1 2図は、従来の突起電極を備えた半導体装置の一例を示す模式的な断面図で 図示の都合上突起電極は 2個のみ示しているが、 実際には紙面に垂直な方向に多数 列設されている。  FIG. 12 is a schematic cross-sectional view showing an example of a conventional semiconductor device provided with a bump electrode. For convenience of illustration, only two bump electrodes are shown. It is lined up.
この半導体装置 1は、 図示の通り、 集積回路が形成された半導体チップ 2の表面 に多数の電極パッド 1 4が列設されている。 その半導体チップ 2の表面には、 各電 極パッド 1 4の周縁部を被覆してその内側を露出させるように、 開口部 1 6 aを設 けた絶縁膜 1 6が形成されている。  As shown in the figure, the semiconductor device 1 has a large number of electrode pads 14 arranged on a surface of a semiconductor chip 2 on which an integrated circuit is formed. An insulating film 16 having an opening 16a is formed on the surface of the semiconductor chip 2 so as to cover the periphery of each electrode pad 14 and expose the inside thereof.
そして、 その絶縁膜 1 6の開口部 1 6 aを通して各電極パッド 1 4上に、 それぞ 共通電極膜 3 3を介して突起電極 4 0が設けられている。 共通電極膜 3 3は、 クロ ムからなる第 1の下部電極層 3 0と、 銅からなる第 2の下部電極層 3 2とが重なつ た 2層構造で形成されている。 各突起電極 4 0は、 共通電極膜 3 3に接して形成さ れたマッシュルーム形状の銅めつき層 3 4と、 その上に形成された半田めつき層 3 6とからなる 2層構造になっている。 半田めつき層 3 6は、 リフロー処理により丸 められて上部が球面に近い形状になっている。 The protruding electrodes 40 are provided on the respective electrode pads 14 through the openings 16 a of the insulating film 16 via the common electrode film 33. The common electrode film 33 has a two-layer structure in which a first lower electrode layer 30 made of chrome and a second lower electrode layer 32 made of copper overlap. Each protruding electrode 40 is formed in contact with the common electrode film 33. It has a two-layer structure consisting of a mushroom-shaped copper plating layer 34 and a solder plating layer 36 formed thereon. The soldering layer 36 is rounded by the reflow process, and the upper portion has a shape close to a spherical surface.
次に、 上述のような構造を有する従来の半導体装置の製造方法について、 第 7図 〜第 1 2図を用いて説明する。  Next, a method for manufacturing a conventional semiconductor device having the above-described structure will be described with reference to FIGS. 7 to 12. FIG.
一般に、 半導体装置は、 一枚の半導体基板 （ゥエーハ） から一度に多数個の半導 体チップを形成して製造する。 そこで、 まず第 7図に示すように、 複数の半導体装 置を構成する各半導体チップに相当する領域毎に図示しない集積回路を形成し、 そ の集積回路を外部と接続するためのアルミニウムからなる電極パッド 1 4を表面に 多数列設した半導体基板 1 2を用意する。 そして、 その表面全体を被覆するように 絶縁膜 1 6を形成する。 続いて、 フォ トエッチング技術により、 その絶縁膜 1 6の 各電極パッド 1 4に対応する部分に開口部 1 6 aを形成して、 その内側に電極パッ ド 1 4を露出させる。  Generally, a semiconductor device is manufactured by forming a large number of semiconductor chips at a time from a single semiconductor substrate (a wafer). Therefore, first, as shown in FIG. 7, an integrated circuit (not shown) is formed for each region corresponding to each semiconductor chip constituting a plurality of semiconductor devices, and is formed of aluminum for connecting the integrated circuit to the outside. A semiconductor substrate 12 having a large number of electrode pads 14 arranged on its surface is prepared. Then, an insulating film 16 is formed so as to cover the entire surface. Subsequently, an opening 16a is formed in a portion of the insulating film 16 corresponding to each electrode pad 14 by photoetching technology, and the electrode pad 14 is exposed inside the opening 16a.
次に、 第 8図に示すように、 この電極パッド 1 4と絶縁膜 1 6を有する半導体基 板 1 2の全面にスパッタリング法により、 共通電極膜 3 3を形成する。 この共通電 極膜 3 3は、 クロムからなる膜厚 0 . 0 1 μ m程度の第 1の下部電極層 3 0と、 銅 からなる膜厚 0 . 4 m程度の第 2の下部電極層 3 2とからなる 2層構造で形成す る。 この第 1の下部電極層 3 0は、 電極パッ ド 1 4との接続層としての役割と、 電 極パッド 1 4と第 2の下部電極層 3 2との相互拡散を防ぐバリヤ層の役割とをもつ ものである。 第 2の下部電極層 3 2は、 突起電極 4 0を電気めつき法にて形成する ときの電極としての役割と、 突起電極 4 0の接続層としての役割をもつ。  Next, as shown in FIG. 8, a common electrode film 33 is formed on the entire surface of the semiconductor substrate 12 having the electrode pads 14 and the insulating film 16 by a sputtering method. The common electrode film 33 is composed of a first lower electrode layer 30 of about 0.1 μm thick made of chromium and a second lower electrode layer 3 of about 0.4 m thick made of copper. 2 is formed in a two-layer structure. The first lower electrode layer 30 has a role as a connection layer with the electrode pad 14 and a role as a barrier layer for preventing mutual diffusion between the electrode pad 14 and the second lower electrode layer 32. It has The second lower electrode layer 32 has a role as an electrode when the bump electrode 40 is formed by the electroplating method and a role as a connection layer of the bump electrode 40.
その後、 この共通電極膜 3 3の全面に感光性樹脂 5 0を回転塗布法により 5 μ m 程度の厚さで形成し、フォトリソグラフィ技術による露光および現像処理を行って、 第 9図に示すようにその感光性樹脂 5 0をパターユングし、 突起電極 4 0を形成す る部分に相当する位置に開口部 5 0 aを形成する。 次に、 この半導体基板 1 2を、 硫酸銅からなる銅めつき液を 2 5 °Cの温度に保つ た図示しない銅めつき槽内に入れ、 その銅めつき槽側の電極と共通電極膜 3 3との 間に流す電流の電流密度を 3 A Z d m とする条件下で、 選択的にめっき処理を行 い、 銅めつき層 3 4を 2 5 μ m程度の厚さに形成する。 Thereafter, a photosensitive resin 50 is formed on the entire surface of the common electrode film 33 to a thickness of about 5 μm by a spin coating method, and is exposed and developed by a photolithography technique, as shown in FIG. Then, the photosensitive resin 50 is patterned and an opening 50a is formed at a position corresponding to a portion where the protruding electrode 40 is to be formed. Next, the semiconductor substrate 12 is placed in a copper plating bath (not shown) in which a copper plating solution made of copper sulfate is maintained at a temperature of 25 ° C., and an electrode on the copper plating bath side and a common electrode film are formed. Under the condition that the current density of the current flowing between 3 and 3 is 3 AZdm, plating is selectively performed to form a copper plating layer 34 with a thickness of about 25 μm.
続いて、 この半導体基板 1 2を、 有機酸からなる半田めつき液を 2 5 °Cに温度に 保った図示しない半田めつき槽に入れ、 その半田めつき槽側の電極と共通電極膜 3  Subsequently, the semiconductor substrate 12 is put into a soldering bath (not shown) in which a soldering solution made of an organic acid is maintained at 25 ° C., and the electrodes on the soldering bath side and the common electrode film 3 are placed.
3 との間に流す電流の電流密度を 3 A/ d m とする条件下で、 同じく選択的にめ つき処理を行い、 第 1 0図に示すように、 銅めつき層 3 4上に半田めつき層 3 6を 2 5 ^ m程度の厚さに形成する。 Similarly, under the condition that the current density of the current flowing between them is 3 A / dm, the same selective plating process is performed, and as shown in FIG. 10, soldering is performed on the copper plating layer 34. The additional layer 36 is formed to a thickness of about 25 ^ m.
このよ うに、 銅めつき層 3 4と半田めつき層 3 6とは、 各々 2 5 μ m程度の厚さ で形成しているが、 これは次のような理由による。 半導体装置をフェースダウン実 装法により実装する場合には、 回路基板に接続した後にアンダフィル剤 （エポキシ 系接着剤） をその半導体装置と回路基板との間に流し込む必要がある。 これは、 外 部からの水分の浸入を防止するとともに、 環境の変化に伴う熱収縮により応力が作 用して半導体装置が剥離することを防止し、 これによつて信頼性を向上させるため である。 そして、 そのアンダフィル剤を流し込んで目的を果たすためには、 その半 導体装置と回路基板との隙間を 5 0 μ m以上確保する必要がある。  As described above, the copper plating layer 34 and the solder plating layer 36 are each formed with a thickness of about 25 μm for the following reason. When a semiconductor device is mounted by a face-down mounting method, it is necessary to pour an underfill agent (epoxy adhesive) between the semiconductor device and the circuit board after connecting to the circuit board. This is to prevent the penetration of moisture from the outside and to prevent the semiconductor device from peeling due to stress due to thermal shrinkage due to an environmental change, thereby improving reliability. is there. In order to achieve the purpose by pouring the underfill agent, it is necessary to secure a gap of 50 μm or more between the semiconductor device and the circuit board.
また、 一般に使用されるガラスとエポキシ樹脂からなる回路基板は数十 m程度 の反りを有するため、 フェースダウン実装法の際、 その反りを吸収して実装できる ようにする必要があるという理由からも、 半導体装置と回路基板との隙間を 5 0 μ m程度確保する必要がある。  Also, circuit boards made of glass and epoxy resin, which are generally used, have a warpage of about several tens of meters, so it is necessary to absorb the warpage and mount them in the face-down mounting method. It is necessary to secure a gap of about 50 μm between the semiconductor device and the circuit board.
次に、 第 1 0図に示した状態から感光性樹脂 5 0を除去すると、 マッシュルーム 形状の銅めつき層 3 4の上部に半田めつき層 3 6が傘のように被さった状態の突起 電極 4 0が得られる。 続いて、 その突起電極 4 0をマスクにして、 共通電極膜 3 3 を構成する第 2の下部電極層 3 2及び第 1の下部電極層 3 0とを湿式エッチング法 によりエッチングし、 その後、 半田めつき層 3 6を加熱によるリフロー処理により 丸めると、 半田めつき層 3 6が表面張力によって盛り上がって、 第 1 1図に示すよ うに表面が球面に近い形状になる。 Next, when the photosensitive resin 50 is removed from the state shown in FIG. 10, the protruding electrode in a state where the soldering layer 36 is covered like an umbrella on the mushroom-shaped copper plating layer 34 is formed. 40 is obtained. Subsequently, using the protruding electrode 40 as a mask, the second lower electrode layer 32 and the first lower electrode layer 30 constituting the common electrode film 33 are wet-etched. Then, the soldered layer 36 is rolled up by reflow treatment by heating. .
そして、 共通電極膜 3 3の不要部分を湿式エッチング法によって除去する。  Then, unnecessary portions of the common electrode film 33 are removed by a wet etching method.
このようにして、 半導体基板 1 2上の各電極パッド 1 4上に突起電極 4 0を設け た後、 ダイシング装置を用いて半導体基板 1 2をダイシングライン aで切断し、 各 半導体チップ 2に相当する領域ごとに分割する。すると、第 1 2図に示したように、 半導体チップ 2上に多数の突起電極 4 0を備えた半導体装置 1が完成する。 In this way, after the protruding electrodes 40 are provided on the respective electrode pads 14 on the semiconductor substrate 12, the semiconductor substrate 12 is cut along the dicing line a using a dicing apparatus, and the semiconductor substrate 12 is equivalent to each semiconductor chip 2. The area is divided for each area. Then, as shown in FIG. 12, a semiconductor device 1 having a large number of projecting electrodes 40 on the semiconductor chip 2 is completed.
このような半導体装置 1を従来は、 次のようにして回路基板に実装していた。 第 1 3図に示すように、 半導体装置 1を実装しようとする回路基板 2 6に、 突 起電極 4 0と回路電極 2 8とを対向させて重ね合わせる。 続いて、 半田めつき層 3 6にリフロー処理を施して半導体装置 1を回路基板 2 6上に接続して固定する。 こ のとき、 両者の位置合わせは、 半田めつき層 3 6の表面張力の作用によって自己整 合的に行なわれるので、各突起電極 4 0と各回路電極 2 8との互いの位置が多少（数 十 μ ιη程度） ずれていても、 その位置のずれが微妙に是正されて ± 1 0 m以内の 精度で接続される。  Conventionally, such a semiconductor device 1 has been mounted on a circuit board as follows. As shown in FIG. 13, the projecting electrode 40 and the circuit electrode 28 are superposed on a circuit board 26 on which the semiconductor device 1 is to be mounted. Subsequently, the soldering layer 36 is subjected to a reflow process to connect and fix the semiconductor device 1 on the circuit board 26. At this time, the positioning of both is performed in a self-aligned manner by the action of the surface tension of the soldered layer 36, so that the positions of the respective protruding electrodes 40 and the respective circuit electrodes 28 are slightly different from each other. Even if there is a deviation, the deviation of the position is delicately corrected and connected with an accuracy of ± 10 m or less.
その後、 半導体チップ 2と回路基板 2 6との隙間にエポキシからなる封止樹脂 3 8を注入して焼成を行う。 このようにして、 従来の半導体装置 1は、 第 1 3図に示 すように、突起電極 4 0と回路電極 2 8とが接続して固定された状態で実装される。  Thereafter, a sealing resin 38 made of epoxy is injected into a gap between the semiconductor chip 2 and the circuit board 26, and firing is performed. In this manner, the conventional semiconductor device 1 is mounted in a state where the protruding electrode 40 and the circuit electrode 28 are connected and fixed as shown in FIG.
しかし、 従来の半導体装置を実装するためには、 電極パッド 1 4のそれぞれに突 起電極 4 0を形成しなければならず、 この突起電極 4 0を形成するために細かくて 手間のかかる作業が必要とされ、 しかも、 めっき工程、 フォ トリソ工程あるいはェ ツチング工程などの多数の工程を経なければならなかった。 また、 突起電極 4 0を 形成する際にはめつき装置、 フォ トリソ装置、 エッチング装置など非常に高価な装 置が必要とされる。 そのため、 半導体装置の製造コス ト及びそれを回路基板に実装 するためのコストが高くなっていた。 However, in order to mount the conventional semiconductor device, it is necessary to form the protruding electrodes 40 on each of the electrode pads 14, and fine and laborious work is required to form the protruding electrodes 40. It was required and had to go through a number of steps such as plating, photolithography or etching. Further, when forming the protruding electrodes 40, extremely expensive equipment such as a fitting apparatus, a photolithography apparatus, and an etching apparatus is required. Therefore, the cost of manufacturing semiconductor devices and mounting them on circuit boards The cost of doing so was high.
また、 従来の半導体装置の実装構造は、 突起電極 4 0を介して実装するため、 第 1 3図に示すように電極パッド 1 4と回路電極 2 8との間隔 hを 5 0 / m以上確保 しなければならず、 高密度実装には適さない構造になっていた。  In addition, since the mounting structure of the conventional semiconductor device is mounted via the protruding electrodes 40, a space h between the electrode pad 14 and the circuit electrode 28 of 50 / m or more is secured as shown in FIG. The structure was not suitable for high-density mounting.
この発明は、 従来の半導体装置の実装構造および実装方法における上記の問題を 解決するためになされたもので、 半導体装置に突起電極を設けることなく実装でき るようにし、 半導体装置の回路基板への実装を容易かつ迅速に行なえ、 かつ安価で 信頼性が高く高密度の実装も可能にすることを目的とする。  SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems in the conventional mounting structure and mounting method of a semiconductor device. The purpose is to enable easy and quick mounting and to enable low-cost, highly reliable and high-density mounting.
発明の開示 Disclosure of the invention
この発明による半導体装置の実装構造は、 上記の目的を達成するため、 集積回路 およびそれを外部に接続するための複数の電極パッドを設けた半導体チップ上の表 面に前記各電極パッド上に開口部を有する絶縁膜を形成した半導体装置を、 パター ニングされた回路電極を有する回路基板に実装した半導体装置の実装構造であって、 半導体装置の絶縁膜を形成した面の略全域と回路基板の回路電極を有する面との 間に、 導電性粒子を混在した異方性導電樹脂を介在し、 導電性粒子が電極パッド及 び前記回路電極と拡散接合しているものである。  In order to achieve the above object, a mounting structure of a semiconductor device according to the present invention includes an integrated circuit and a plurality of electrode pads for connecting the integrated circuit to the outside. The mounting structure of a semiconductor device in which a semiconductor device having an insulating film having a portion formed thereon is mounted on a circuit board having patterned circuit electrodes, and substantially the entire surface of the semiconductor device on which the insulating film is formed and the circuit board. An anisotropic conductive resin mixed with conductive particles is interposed between the surface having the circuit electrodes and the conductive particles are diffusion-bonded to the electrode pads and the circuit electrodes.
導電性粒子は、 金からなるものが好ましい。  The conductive particles are preferably made of gold.
また、 導電性粒子が銅等の金属を核とし、 その表面に金又は白金等の拡散接合し やすい別の金属を被膜してなるものでもよいし、 樹脂粒子の表面に金属膜を形成し レ、。  Further, the conductive particles may be made of a metal such as copper as a nucleus and the surface thereof is coated with another metal such as gold or platinum which is easily diffused and bonded, or a metal film is formed on the surface of the resin particles. ,.
また、 この発明による半導体装置の実装方法は、 以下の（1)〜 （3)までの各工程 を有する。  Further, a method of mounting a semiconductor device according to the present invention includes the following steps (1) to (3).
(1) 集積回路およびそれを外部に接続するための複数の電極パッドを設けた半導 体チップの表面に各電極パッド上に開口部を有する絶縁膜を形成した半導体装置の 前記絶縁膜を形成した面の略全域に、 導電性粒子を混在した異方性導電樹脂を配置 する工程、 (1) Forming the insulating film of a semiconductor device in which an insulating film having an opening on each electrode pad is formed on the surface of a semiconductor chip provided with a plurality of electrode pads for connecting the integrated circuit to the outside. Anisotropic conductive resin mixed with conductive particles is placed almost all over the surface Process,
(2) その各半導体装置を、 回路電極を有する回路基板上に、 異方性導電樹脂を介 して各電極パッドと前記回路電極とを対向させるように位置合わせして配置するェ 程、  (2) arranging the respective semiconductor devices on a circuit board having circuit electrodes, with the respective electrode pads and the circuit electrodes facing each other via an anisotropic conductive resin,
(3) 半導体装置に超音波を印加するとともに荷重を加える工程、  (3) applying ultrasonic waves and applying a load to the semiconductor device,
また、 前記半導体装置の表面に異方性導電樹脂を配置する工程と、 その半導体装 置を前記回路基板上に配置する工程との間に、 8 0 °C〜 1 0 0 °C程度の温度で前記 半導体装置を加熱して前記異方性導電樹脂中の溶媒の一部を蒸発させる工程を有す る半導体装置の実装方法とするのがよい。  Further, a temperature of about 80 ° C. to about 100 ° C. is applied between the step of disposing the anisotropic conductive resin on the surface of the semiconductor device and the step of disposing the semiconductor device on the circuit board. Preferably, the method for mounting a semiconductor device includes a step of heating the semiconductor device to evaporate a part of the solvent in the anisotropic conductive resin.
さらに、 上記各半導体装置に超音波を印加するとともに荷重を加える工程中に、 回路基板側から加熱する半導体装置の実装方法とするのがよい。  Further, it is preferable to adopt a method of mounting a semiconductor device in which the semiconductor device is heated from the circuit board side during the step of applying a load and applying an ultrasonic wave to each semiconductor device.
さらにまた、 上記回路基板側から加熱する温度が 1 5 0 °C〜 2 0 0 °C程度である 半導体装置の実装方法とするのがよい。  Furthermore, it is preferable to adopt a method of mounting a semiconductor device in which the temperature for heating from the circuit board side is about 150 ° C. to 200 ° C.
図面の簡単な説明 BRIEF DESCRIPTION OF THE FIGURES
第 1図は、 この発明による半導体装置の実装構造の一実施形態を示す模式的な断 面図である。  FIG. 1 is a schematic cross-sectional view showing one embodiment of a semiconductor device mounting structure according to the present invention.
第 2図は、 第 1図に示す半導体装置の実装構造の要部を示す模式的な断面図であ る。  FIG. 2 is a schematic sectional view showing a main part of the mounting structure of the semiconductor device shown in FIG.
第 3図〜第 5図は、 この発明による半導体装置の実装方法の一実施形態を説明す るための各工程を順に示す模式的な断面図である。  FIG. 3 to FIG. 5 are schematic cross-sectional views sequentially showing each step for describing one embodiment of a method for mounting a semiconductor device according to the present invention.
第 6図は、 この発明による別の手順による半導体装置の実装方法で用いる半導体 チップを示す模式的な断面図である。  FIG. 6 is a schematic sectional view showing a semiconductor chip used in a semiconductor device mounting method according to another procedure according to the present invention.
第 7図〜第 1 2図は、 従来の半導体装置の製造方法を説明するための各工程を順 に示す模式的な断面図である。  7 to 12 are schematic cross-sectional views showing, in order, respective steps for describing a conventional method of manufacturing a semiconductor device.
第 1 3図は、 従来の半導体装置の実装構造を示す模式的な断面図である。 発明を実施するための最良の形態 FIG. 13 is a schematic cross-sectional view showing a mounting structure of a conventional semiconductor device. BEST MODE FOR CARRYING OUT THE INVENTION
以下、 この発明による半導体装置の実装構造を実施するための最良の形態につい て、 第 1図から第 6図を用いて詳細に説明する。 なお、 第 7図から第 1 3図に示し た従来例と対応する部分には、 同一の符号を付している。  Hereinafter, the best mode for implementing a semiconductor device mounting structure according to the present invention will be described in detail with reference to FIGS. 1 to 6. Parts corresponding to those in the conventional example shown in FIGS. 7 to 13 are denoted by the same reference numerals.
この発明による半導体装置の実装構造は、 第 1図に示すように、 半導体装置 1 0を回路基板 2 6に対して、 異方性導電樹脂 2 0を介して実装したものである。 そして、 異方性導電樹脂 2 0に含まれる導電性粒子 1 8が電極パッド 1 4及び回路 電極 2 8に対して互いに拡散接合することによって、 電極パッド 1 4と回路基板 2 8が電気的に接続して固定されている。  As shown in FIG. 1, the mounting structure of a semiconductor device according to the present invention is such that a semiconductor device 10 is mounted on a circuit board 26 via an anisotropic conductive resin 20. Then, the conductive particles 18 contained in the anisotropic conductive resin 20 are diffused and bonded to the electrode pad 14 and the circuit electrode 28 to electrically connect the electrode pad 14 and the circuit board 28. Connected and fixed.
半導体装置 1 0は、 従来と同様に集積回路が形成された半導体チップ 2の片側表 面に、 電極パッド 1 4が多数列設されるとともに、 各電極パッド 1 4上に開口部 1 6 aを有する絶縁膜 1 6が形成されている。  In the semiconductor device 10, a large number of electrode pads 14 are arranged on one surface of a semiconductor chip 2 on which an integrated circuit is formed in the same manner as before, and an opening 16a is formed on each electrode pad 14. The insulating film 16 is formed.
異方性導電樹脂 2 0は、 エポキシ樹脂、 フエノール樹脂等の絶縁性の樹脂に導電 性粒子 1 8を多数混入させたもので、 図に示すように、 半導体チップ 2の表面に配 置したときにその厚さ方向には導電性を有するが、 その他の方向 （半導体チップ 2 の表面の平行な方向） には導電性を持たない性質を有するものである。 この発明の 実施形態では、 エポキシ系の樹脂を用いている。  The anisotropic conductive resin 20 is obtained by mixing a large number of conductive particles 18 into an insulating resin such as an epoxy resin or a phenol resin, and is disposed on the surface of the semiconductor chip 2 as shown in the figure. It has the property of having conductivity in the thickness direction, but not having conductivity in the other directions (parallel to the surface of the semiconductor chip 2). In the embodiment of the present invention, an epoxy resin is used.
異方性導電樹脂 2 0は、 半導体チップ 2の表面に回転塗布法により配置されてい る。 この場合の異方性導電樹脂 2 0は、 ペース ト状を呈したものを用いている。 そ のほか、 スクリーン印刷法等によって配置してもよい。  The anisotropic conductive resin 20 is arranged on the surface of the semiconductor chip 2 by a spin coating method. In this case, a paste-like resin is used as the anisotropic conductive resin 20. In addition, they may be arranged by a screen printing method or the like.
また、ベースフィルム上にフィルム状に形成された異方性導電フィルム （A C F ) を転写しているものを用いてもよい。  Further, a material obtained by transferring an anisotropic conductive film (ACF) formed in a film shape on a base film may be used.
いずれの場合も、 半導体チップ 2の表面に配置された時点ではその膜厚が約 1 0 μ ΐη〜 3 0 程度であるが、 回路基板 2 6上に実装された後では圧着力によって 押しつぶされる。 導電性粒子 1 8は、 金、 パラジウム、 白金、 銀、 アルミニウムあるいは半田など の金属単体からなる粒子で、 この発明の実施形態では、 電気伝導性が良好で電極パ ッ ド 1 4及び回路基板 2 8 との相性が良く拡散接合しやすい金を用いている。 その 粒径は、 絶縁膜 1 6の膜厚よりも大きくなるようにする必要がある。 粒径が絶縁膜 1 6の膜厚よりも小さいと、 開口部 1 6 aの隙間に埋もれてしまい、 電極パッ ド 1 4と回路電極 2 8 とを接合できなくなるので好ましくない。 具体的には、 粒径にあ る程度のばらつきがあることと、 絶縁膜 1 6の膜厚が約 1 ； u mであることを考慮し て、 平均粒径を約 1 . 5 μ ΐη乃至 5 μ m程度とするのがよい。 In any case, the film thickness is about 10 μΐη to about 30 when it is arranged on the surface of the semiconductor chip 2, but after being mounted on the circuit board 26, it is crushed by the pressing force. The conductive particles 18 are particles made of a simple metal such as gold, palladium, platinum, silver, aluminum, or solder. Uses gold that is compatible with 8 and easily diffused. The particle size must be larger than the thickness of the insulating film 16. If the particle size is smaller than the film thickness of the insulating film 16, it is not preferable because the electrode pad 14 and the circuit electrode 28 cannot be joined because they are buried in the gap between the openings 16 a. Specifically, considering that there is a certain degree of variation in the particle diameter and that the thickness of the insulating film 16 is about 1 μm, the average particle diameter is about 1.5 μΐη to 5 μm. It is good to be about μm.
導電性粒子 1 8は、 金、 白金などの 1種類の金属ではなく、 2種類の金属からな る 2層構造と してもよい。 例えば、 銅等の金属を核とし、 その表面に拡散接合しや すい別の金属 （例えば、 金または白金） を被膜して形成したものでもよレ、。 逆に、 チタンゃ鉄のような金属は、 導電性粒子 1 8の材質としてはあまり適さない。  The conductive particles 18 may have a two-layer structure made of two types of metals, instead of one type of metal such as gold and platinum. For example, a core formed of a metal such as copper and coated with another metal (for example, gold or platinum) which is easily bonded to the surface thereof may be used. Conversely, metals such as titanium and iron are not very suitable as the material of the conductive particles 18.
また、 プラスチック性の樹脂粒子の表面にめっきを施して金属膜を形成したもの でもよい。 この場合の金属は、 金または白金が好ましく、 特に金を用いるのがよい。 金または白金は、 電極パッ ド 1 4との拡散接合をしやすく、 良好な接続状態を維持 できる点で好ましい。  Further, a metal film may be formed by plating the surface of plastic resin particles. In this case, the metal is preferably gold or platinum, and gold is particularly preferably used. Gold or platinum is preferable because it can be easily diffused and bonded to the electrode pad 14 and can maintain a good connection state.
そして、 この導電性粒子 1 8は、 その粒径、 電極パッ ド 1 4の大きさや電極間ピ ツチ等を考慮して接着剤樹脂に対して添加する量を決めればよく、 例えば、 約 4 w t % (重量。 /0 ) の量で添加して混練することによって異方性導電樹脂 2 0としてい る。 The amount of the conductive particles 18 to be added to the adhesive resin may be determined in consideration of the particle size, the size of the electrode pad 14, the pitch between the electrodes, and the like. % (wt. / 0) it is the anisotropic conductive resin 2 0 by kneading added in an amount of.
そして、 この異方性導電樹脂 2 0内の多数の導電性粒子 1 8のうち、 一部の導電 性粒子 1 8 a 、 電極パッ ド 1 4及び回路電極 2 8の双方と互いに拡散接合により 接続している。 すなわち、 電極パッ ド 1 4と回路電極 2 8 とが導電性粒子 1 8を介 して互いに電気的かつ物理的に接続されている。 この 3つが接続されている部分を 拡大して図示すると、 第 2図に示すようになる。 電極パッ ド 1 4及び回路電極 2 8 は、 それぞれ導電性粒子 1 8との接続点 a , bにおいて金属原子 （分子） が互いに 相手方に拡散する拡散接合により確実に接続されている。 Then, of the many conductive particles 18 in the anisotropic conductive resin 20, some of the conductive particles 18 a are connected to both the electrode pad 14 and the circuit electrode 28 by diffusion bonding. are doing. That is, the electrode pad 14 and the circuit electrode 28 are electrically and physically connected to each other via the conductive particles 18. Fig. 2 shows an enlarged view of the part where these three are connected. Electrode pad 14 and circuit electrode 2 8 Are surely connected by diffusion bonding in which metal atoms (molecules) diffuse to each other at connection points a and b with the conductive particles 18 respectively.
この実施形態では、 後述するように、 半導体チップ 2の裏面 （電極パッド 1 4の 形成されていない面） から超音波を印加するとともに荷重を加え、 さらに、 回路基 板 2 6の側から加熱して拡散接合を形成している。 超音波を印加すると、 その超音 波による振動エネルギーが電極パッド 1 4を介して導電性粒子 1 8に伝わり、 この 振動エネルギーを受けた導電性粒子 1 8が揺さぶられて電極パッド 1 4及び回路電 極 2 8の表面で摩擦を起こし、 その摩擦による熱エネルギーがその接触部分に加わ ることによって拡散接合が促進されている。 この際、 電極パッド 1 4は、 アルミ二 ゥムからなつているので、 その表面には薄い酸化膜 1 4 aが形成されているが、 導 電性粒子 1 8は、 揺さぶられたときにその酸化膜 1 4 aを突き破り、 直接に電極パ ッド 1 4のアルミニウムの表面 1 4 bと接触する。 こうして、 拡散接合による電気 的な接続が確実になっている。  In this embodiment, as described later, ultrasonic waves are applied from the back surface of the semiconductor chip 2 (the surface on which the electrode pads 14 are not formed), a load is applied, and the semiconductor chip 2 is further heated from the circuit board 26 side. To form a diffusion bond. When an ultrasonic wave is applied, the vibration energy due to the ultrasonic wave is transmitted to the conductive particles 18 via the electrode pads 14, and the conductive particles 18 which have received the vibration energy are shaken, and the electrode pads 14 and the circuit Friction occurs on the surface of the electrode 28, and thermal energy due to the friction is applied to the contact portion, thereby promoting diffusion bonding. At this time, since the electrode pad 14 is made of aluminum, a thin oxide film 14a is formed on the surface of the electrode pad 14, but the conductive particles 18 are not swayed when they are shaken. Breaks through the oxide film 14a and makes direct contact with the aluminum surface 14b of the electrode pad 14. Thus, electrical connection by diffusion bonding is ensured.
拡散接合を形成するには、 超音波を印加することなく加熱することによって導電 性粒子 1 8を振動させてもよい。 しかし、 超音波の印加による拡散接合は、 振動を 加えるのに必要なエネルギーを熱エネルギーではなく超音波によって加えているた め、 実装する時の温度を低温で実現できる点で好ましい。 低温で実装することによ つて、 次の二つの作用効果がもたらされる。  To form a diffusion bond, the conductive particles 18 may be vibrated by heating without applying ultrasonic waves. However, diffusion bonding by application of ultrasonic waves is preferable because the energy required for applying vibration is applied not by heat energy but by ultrasonic waves, so that the mounting temperature can be realized at a low temperature. Mounting at low temperature has the following two effects.
加熱することによって、 実装する際の温度を高温にすると、 異方性導電樹脂 2 0 が変質したり、 半導体チップ 2内に設けられた素子の動作に悪影響を与えるおそれ がある。 また、 この実装構造のように、 互いに性質が異なるものを狭い領域に密集 させていると、 高温にした場合にそれぞれの線膨張係数の相違が助長されてひずみ が発生し、 接続状況が悪化するおそれがある。 しかし、 超音波印加による拡散接合 の場合は、 これらの影響が出ない範囲の低温での実装が可能となる。  If the temperature at the time of mounting is increased by heating, the anisotropic conductive resin 20 may deteriorate or adversely affect the operation of elements provided in the semiconductor chip 2. Also, as shown in this mounting structure, if things with different properties are densely packed in a narrow area, the difference in linear expansion coefficient will be promoted at high temperatures, resulting in distortion and deterioration of the connection situation. There is a risk. However, in the case of diffusion bonding by applying ultrasonic waves, mounting at a low temperature within a range where these effects do not occur can be achieved.
そして、 超音波印加および加熱の双方を施すと、 超音波による振動と熱エネルギ 一による振動という周波数や振動の方向が異なる 2種類の振動が加わるため、 導電 性粒子 1 8と電極パッ ド 1 4等との接触がより良好となる。 もちろん超音波印加の みの拡散接合でもよいし、 加熱のみの拡散接合でもよい。 When both ultrasonic application and heating are performed, vibration and heat energy Since two types of vibrations having different frequencies and different directions of vibration are applied, the contact between the conductive particles 18 and the electrode pads 14 and the like becomes better. Of course, diffusion bonding using only ultrasonic waves or diffusion bonding using only heating may be used.
さらに、 導電性粒子 1 8は金属製粒子と しているため、 実装時に荷重が加えられ ても容易には変形しない。 したがって、 粒子が変形した際の復元力が発生すること がない。  Further, since the conductive particles 18 are metal particles, they do not easily deform even when a load is applied during mounting. Therefore, no restoring force is generated when the particles are deformed.
この点、 プラスチック粒子に金属を被覆させた導電性粒子 1 8を用いると、 その プラスチック粒子の変形による復元力を利用して接続できるので、 接続をより確実 にできる点で好ましい。 しかし、 そのためにはプラスチック粒子を変形させられる 程度の荷重 （4 0 0 kg/cm2 程度） を加えねばならない。 In this regard, the use of conductive particles 18 in which plastic particles are coated with metal is preferable in that connection can be made more reliably because the connection can be made using the restoring force due to deformation of the plastic particles. However, for that purpose, a load (about 400 kg / cm 2 ) that can deform the plastic particles must be applied.
一方、 導電性粒子 1 8を金属製粒子にした場合は、 変形させる必要がないため荷 重はその半分以下の 6 0 〜 2 0 0 k g Z c m 2程度でよい。 この程度の荷重であれ ば半導体チップ 2内の回路素子に悪影響が及ぶおそれもない。 また、 導電性粒子 1 8には、 変形による復元力はほとんど発揮されないが、 拡散接合により接続されて いるので、 接続状態は充分に良好でありかつ確実である。 On the other hand, when the conductive particles 18 are made of metal particles, there is no need to deform them, so the load may be about 60 to 200 kg Zcm 2 which is half or less. With such a load, there is no possibility that circuit elements in the semiconductor chip 2 will be adversely affected. Although the conductive particles 18 hardly exert a restoring force due to deformation, they are connected by diffusion bonding, so that the connection state is sufficiently good and reliable.
以上のように、 半導体装置 1 0は電極パッ ド 1 4と回路電極 2 8とを異方性導電 樹脂 2 0中の導電性粒子 1 8を介して電気的及び物理的に接続している。 したがつ て、 従来の半導体装置 1のように、 突起電極を設けて実装する構造と比較して、 電 極パッ ド 1 4相互間のピッチおょぴ電極パッ ド 1 4と回路電極 2 8 との間隔を狭め ることができるので、 高密度実装が可能になる。 さらに、 超音波の印加により拡散 接合する場合には、 接続状態がより確実になり高い信頼性が得られる。  As described above, the semiconductor device 10 electrically and physically connects the electrode pad 14 and the circuit electrode 28 via the conductive particles 18 in the anisotropic conductive resin 20. Therefore, the pitch between the electrode pads 14 and the electrode pads 14 and the circuit electrodes 28 are different from those of the conventional semiconductor device 1 in which bump electrodes are provided and mounted. Since the distance between them can be reduced, high-density mounting is possible. Furthermore, in the case of diffusion bonding by applying ultrasonic waves, the connection state is more reliable and high reliability is obtained.
次に、この第 1図に示した半導体装置の実装構造を得るための実装方法について、 第 3図から第 7図を用いて説明する。 この場合も、 一枚の半導体基板 （ゥエーハ） から一度に多数の半導体装置を製造する。  Next, a mounting method for obtaining the mounting structure of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. Also in this case, a large number of semiconductor devices are manufactured at once from a single semiconductor substrate (a wafer).
そこで、 まず第 7図に示した従来例と同様に、 複数の半導体装置を構成する各半 導体チップに相当する領域毎に図示しない集積回路を形成し、 その集積回路を外部 と接続するためのアルミニウムからなる電極パッ ド 1 4を多数上面に列設した半導 体基板 1 2を用意する。 そして、 その上面全体を被覆するように絶縁膜 1 6を形成 する。 続いて、 フォ トエッチング技術により、 その絶縁膜 1 6の各電極パッ ド 1 4 に対応する部分に開口部 1 6 aを形成して、 その内側に電極パッ ド 1 4を露出させ る。 Therefore, similarly to the conventional example shown in FIG. 7, each half of the plurality of semiconductor devices is formed. An integrated circuit (not shown) is formed for each region corresponding to the conductive chip, and a semiconductor substrate 12 is prepared in which a large number of aluminum electrode pads 14 for connecting the integrated circuit to the outside are arranged on the upper surface. . Then, an insulating film 16 is formed so as to cover the entire upper surface. Subsequently, an opening 16a is formed in a portion of the insulating film 16 corresponding to each electrode pad 14 by a photo-etching technique, and the electrode pad 14 is exposed inside.
なお、 絶縁膜 1 6は、 窒化珪素膜をプラズマ化学的気相成長 （プラズマ C V D ) 法により形成するもので、 膜厚は Ι μ πι程度とする。 また、 窒化珪素以外に、 二酸 化珪素や酸化タンタル、 あるいは酸化アルミニウムなどの無機質膜としてもよく、 その形成方法としてスパッタリング法を用いてもよい。  The insulating film 16 is formed by forming a silicon nitride film by a plasma-enhanced chemical vapor deposition (plasma CVD) method, and has a film thickness of about μπι. Further, in addition to silicon nitride, an inorganic film such as silicon dioxide, tantalum oxide, or aluminum oxide may be used, and a sputtering method may be used as a formation method.
次に、 第 3図に示すように、 この半導体基板 1 2の絶縁膜 1 6を形成した面の全 面に導電性粒子 1 8を混在させた異方性導電樹脂 2 0を回転塗布法により、 膜厚が 約 Ι Ο μ π！〜 3 0 mとなるように被膜形成する。 このとき、 導電性粒子 1 8は、 粒径が約 5 mの金からなる粒子を用いるが、 金以外にインジウム、 パラジウム、 白金、 銀、 アルミニウム、 半田でもよいし、 プラスチック粒子にこれらの金属被膜 を形成したものでもよい。  Next, as shown in FIG. 3, an anisotropic conductive resin 20 mixed with conductive particles 18 is applied to the entire surface of the semiconductor substrate 12 on which the insulating film 16 is formed by a spin coating method. The film thickness is about Ο Ο μπ! A film is formed to have a thickness of about 30 m. At this time, the conductive particles 18 are made of gold particles having a particle size of about 5 m, but may be made of indium, palladium, platinum, silver, aluminum, solder, or plastic particles other than gold. May be formed.
また異方性導電樹脂 2 0としては、 ペース ト状のものを用いる。 回転塗布法以外 に印刷法、 具体的にはスクリーン印刷法を用いてもよい。 スクリーン印刷法による と、 ダイシングラインを外して異方性導電樹脂 2 0を配置できるので、 半導体基板 1 2をダイシングする際に異方性導電樹脂 2 0が邪魔にならない点で好ましい。 続いて、 約 8 0 °C〜 1 0 0 C程度の温度で半導体基板 1 2を加熱 （仮焼成） する ことによって、 異方性導電樹脂 2 0の中に含まれる溶媒の一部を蒸発させて異方性 導電樹脂 2 0を幾分固めることができる。異方性導電樹脂 2 0が幾分でも固まると、 配置した異方性導電樹脂 2 0の隅の部分が流れ出して形がくずれることがなくなる c また、 その後の半導体基板 1 2の取扱いも容易になる。 その後、 図示しないダイシングを用いて半導体基板 1 2をダイシングライン aで 切断して、 第 4図に示すように単個の半導体チップ 2に分割する。 この半導体チッ プ 2は、 その表面に電極パッド 1 4上に開口部 1 6 aを有する絶縁膜 1 6が形成さ れており、 この発明で使用する半導体装置 1 0となる。 Also, a paste-like resin is used as the anisotropic conductive resin 20. In addition to the spin coating method, a printing method, specifically, a screen printing method may be used. According to the screen printing method, since the anisotropic conductive resin 20 can be arranged without the dicing line, the anisotropic conductive resin 20 is not hindered when the semiconductor substrate 12 is diced. Subsequently, by heating (temporarily firing) the semiconductor substrate 12 at a temperature of about 80 ° C. to 100 ° C., a part of the solvent contained in the anisotropic conductive resin 20 is evaporated. Thus, the anisotropic conductive resin 20 can be hardened somewhat. When the anisotropic conductive resin 2 0 solidifies in somewhat, c that form flow out the corner portion of the anisotropic conductive resin 2 0 disposed is lost is eliminated also easily subsequent semiconductor substrate 1 2 handling Become. Thereafter, the semiconductor substrate 12 is cut along a dicing line a using dicing (not shown), and divided into single semiconductor chips 2 as shown in FIG. The semiconductor chip 2 has an insulating film 16 having an opening 16a formed on the electrode pad 14 on the surface thereof, and becomes a semiconductor device 10 used in the present invention.
以上の工程では、 半導体基板 1 2からダイシングによる切断によって、 半導体装 置 1 0を製造するまでの工程で、 異方性導電樹脂 2 0を配置する工程と仮焼成のェ 程とを実施している。 しかし、 これらの工程の順序を変更してもよく、 第 7図に示 した半導体基板 1 2を先にダイシングにより切断して、 第 6図に示す半導体装置 1 0とした後に、 異方性導電樹脂 2 0を配置して仮焼成を行なってもよい。  In the above process, the process of arranging the anisotropic conductive resin 20 and the process of calcination are carried out in the process up to the manufacture of the semiconductor device 10 by cutting from the semiconductor substrate 12 by dicing. I have. However, the order of these steps may be changed. The semiconductor substrate 12 shown in FIG. 7 is first cut by dicing to obtain a semiconductor device 10 shown in FIG. Preliminary baking may be performed by disposing the resin 20.
この場合は、 異方性導電樹脂 2 0は、 ペース ト状よりもフィルム状になっている ものを用いるのがよい。 例えば、 異方性導電樹脂 2 0がロール状に巻き付けられた ベ一スフイルム上に形成されているものを用いる。 この場合は、 そのベースフィル ムごと予め異方性導電樹脂 2 0を転写しようとする領域に合わせて力ッ トし、 その カットした異方性導電樹脂 2 0を半導体チップ 2上に配置する。  In this case, it is preferable that the anisotropic conductive resin 20 has a film shape rather than a paste shape. For example, an anisotropic conductive resin 20 formed on a base film wound in a roll shape is used. In this case, the base film is pre-tensioned in accordance with the region where the anisotropic conductive resin 20 is to be transferred, and the cut anisotropic conductive resin 20 is placed on the semiconductor chip 2.
次に、 第 5図に示すように、 実装する回路基板 2 6上に半導体装置 1 0を配置し て各電極パッド 1 4と回路電極 2 8とが対向するように位置合わせを行う。さらに、 各半導体装置 1 0毎に半導体チップ 2側から超音波ツール 2 4により超音波振動と 荷重を加える。 このとき、 加える超音波の周波数は、 約 2 0〜 3 0 K H zとし、 荷 重の大きさは、 6 0〜 2 0 0 k g / c m 2程度とする。 また、 超音波を印加する時 間は、 1回当たり約 0 . 5〜 2秒の程度とする。 さらに好ましくは、 回路基板 2 6 側より約 1 5 0 ：〜 2 0 0 °C程度の温度で加熱を行う。 Next, as shown in FIG. 5, the semiconductor device 10 is disposed on the circuit board 26 to be mounted, and alignment is performed so that the electrode pads 14 and the circuit electrodes 28 face each other. Further, an ultrasonic vibration and a load are applied by the ultrasonic tool 24 from the semiconductor chip 2 side for each semiconductor device 10. At this time, the frequency of the ultrasonic wave to be applied is about 20 to 30 KHz, and the magnitude of the load is about 60 to 200 kg / cm2. The time for applying ultrasonic waves is about 0.5 to 2 seconds per application. More preferably, heating is performed at a temperature of about 150: up to about 200 ° C. from the circuit board 26 side.
この工程を経ることによって、 異方性導電樹脂 2 0がつぶれて中に含まれる導電 性粒子 1 8が電極パッド 1 4と回路電極 2 8との間に挟み込まれ、 その導電性粒子 1 8 ( 1 8 a ) により電極パッド 1 4と回路電極 2 8 との電気的な導通が確保され る。 また、 超音波による振動エネルギが導電性粒子 1 8に加えられたことで、 導電 性粒子 1 8 a と電極パッ ド 1 4及び回路電極 2 8との接続点 a、 bで、金属原子（分 子） が相互に相手方に拡散して拡散接合が形成される。 さらに、 熱エネルギが加わ れば良好な拡散接合が形成される。 この拡散接合の形成とともに、 半導体装置 1 0 を回路基板 2 6に実装することができる。 Through this step, the anisotropic conductive resin 20 is crushed and the conductive particles 18 contained therein are sandwiched between the electrode pad 14 and the circuit electrode 28, and the conductive particles 18 ( By 18 a), electrical continuity between the electrode pad 14 and the circuit electrode 28 is ensured. In addition, the vibration energy generated by the ultrasonic waves was applied to the conductive particles 18 to increase the conductivity. At connection points a and b between the conductive particles 18a and the electrode pads 14 and the circuit electrodes 28, metal atoms (molecules) diffuse into each other to form a diffusion junction. In addition, good diffusion bonding is formed when heat energy is applied. With the formation of the diffusion junction, the semiconductor device 10 can be mounted on the circuit board 26.
このように、 この発明による半導体装置の実装方法によれば、 導電性粒子 1 8を 混在させた異方性導電樹脂 2 0を用いた拡散接合により、 半導体装置 1 0を回路基 板 2 6に実装することができるので、 従来のように、 半導体装置に突起電極を設け る必要がない。 そのため、 突起電極を形成するために必要なめっき工程、 フォ トリ ソ工程およびエッチング工程が省かれるため、 製造工程を大幅に短縮しかつ簡便な ものとすることができる。 しかも、 これらの工程に必要なめっき装置、 フォ トリ ソ 装置、 エッチング装置など非常に高価な装置も不要となり、 実装にかかるコス トを 大幅に低減することができる。  As described above, according to the semiconductor device mounting method of the present invention, the semiconductor device 10 is attached to the circuit board 26 by diffusion bonding using the anisotropic conductive resin 20 in which the conductive particles 18 are mixed. Since the semiconductor device can be mounted, there is no need to provide a bump electrode on the semiconductor device as in the conventional case. Therefore, a plating step, a photolithography step, and an etching step required for forming the protruding electrode are omitted, so that the manufacturing process can be greatly reduced and simplified. In addition, very expensive equipment such as a plating apparatus, a photolithography apparatus, and an etching apparatus required for these steps is not required, and the mounting cost can be significantly reduced.
また、 突起電極が不要で且つ半導体装置 1 0の電極パッ ド 1 4 と回路基板 2 6の 回路電極 2 8とを異方性導電樹脂 2 0中の導電性粒子 1 8 a との拡散接合により接 合しているので、 高密度で信頼性の高い実装構造が得られる。  In addition, a projecting electrode is unnecessary, and the electrode pad 14 of the semiconductor device 10 and the circuit electrode 28 of the circuit board 26 are formed by diffusion bonding with the conductive particles 18a in the anisotropic conductive resin 20. Since they are connected, a high-density and highly reliable mounting structure can be obtained.
さらに、 異方性導電樹脂 2 0が封止樹脂として機能するため、 半導体チップ 2と 回路基板 2 6 との接続と、 その接続部の封止とを同時に行なうことができる。 した がって、 従来行なっていた封止樹脂の注入工程が不要となり、 製造工程が一層簡略 化される。 産業上の利用可能性  Furthermore, since the anisotropic conductive resin 20 functions as a sealing resin, the connection between the semiconductor chip 2 and the circuit board 26 and the sealing of the connection portion can be performed simultaneously. Therefore, the step of injecting the sealing resin, which has been conventionally performed, becomes unnecessary, and the manufacturing process is further simplified. Industrial applicability
この発明による半導体装置の実装構造およびその実装方法によれば、異方性導電 樹脂に含まれる導電性粒子による電極パッ ド及び回路電極との拡散接合によって、 半導体装置が回路基板に接続して固定されるので、 その接続状態が確実であり、 高 密度でしかも信頼性の高い実装構造が得られる。 また、 半導体装置に突起電極を形 成する必要がないので、 その製造工程が大幅に短縮され、 製造コス ト及び実装にか かるコス トが大幅に削減される。 したがって、 多数の I Cや L S I等の半導体装置 を回路基板に表面実装する液晶表示装置をはじめ、携帯用電子機器やその他の各種 電子機器に対し広範に利用できる。 According to the mounting structure and the mounting method of the semiconductor device according to the present invention, the semiconductor device is connected to the circuit board and fixed by diffusion bonding with the electrode pad and the circuit electrode by the conductive particles contained in the anisotropic conductive resin. Therefore, the connection state is reliable, and a high-density and highly reliable mounting structure can be obtained. Also, projecting electrodes are formed on semiconductor devices. Since there is no need to perform this process, the manufacturing process is greatly shortened, and the manufacturing costs and mounting costs are greatly reduced. Therefore, it can be widely used for portable electronic devices and various other electronic devices, including liquid crystal display devices in which many semiconductor devices such as ICs and LSIs are surface-mounted on circuit boards.

Claims

請 求 の 範 囲 The scope of the claims
1 . 集積回路およびそれを外部に接続するための複数の電極パッドを設けた半導体 チップ上の表面に前記各電極パッド上に開口部を有する絶縁膜を形成した半導体装 置を、 パターニングされた回路電極を有する回路基板に実装した半導体装置の実装 構造であって、 1. A circuit in which an integrated circuit and a semiconductor device in which an insulating film having an opening on each of the electrode pads is formed on a surface of a semiconductor chip provided with a plurality of electrode pads for connecting the integrated circuit to the outside is patterned. A mounting structure of a semiconductor device mounted on a circuit board having electrodes,
前記半導体装置の前記絶縁膜を形成した面の略全域と前記回路基板の前記回路電 極を有する面との間に、 導電性粒子を混在した異方性導電樹脂を介在し、  An anisotropic conductive resin mixed with conductive particles is interposed between substantially the entire surface of the semiconductor device on which the insulating film is formed and the surface of the circuit board having the circuit electrodes;
前記導電性粒子が前記電極パッド及び前記回路電極と拡散接合していることを特 徴とする半導体装置の実装構造。  A semiconductor device mounting structure, wherein the conductive particles are diffusion-bonded to the electrode pad and the circuit electrode.
2 .前記導電性粒子が金からなる請求の範囲第 1項に記載の半導体装置の実装構造。 2. The mounting structure of a semiconductor device according to claim 1, wherein the conductive particles are made of gold.
3 . 前記導電性粒子が銅等の金属を核とし、 その表面に金又は白金等の拡散接合し やすい別の金属を被膜してなる請求の範囲第 1項に記載の半導体装置の実装構造。3. The mounting structure of a semiconductor device according to claim 1, wherein the conductive particles have a core such as copper as a nucleus and have a surface coated with another metal such as gold or platinum which is easily diffused and bonded.
4 . 前記導電性粒子が樹脂粒子の表面に金属膜を形成してなる請求の範囲第 1項に 記載の半導体装置の実装構造 4. The semiconductor device mounting structure according to claim 1, wherein the conductive particles are formed by forming a metal film on the surface of resin particles.
5 . 集積回路およびそれを外部に接続するための複数の電極パッドを設けた半導体 チップの表面に前記各電極パッド上に開口部を有する絶縁膜を形成した半導体装置 の前記絶縁膜を形成した面の略全域に、 導電性粒子を混在した異方性導電樹脂を配 置する工程と、  5. A surface of a semiconductor device in which an insulating film having an opening on each of the electrode pads is formed on a surface of a semiconductor chip provided with a plurality of electrode pads for connecting the integrated circuit to the outside and the surface where the insulating film is formed. Disposing an anisotropic conductive resin mixed with conductive particles over substantially the entire area of
その各半導体装置を、 回路電極を有する回路基板上に、 前記異方性導電樹脂を介 して前記各電極パッドと前記回路電極とを対向させるように位置合わせして配置す る工程と、  Arranging each of the semiconductor devices on a circuit board having a circuit electrode so that the electrode pads and the circuit electrode face each other via the anisotropic conductive resin;
前記半導体装置に超音波を印加するとともに荷重を加える工程とを有する ことを特徴とする半導体装置の実装方法。  Applying an ultrasonic wave to the semiconductor device and applying a load to the semiconductor device.
6 . 請求の範囲第 5項に記載の半導体装置の実装方法において、 前記半導体装置の表面に異方性導電樹脂を配置する工程と、 その半導体装置を前 記回路基板上に配置する工程との間に、 8 0 °C〜 1 0 0 °C程度の温度で前記半導体 装置を加熱して前記異方性導電樹脂中の溶媒の一部を蒸発させる工程を有すること を特徴とする半導体装置の実装方法。 6. The method of mounting a semiconductor device according to claim 5, Between the step of disposing the anisotropic conductive resin on the surface of the semiconductor device and the step of disposing the semiconductor device on the circuit board, the temperature is set to about 80 ° C. to 100 ° C. A method for mounting a semiconductor device, comprising a step of heating a semiconductor device to evaporate a part of a solvent in the anisotropic conductive resin.
7 . 前記各半導体装置に超音波を印加するとともに荷重を加える工程中に、 前記回路基板側から加熱する請求の範囲第 5項に記載の半導体装置の実装方法。 7. The semiconductor device mounting method according to claim 5, wherein the semiconductor device is heated from the circuit board side during the step of applying a load and applying a ultrasonic wave to each of the semiconductor devices.
8 . 前記各半導体装置に超音波を印加するとともに荷重を加える工程中に、 前記回路基板側から加熱する請求の範囲第 6項に記載の半導体装置の実装方法。8. The method of mounting a semiconductor device according to claim 6, wherein heating is performed from a side of the circuit board during a step of applying a load and applying a ultrasonic wave to each of the semiconductor devices.
9 . 前記回路基板側から加熱する温度が 1 5 0 °C〜 2 0 0 °C程度である請求の範囲 第 7項に記載の半導体装置の実装方法。 9. The method for mounting a semiconductor device according to claim 7, wherein a temperature of heating from the circuit board side is about 150 ° C. to 200 ° C.
1 0 . 前記回路基板側から加熱する温度が 1 5 0 °C〜 2 0 0 °C程度である請求の範 囲第 8項に記載の半導体装置の実装方法。  10. The method for mounting a semiconductor device according to claim 8, wherein the temperature heated from the circuit board side is about 150 ° C. to 200 ° C.
PCT/JP2000/001791 1999-03-23 2000-03-23 Structure for mounting semiconductor device and mounting method WO2000057469A1 (en)

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