WO2000057469A1 - Structure et procédé de montage de semi-conducteur - Google Patents

Structure et procédé de montage de semi-conducteur Download PDF

Info

Publication number
WO2000057469A1
WO2000057469A1 PCT/JP2000/001791 JP0001791W WO0057469A1 WO 2000057469 A1 WO2000057469 A1 WO 2000057469A1 JP 0001791 W JP0001791 W JP 0001791W WO 0057469 A1 WO0057469 A1 WO 0057469A1
Authority
WO
WIPO (PCT)
Prior art keywords
semiconductor device
electrode
mounting
circuit board
circuit
Prior art date
Application number
PCT/JP2000/001791
Other languages
English (en)
Japanese (ja)
Inventor
Noboru Taguchi
Original Assignee
Citizen Watch Co., Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Citizen Watch Co., Ltd. filed Critical Citizen Watch Co., Ltd.
Publication of WO2000057469A1 publication Critical patent/WO2000057469A1/fr

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05022—Disposition the internal layer being at least partially embedded in the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/0502—Disposition
    • H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
    • H01L2224/05027—Disposition the internal layer being disposed in a recess of the surface the internal layer extending out of an opening
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/05568—Disposition the whole external layer protruding from the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/1182—Applying permanent coating, e.g. in-situ coating
    • H01L2224/11823—Immersion coating, e.g. in a solder bath
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/13076—Plural core members being mutually engaged together, e.g. through inserts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/273—Manufacturing methods by local deposition of the material of the layer connector
    • H01L2224/2731—Manufacturing methods by local deposition of the material of the layer connector in liquid form
    • H01L2224/2732—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/274—Manufacturing methods by blanket deposition of the material of the layer connector
    • H01L2224/2741—Manufacturing methods by blanket deposition of the material of the layer connector in liquid form
    • H01L2224/27416—Spin coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/27—Manufacturing methods
    • H01L2224/278—Post-treatment of the layer connector
    • H01L2224/27848—Thermal treatments, e.g. annealing, controlled cooling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29301—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/29309—Indium [In] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29317—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/29324—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29339—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29338—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/29344—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29364—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298—Fillers
    • H01L2224/29299—Base material
    • H01L2224/293—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/29363—Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/29369—Platinum [Pt] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/822—Applying energy for connecting
    • H01L2224/82201—Compression bonding
    • H01L2224/82203—Thermocompression bonding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83851—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester being an anisotropic conductive adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01046—Palladium [Pd]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01049—Indium [In]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/0665—Epoxy resin
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads

Definitions

  • the present invention relates to a semiconductor device mounting structure in which a semiconductor device is connected and fixed on a circuit board using an anisotropic conductive resin, and a semiconductor device mounting method for mounting the same.
  • IC integrated circuits
  • LSI large-scale integrated circuits
  • surface mount type semiconductor devices are mounted on a circuit board such as a printed wiring board of various electronic devices or a glass substrate of a liquid crystal display panel, so that a large number of semiconductor devices are electrically and mechanically connected to the wiring pattern.
  • the projection electrodes (bumps) are arranged in rows.
  • FIG. 7 the structure of a conventional semiconductor device having a bump electrode formed thereon, its manufacturing method, and its mounting method will be described with reference to the cross-sectional views of FIGS. 7 to 13.
  • FIG. 7 the structure of a conventional semiconductor device having a bump electrode formed thereon, its manufacturing method, and its mounting method will be described with reference to the cross-sectional views of FIGS. 7 to 13.
  • FIG. 12 is a schematic cross-sectional view showing an example of a conventional semiconductor device provided with a bump electrode. For convenience of illustration, only two bump electrodes are shown. It is lined up.
  • the semiconductor device 1 has a large number of electrode pads 14 arranged on a surface of a semiconductor chip 2 on which an integrated circuit is formed.
  • An insulating film 16 having an opening 16a is formed on the surface of the semiconductor chip 2 so as to cover the periphery of each electrode pad 14 and expose the inside thereof.
  • the protruding electrodes 40 are provided on the respective electrode pads 14 through the openings 16 a of the insulating film 16 via the common electrode film 33.
  • the common electrode film 33 has a two-layer structure in which a first lower electrode layer 30 made of chrome and a second lower electrode layer 32 made of copper overlap.
  • Each protruding electrode 40 is formed in contact with the common electrode film 33. It has a two-layer structure consisting of a mushroom-shaped copper plating layer 34 and a solder plating layer 36 formed thereon.
  • the soldering layer 36 is rounded by the reflow process, and the upper portion has a shape close to a spherical surface.
  • FIG. 7 a method for manufacturing a conventional semiconductor device having the above-described structure will be described with reference to FIGS. 7 to 12.
  • a semiconductor device is manufactured by forming a large number of semiconductor chips at a time from a single semiconductor substrate (a wafer). Therefore, first, as shown in FIG. 7, an integrated circuit (not shown) is formed for each region corresponding to each semiconductor chip constituting a plurality of semiconductor devices, and is formed of aluminum for connecting the integrated circuit to the outside.
  • a semiconductor substrate 12 having a large number of electrode pads 14 arranged on its surface is prepared.
  • an insulating film 16 is formed so as to cover the entire surface.
  • an opening 16a is formed in a portion of the insulating film 16 corresponding to each electrode pad 14 by photoetching technology, and the electrode pad 14 is exposed inside the opening 16a.
  • a common electrode film 33 is formed on the entire surface of the semiconductor substrate 12 having the electrode pads 14 and the insulating film 16 by a sputtering method.
  • the common electrode film 33 is composed of a first lower electrode layer 30 of about 0.1 ⁇ m thick made of chromium and a second lower electrode layer 3 of about 0.4 m thick made of copper. 2 is formed in a two-layer structure.
  • the first lower electrode layer 30 has a role as a connection layer with the electrode pad 14 and a role as a barrier layer for preventing mutual diffusion between the electrode pad 14 and the second lower electrode layer 32.
  • the second lower electrode layer 32 has a role as an electrode when the bump electrode 40 is formed by the electroplating method and a role as a connection layer of the bump electrode 40.
  • a photosensitive resin 50 is formed on the entire surface of the common electrode film 33 to a thickness of about 5 ⁇ m by a spin coating method, and is exposed and developed by a photolithography technique, as shown in FIG. Then, the photosensitive resin 50 is patterned and an opening 50a is formed at a position corresponding to a portion where the protruding electrode 40 is to be formed.
  • the semiconductor substrate 12 is placed in a copper plating bath (not shown) in which a copper plating solution made of copper sulfate is maintained at a temperature of 25 ° C., and an electrode on the copper plating bath side and a common electrode film are formed. Under the condition that the current density of the current flowing between 3 and 3 is 3 AZdm, plating is selectively performed to form a copper plating layer 34 with a thickness of about 25 ⁇ m.
  • the semiconductor substrate 12 is put into a soldering bath (not shown) in which a soldering solution made of an organic acid is maintained at 25 ° C., and the electrodes on the soldering bath side and the common electrode film 3 are placed.
  • the same selective plating process is performed, and as shown in FIG. 10, soldering is performed on the copper plating layer 34.
  • the additional layer 36 is formed to a thickness of about 25 ⁇ m.
  • the copper plating layer 34 and the solder plating layer 36 are each formed with a thickness of about 25 ⁇ m for the following reason.
  • an underfill agent epoxy adhesive
  • the semiconductor device is mounted by a face-down mounting method
  • an underfill agent epoxy adhesive
  • circuit boards made of glass and epoxy resin which are generally used, have a warpage of about several tens of meters, so it is necessary to absorb the warpage and mount them in the face-down mounting method. It is necessary to secure a gap of about 50 ⁇ m between the semiconductor device and the circuit board.
  • the protruding electrode in a state where the soldering layer 36 is covered like an umbrella on the mushroom-shaped copper plating layer 34 is formed. 40 is obtained. Subsequently, using the protruding electrode 40 as a mask, the second lower electrode layer 32 and the first lower electrode layer 30 constituting the common electrode film 33 are wet-etched. Then, the soldered layer 36 is rolled up by reflow treatment by heating. .
  • the semiconductor substrate 12 is cut along the dicing line a using a dicing apparatus, and the semiconductor substrate 12 is equivalent to each semiconductor chip 2. The area is divided for each area. Then, as shown in FIG. 12, a semiconductor device 1 having a large number of projecting electrodes 40 on the semiconductor chip 2 is completed.
  • such a semiconductor device 1 has been mounted on a circuit board as follows. As shown in FIG. 13, the projecting electrode 40 and the circuit electrode 28 are superposed on a circuit board 26 on which the semiconductor device 1 is to be mounted. Subsequently, the soldering layer 36 is subjected to a reflow process to connect and fix the semiconductor device 1 on the circuit board 26. At this time, the positioning of both is performed in a self-aligned manner by the action of the surface tension of the soldered layer 36, so that the positions of the respective protruding electrodes 40 and the respective circuit electrodes 28 are slightly different from each other. Even if there is a deviation, the deviation of the position is delicately corrected and connected with an accuracy of ⁇ 10 m or less.
  • a sealing resin 38 made of epoxy is injected into a gap between the semiconductor chip 2 and the circuit board 26, and firing is performed.
  • the conventional semiconductor device 1 is mounted in a state where the protruding electrode 40 and the circuit electrode 28 are connected and fixed as shown in FIG.
  • the present invention has been made to solve the above-mentioned problems in the conventional mounting structure and mounting method of a semiconductor device.
  • the purpose is to enable easy and quick mounting and to enable low-cost, highly reliable and high-density mounting.
  • a mounting structure of a semiconductor device includes an integrated circuit and a plurality of electrode pads for connecting the integrated circuit to the outside.
  • the mounting structure of a semiconductor device in which a semiconductor device having an insulating film having a portion formed thereon is mounted on a circuit board having patterned circuit electrodes, and substantially the entire surface of the semiconductor device on which the insulating film is formed and the circuit board.
  • An anisotropic conductive resin mixed with conductive particles is interposed between the surface having the circuit electrodes and the conductive particles are diffusion-bonded to the electrode pads and the circuit electrodes.
  • the conductive particles are preferably made of gold.
  • the conductive particles may be made of a metal such as copper as a nucleus and the surface thereof is coated with another metal such as gold or platinum which is easily diffused and bonded, or a metal film is formed on the surface of the resin particles. ,.
  • a method of mounting a semiconductor device according to the present invention includes the following steps (1) to (3).
  • a temperature of about 80 ° C. to about 100 ° C. is applied between the step of disposing the anisotropic conductive resin on the surface of the semiconductor device and the step of disposing the semiconductor device on the circuit board.
  • the method for mounting a semiconductor device includes a step of heating the semiconductor device to evaporate a part of the solvent in the anisotropic conductive resin.
  • the temperature for heating from the circuit board side is about 150 ° C. to 200 ° C.
  • FIG. 1 is a schematic cross-sectional view showing one embodiment of a semiconductor device mounting structure according to the present invention.
  • FIG. 2 is a schematic sectional view showing a main part of the mounting structure of the semiconductor device shown in FIG.
  • FIG. 3 to FIG. 5 are schematic cross-sectional views sequentially showing each step for describing one embodiment of a method for mounting a semiconductor device according to the present invention.
  • FIG. 6 is a schematic sectional view showing a semiconductor chip used in a semiconductor device mounting method according to another procedure according to the present invention.
  • 7 to 12 are schematic cross-sectional views showing, in order, respective steps for describing a conventional method of manufacturing a semiconductor device.
  • FIG. 13 is a schematic cross-sectional view showing a mounting structure of a conventional semiconductor device.
  • FIGS. 1 to 6 Parts corresponding to those in the conventional example shown in FIGS. 7 to 13 are denoted by the same reference numerals.
  • the mounting structure of a semiconductor device according to the present invention is such that a semiconductor device 10 is mounted on a circuit board 26 via an anisotropic conductive resin 20. Then, the conductive particles 18 contained in the anisotropic conductive resin 20 are diffused and bonded to the electrode pad 14 and the circuit electrode 28 to electrically connect the electrode pad 14 and the circuit board 28. Connected and fixed.
  • a large number of electrode pads 14 are arranged on one surface of a semiconductor chip 2 on which an integrated circuit is formed in the same manner as before, and an opening 16a is formed on each electrode pad 14.
  • the insulating film 16 is formed.
  • the anisotropic conductive resin 20 is obtained by mixing a large number of conductive particles 18 into an insulating resin such as an epoxy resin or a phenol resin, and is disposed on the surface of the semiconductor chip 2 as shown in the figure. It has the property of having conductivity in the thickness direction, but not having conductivity in the other directions (parallel to the surface of the semiconductor chip 2).
  • an epoxy resin is used.
  • the anisotropic conductive resin 20 is arranged on the surface of the semiconductor chip 2 by a spin coating method.
  • a paste-like resin is used as the anisotropic conductive resin 20.
  • they may be arranged by a screen printing method or the like.
  • ACF anisotropic conductive film
  • the film thickness is about 10 ⁇ to about 30 when it is arranged on the surface of the semiconductor chip 2, but after being mounted on the circuit board 26, it is crushed by the pressing force.
  • the conductive particles 18 are particles made of a simple metal such as gold, palladium, platinum, silver, aluminum, or solder. Uses gold that is compatible with 8 and easily diffused.
  • the particle size must be larger than the thickness of the insulating film 16. If the particle size is smaller than the film thickness of the insulating film 16, it is not preferable because the electrode pad 14 and the circuit electrode 28 cannot be joined because they are buried in the gap between the openings 16 a. Specifically, considering that there is a certain degree of variation in the particle diameter and that the thickness of the insulating film 16 is about 1 ⁇ m, the average particle diameter is about 1.5 ⁇ to 5 ⁇ m. It is good to be about ⁇ m.
  • the conductive particles 18 may have a two-layer structure made of two types of metals, instead of one type of metal such as gold and platinum.
  • a core formed of a metal such as copper and coated with another metal (for example, gold or platinum) which is easily bonded to the surface thereof may be used.
  • metals such as titanium and iron are not very suitable as the material of the conductive particles 18.
  • a metal film may be formed by plating the surface of plastic resin particles.
  • the metal is preferably gold or platinum, and gold is particularly preferably used. Gold or platinum is preferable because it can be easily diffused and bonded to the electrode pad 14 and can maintain a good connection state.
  • the amount of the conductive particles 18 to be added to the adhesive resin may be determined in consideration of the particle size, the size of the electrode pad 14, the pitch between the electrodes, and the like. % (wt. / 0) it is the anisotropic conductive resin 2 0 by kneading added in an amount of.
  • Electrode pad 14 and circuit electrode 2 8 are surely connected by diffusion bonding in which metal atoms (molecules) diffuse to each other at connection points a and b with the conductive particles 18 respectively.
  • ultrasonic waves are applied from the back surface of the semiconductor chip 2 (the surface on which the electrode pads 14 are not formed), a load is applied, and the semiconductor chip 2 is further heated from the circuit board 26 side.
  • a load is applied
  • the semiconductor chip 2 is further heated from the circuit board 26 side.
  • the vibration energy due to the ultrasonic wave is transmitted to the conductive particles 18 via the electrode pads 14, and the conductive particles 18 which have received the vibration energy are shaken, and the electrode pads 14 and the circuit Friction occurs on the surface of the electrode 28, and thermal energy due to the friction is applied to the contact portion, thereby promoting diffusion bonding.
  • the electrode pad 14 is made of aluminum, a thin oxide film 14a is formed on the surface of the electrode pad 14, but the conductive particles 18 are not swayed when they are shaken. Breaks through the oxide film 14a and makes direct contact with the aluminum surface 14b of the electrode pad 14. Thus, electrical connection by diffusion bonding is ensured.
  • the conductive particles 18 may be vibrated by heating without applying ultrasonic waves.
  • diffusion bonding by application of ultrasonic waves is preferable because the energy required for applying vibration is applied not by heat energy but by ultrasonic waves, so that the mounting temperature can be realized at a low temperature. Mounting at low temperature has the following two effects.
  • the anisotropic conductive resin 20 may deteriorate or adversely affect the operation of elements provided in the semiconductor chip 2. Also, as shown in this mounting structure, if things with different properties are densely packed in a narrow area, the difference in linear expansion coefficient will be promoted at high temperatures, resulting in distortion and deterioration of the connection situation. There is a risk. However, in the case of diffusion bonding by applying ultrasonic waves, mounting at a low temperature within a range where these effects do not occur can be achieved.
  • the conductive particles 18 are metal particles, they do not easily deform even when a load is applied during mounting. Therefore, no restoring force is generated when the particles are deformed.
  • connection can be made more reliably because the connection can be made using the restoring force due to deformation of the plastic particles.
  • a load about 400 kg / cm 2 ) that can deform the plastic particles must be applied.
  • the conductive particles 18 are made of metal particles, there is no need to deform them, so the load may be about 60 to 200 kg Zcm 2 which is half or less. With such a load, there is no possibility that circuit elements in the semiconductor chip 2 will be adversely affected. Although the conductive particles 18 hardly exert a restoring force due to deformation, they are connected by diffusion bonding, so that the connection state is sufficiently good and reliable.
  • the semiconductor device 10 electrically and physically connects the electrode pad 14 and the circuit electrode 28 via the conductive particles 18 in the anisotropic conductive resin 20. Therefore, the pitch between the electrode pads 14 and the electrode pads 14 and the circuit electrodes 28 are different from those of the conventional semiconductor device 1 in which bump electrodes are provided and mounted. Since the distance between them can be reduced, high-density mounting is possible. Furthermore, in the case of diffusion bonding by applying ultrasonic waves, the connection state is more reliable and high reliability is obtained.
  • FIG. 1 a mounting method for obtaining the mounting structure of the semiconductor device shown in FIG. 1 will be described with reference to FIGS. Also in this case, a large number of semiconductor devices are manufactured at once from a single semiconductor substrate (a wafer).
  • each half of the plurality of semiconductor devices is formed.
  • An integrated circuit (not shown) is formed for each region corresponding to the conductive chip, and a semiconductor substrate 12 is prepared in which a large number of aluminum electrode pads 14 for connecting the integrated circuit to the outside are arranged on the upper surface. .
  • an insulating film 16 is formed so as to cover the entire upper surface.
  • an opening 16a is formed in a portion of the insulating film 16 corresponding to each electrode pad 14 by a photo-etching technique, and the electrode pad 14 is exposed inside.
  • the insulating film 16 is formed by forming a silicon nitride film by a plasma-enhanced chemical vapor deposition (plasma CVD) method, and has a film thickness of about ⁇ . Further, in addition to silicon nitride, an inorganic film such as silicon dioxide, tantalum oxide, or aluminum oxide may be used, and a sputtering method may be used as a formation method.
  • plasma CVD plasma-enhanced chemical vapor deposition
  • an anisotropic conductive resin 20 mixed with conductive particles 18 is applied to the entire surface of the semiconductor substrate 12 on which the insulating film 16 is formed by a spin coating method.
  • the film thickness is about ⁇ ⁇ ⁇ !
  • a film is formed to have a thickness of about 30 m.
  • the conductive particles 18 are made of gold particles having a particle size of about 5 m, but may be made of indium, palladium, platinum, silver, aluminum, solder, or plastic particles other than gold. May be formed.
  • a paste-like resin is used as the anisotropic conductive resin 20.
  • a printing method specifically, a screen printing method may be used. According to the screen printing method, since the anisotropic conductive resin 20 can be arranged without the dicing line, the anisotropic conductive resin 20 is not hindered when the semiconductor substrate 12 is diced. Subsequently, by heating (temporarily firing) the semiconductor substrate 12 at a temperature of about 80 ° C. to 100 ° C., a part of the solvent contained in the anisotropic conductive resin 20 is evaporated. Thus, the anisotropic conductive resin 20 can be hardened somewhat.
  • the semiconductor substrate 12 is cut along a dicing line a using dicing (not shown), and divided into single semiconductor chips 2 as shown in FIG.
  • the semiconductor chip 2 has an insulating film 16 having an opening 16a formed on the electrode pad 14 on the surface thereof, and becomes a semiconductor device 10 used in the present invention.
  • the process of arranging the anisotropic conductive resin 20 and the process of calcination are carried out in the process up to the manufacture of the semiconductor device 10 by cutting from the semiconductor substrate 12 by dicing. I have. However, the order of these steps may be changed.
  • the semiconductor substrate 12 shown in FIG. 7 is first cut by dicing to obtain a semiconductor device 10 shown in FIG. Preliminary baking may be performed by disposing the resin 20.
  • the anisotropic conductive resin 20 has a film shape rather than a paste shape.
  • an anisotropic conductive resin 20 formed on a base film wound in a roll shape is used.
  • the base film is pre-tensioned in accordance with the region where the anisotropic conductive resin 20 is to be transferred, and the cut anisotropic conductive resin 20 is placed on the semiconductor chip 2.
  • the semiconductor device 10 is disposed on the circuit board 26 to be mounted, and alignment is performed so that the electrode pads 14 and the circuit electrodes 28 face each other. Further, an ultrasonic vibration and a load are applied by the ultrasonic tool 24 from the semiconductor chip 2 side for each semiconductor device 10.
  • the frequency of the ultrasonic wave to be applied is about 20 to 30 KHz, and the magnitude of the load is about 60 to 200 kg / cm2.
  • the time for applying ultrasonic waves is about 0.5 to 2 seconds per application. More preferably, heating is performed at a temperature of about 150: up to about 200 ° C. from the circuit board 26 side.
  • the anisotropic conductive resin 20 is crushed and the conductive particles 18 contained therein are sandwiched between the electrode pad 14 and the circuit electrode 28, and the conductive particles 18 ( By 18 a), electrical continuity between the electrode pad 14 and the circuit electrode 28 is ensured.
  • the vibration energy generated by the ultrasonic waves was applied to the conductive particles 18 to increase the conductivity.
  • metal atoms (molecules) diffuse into each other to form a diffusion junction.
  • good diffusion bonding is formed when heat energy is applied. With the formation of the diffusion junction, the semiconductor device 10 can be mounted on the circuit board 26.
  • the semiconductor device 10 is attached to the circuit board 26 by diffusion bonding using the anisotropic conductive resin 20 in which the conductive particles 18 are mixed. Since the semiconductor device can be mounted, there is no need to provide a bump electrode on the semiconductor device as in the conventional case. Therefore, a plating step, a photolithography step, and an etching step required for forming the protruding electrode are omitted, so that the manufacturing process can be greatly reduced and simplified. In addition, very expensive equipment such as a plating apparatus, a photolithography apparatus, and an etching apparatus required for these steps is not required, and the mounting cost can be significantly reduced.
  • the electrode pad 14 of the semiconductor device 10 and the circuit electrode 28 of the circuit board 26 are formed by diffusion bonding with the conductive particles 18a in the anisotropic conductive resin 20. Since they are connected, a high-density and highly reliable mounting structure can be obtained.
  • the anisotropic conductive resin 20 functions as a sealing resin, the connection between the semiconductor chip 2 and the circuit board 26 and the sealing of the connection portion can be performed simultaneously. Therefore, the step of injecting the sealing resin, which has been conventionally performed, becomes unnecessary, and the manufacturing process is further simplified.
  • the semiconductor device is connected to the circuit board and fixed by diffusion bonding with the electrode pad and the circuit electrode by the conductive particles contained in the anisotropic conductive resin. Therefore, the connection state is reliable, and a high-density and highly reliable mounting structure can be obtained. Also, projecting electrodes are formed on semiconductor devices. Since there is no need to perform this process, the manufacturing process is greatly shortened, and the manufacturing costs and mounting costs are greatly reduced. Therefore, it can be widely used for portable electronic devices and various other electronic devices, including liquid crystal display devices in which many semiconductor devices such as ICs and LSIs are surface-mounted on circuit boards.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

Dans le cadre de ce procédé, on intercale une résine à conductivité anisotropique mêlée à des particules conductrices entre un dispositif à semi-conducteur (10) comprenant une microplaquette à semi-conducteur (2), portant des barres d'électrode (14) et revêtue d'un film isolant pourvu d'ouvertures (16a) au-dessus des barres d'électrode (14), et une carte de circuit imprimé (26), comportant des électrodes de circuit (28). Les particules conductrices (18) sont liées par diffusion aux barres d'électrode (14) ainsi qu'aux électrodes de circuit (28). Le dispositif à semi-conducteur (10) est, de la sorte, monté sur la carte de circuit imprimé (26).
PCT/JP2000/001791 1999-03-23 2000-03-23 Structure et procédé de montage de semi-conducteur WO2000057469A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP07731499A JP2003152023A (ja) 1999-03-23 1999-03-23 半導体装置の接続構造とその製造方法
JP11/77314 1999-03-23

Publications (1)

Publication Number Publication Date
WO2000057469A1 true WO2000057469A1 (fr) 2000-09-28

Family

ID=13630472

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2000/001791 WO2000057469A1 (fr) 1999-03-23 2000-03-23 Structure et procédé de montage de semi-conducteur

Country Status (2)

Country Link
JP (1) JP2003152023A (fr)
WO (1) WO2000057469A1 (fr)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10063914A1 (de) * 2000-12-20 2002-07-25 Pac Tech Gmbh Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
WO2004070827A1 (fr) 2003-02-05 2004-08-19 Senju Metal Industry Co., Ltd. Procede d'interconnexion de bornes et procede de montage de dispositifs semi-conducteurs
JP2008311584A (ja) * 2007-06-18 2008-12-25 Elpida Memory Inc 半導体パッケージの実装構造
CN102856306A (zh) * 2012-09-29 2013-01-02 苏州晶方半导体科技股份有限公司 半导体器件系统级封装结构及封装模组
JP2019526935A (ja) * 2016-08-31 2019-09-19 アモセンス・カンパニー・リミテッドＡｍｏｓｅｎｓｅ Ｃｏ．， Ｌｔｄ． フレキシブルプリント回路基板の製造方法、およびそれにより製造されたフレキシブルプリント回路基板

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4902867B2 (ja) * 2006-04-19 2012-03-21 パナソニック株式会社 電子部品の接続方法及び突起電極の形成方法、並びに電子部品実装体及び突起電極の製造装置

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372880A2 (fr) * 1988-12-05 1990-06-13 Hitachi Chemical Co., Ltd. Composition pour connexion de circuits, procédé de connexion utilisant cette composition, et structure connectée de puces semi-conductrices
JPH09162235A (ja) * 1995-12-05 1997-06-20 Hitachi Chem Co Ltd Ｉｃチップの実装方法及び接続部材
JPH10189657A (ja) * 1996-12-27 1998-07-21 Rohm Co Ltd 端子間の接続方法、半導体チップの実装方法、半導体チップのボンディング方法、および端子間の接続構造
JPH10199934A (ja) * 1997-01-13 1998-07-31 Hitachi Ltd 半導体素子実装構造体及び半導体素子実装方法
JPH10199927A (ja) * 1996-12-27 1998-07-31 Texas Instr Japan Ltd 異方性導電膜付回路基体及び回路チップ並びにその製法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0372880A2 (fr) * 1988-12-05 1990-06-13 Hitachi Chemical Co., Ltd. Composition pour connexion de circuits, procédé de connexion utilisant cette composition, et structure connectée de puces semi-conductrices
JPH09162235A (ja) * 1995-12-05 1997-06-20 Hitachi Chem Co Ltd Ｉｃチップの実装方法及び接続部材
JPH10189657A (ja) * 1996-12-27 1998-07-21 Rohm Co Ltd 端子間の接続方法、半導体チップの実装方法、半導体チップのボンディング方法、および端子間の接続構造
JPH10199927A (ja) * 1996-12-27 1998-07-31 Texas Instr Japan Ltd 異方性導電膜付回路基体及び回路チップ並びにその製法
JPH10199934A (ja) * 1997-01-13 1998-07-31 Hitachi Ltd 半導体素子実装構造体及び半導体素子実装方法

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10063914A1 (de) * 2000-12-20 2002-07-25 Pac Tech Gmbh Kontakthöckeraufbau zur Herstellung eines Verbindungsaufbaus zwischen Substratanschlussflächen
US7007834B2 (en) 2000-12-20 2006-03-07 PAC Tech—Packaging Technologies GmbH Contact bump construction for the production of a connector construction for substrate connecting surfaces
WO2004070827A1 (fr) 2003-02-05 2004-08-19 Senju Metal Industry Co., Ltd. Procede d'interconnexion de bornes et procede de montage de dispositifs semi-conducteurs
US7524748B2 (en) 2003-02-05 2009-04-28 Senju Metal Industry Co., Ltd. Method of interconnecting terminals and method of mounting semiconductor devices
JP2008311584A (ja) * 2007-06-18 2008-12-25 Elpida Memory Inc 半導体パッケージの実装構造
CN102856306A (zh) * 2012-09-29 2013-01-02 苏州晶方半导体科技股份有限公司 半导体器件系统级封装结构及封装模组
JP2019526935A (ja) * 2016-08-31 2019-09-19 アモセンス・カンパニー・リミテッドＡｍｏｓｅｎｓｅ Ｃｏ．， Ｌｔｄ． フレキシブルプリント回路基板の製造方法、およびそれにより製造されたフレキシブルプリント回路基板
US11013128B2 (en) 2016-08-31 2021-05-18 Amosense Co., Ltd Method for manufacturing flexible printed circuit board and flexible printed circuit board manufactured by same

Also Published As

Publication number Publication date
JP2003152023A (ja) 2003-05-23

Similar Documents

Publication Publication Date Title
US7640655B2 (en) Electronic component embedded board and its manufacturing method
TW492120B (en) Semiconductor device and its manufacturing method, stacked type semiconductor device, circuit substrate and electronic machine
JP2825083B2 (ja) 半導体素子の実装構造
JP2002261190A (ja) 半導体装置、その製造方法及び電子機器
JPWO2007043639A1 (ja) プリント配線基板及びプリント配線基板の製造方法
JP2001168265A (ja) 電子デバイス集合体と電子デバイスの接続方法
US20080001271A1 (en) Flipped, stacked-chip IC packaging for high bandwidth data transfer buses
JP2001298115A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP3654116B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2004327480A (ja) 半導体装置及びその製造方法、電子装置及びその製造方法並びに電子機器
WO2000057469A1 (fr) Structure et procédé de montage de semi-conducteur
JP2002313985A (ja) チップサイズパッケージの製造方法
JP3925752B2 (ja) バンプ付き配線基板及び半導体パッケ−ジの製造法
JP4465891B2 (ja) 半導体装置
WO2000026959A1 (fr) Dispositif a semi-conducteur, son procede de fabrication, carte de circuit imprime et dispositif electronique
JP3394696B2 (ja) 半導体装置及びその製造方法
JP3800298B2 (ja) バンプの形成方法及び半導体装置の製造方法
JP2007150346A (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2000357710A (ja) 半導体装置の実装構造および実装方法
JP3500378B2 (ja) 半導体装置およびその製造方法
JP2004288815A (ja) 半導体装置及びその製造方法
JP3283947B2 (ja) 半導体装置およびその製造方法
JP2008177404A (ja) 半導体装置、半導体モジュールおよびその製造方法
JP2002176267A (ja) 電子部品、回路装置とその製造方法並びに半導体装置
JP2001351947A (ja) 半導体装置の製造方法およびその実装方法

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): JP US

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
122 Ep: pct application non-entry in european phase
NENP Non-entry into the national phase

Ref country code: JP