JPH09275165A - Circuit board and semiconductor device using the same - Google Patents
Circuit board and semiconductor device using the sameInfo
- Publication number
- JPH09275165A JPH09275165A JP9024733A JP2473397A JPH09275165A JP H09275165 A JPH09275165 A JP H09275165A JP 9024733 A JP9024733 A JP 9024733A JP 2473397 A JP2473397 A JP 2473397A JP H09275165 A JPH09275165 A JP H09275165A
- Authority
- JP
- Japan
- Prior art keywords
- bonding material
- conductive foil
- circuit pattern
- semiconductor device
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Structure Of Printed Boards (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、パワー半導体装置
の実装技術に係わり、特に、導電箔が接合された絶縁性
基板を備えたモジュール構造の半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mounting technique for a power semiconductor device, and more particularly to a semiconductor device having a module structure including an insulating substrate to which a conductive foil is joined.
【０００２】[0002]
【従来の技術】従来、パワー半導体素子を搭載するモジ
ュールは図４に示すように導電箔回路パターン３が付い
た絶縁性基板１からなる回路基板に半導体素子４が半田
６で接続される。この回路基板はモリブデンや銅などの
金属ベース基板８上に半田７を用いて接合されていた。
前記絶縁性基板１としては、酸化アルミニウムや窒化ア
ルミニウムなどのセラミックス基板が用いられてきた。
このセラミックス基板に回路パターンを形成する銅箔を
接合する方法としては、例えば特開昭60−177634号公報
に開示されている銀ろうによる活性金属法や、特開昭56
−163093号公報に開示されている銅と窒化アルミニウム
とを直接接合するＤＢＣ法がある。前記活性金属法によ
り接合した銅箔付絶縁性基板は、ＤＢＣ法に比べて低い
温度で接合するので、窒化アルミニウムと銅の熱膨脹率
の差に起因する残留応力が小さく、ヒートサイクルなど
の熱荷重に対して耐久性がある。2. Description of the Related Art Conventionally, in a module having a power semiconductor element mounted thereon, a semiconductor element 4 is connected by solder 6 to a circuit board made of an insulating substrate 1 having a conductive foil circuit pattern 3 as shown in FIG. This circuit board was bonded onto a metal base board 8 made of molybdenum, copper, or the like using solder 7.
As the insulating substrate 1, a ceramic substrate such as aluminum oxide or aluminum nitride has been used.
As a method for joining a copper foil for forming a circuit pattern to this ceramic substrate, for example, an active metal method using silver solder disclosed in JP-A-60-177634 and JP-A-56
There is a DBC method disclosed in Japanese Laid-Open Patent Publication No. 163093 in which copper and aluminum nitride are directly joined. Since the insulating substrate with a copper foil joined by the active metal method is joined at a lower temperature than the DBC method, the residual stress due to the difference in thermal expansion coefficient between aluminum nitride and copper is small, and the thermal load such as heat cycle is applied. Durable against.
【０００３】[0003]
【発明が解決しようとする課題】動作中の半導体素子４
から発生した熱は、導電箔回路パターン３が付いた絶縁
性基板１，モリブデンや銅などの金属ベース基板８，グ
リース９を介して冷却体１０から放熱される。このた
め、半導体素子動作時は、モジュール構成部材である導
電箔回路パターン３が付いた絶縁性基板１及び金属ベー
ス基板８の温度が上昇する。また、半導体素子４が動作
を停止しているときには、前記部分の温度が降下する。
このように、モジュール構成部材は、温度の上昇降下を
繰り返す。このために、導電箔回路パターン３と絶縁性
基板１との熱膨脹率の差により、熱応力が発生し、絶縁
性基板１にクラックが生じる場合がある。このクラック
により半導体素子４から金属ベース基板８，冷却体１０
への熱伝導が阻害されるために、半導体素子４の温度が
上昇し、半導体素子４が熱破壊を受ける問題があった。
本発明の目的は、パワー半導体素子を搭載したモジュー
ルにおいて、モジュールの温度変化による絶縁性基板の
クラックを生じにくい信頼性の高い回路基板及びそれを
用いた半導体装置を提供することにある。The semiconductor element 4 in operation.
The heat generated from the cooling body 10 is radiated through the insulating substrate 1 having the conductive foil circuit pattern 3, the metal base substrate 8 such as molybdenum or copper, and the grease 9. Therefore, during operation of the semiconductor device, the temperatures of the insulating substrate 1 and the metal base substrate 8 having the conductive foil circuit pattern 3 which is a module constituent member rise. Further, when the semiconductor element 4 stops operating, the temperature of the portion drops.
In this way, the module constituent members repeatedly rise and fall in temperature. Therefore, thermal stress may be generated due to the difference in coefficient of thermal expansion between the conductive foil circuit pattern 3 and the insulating substrate 1, and the insulating substrate 1 may be cracked. Due to this crack, the semiconductor element 4 to the metal base substrate 8 and the cooling body 10
Since the heat conduction to the semiconductor element 4 is hindered, the temperature of the semiconductor element 4 rises and the semiconductor element 4 is thermally damaged.
It is an object of the present invention to provide a highly reliable circuit board in which a power semiconductor element is mounted in a module, which is unlikely to cause cracks in the insulating substrate due to temperature change of the module, and a semiconductor device using the circuit board.
【０００４】[0004]
【課題を解決するための手段】本発明の半導体装置は、
金属ベース基板上に絶縁性基板と接合材と導電箔と半導
体素子を積層し該導電箔を該接合材により該絶縁性基板
に接合した半導体装置において、前記接合材の端部が前
記導電箔端部より外側に存在し、前記接合材端部のはみ
だし部の長さが、前記接合材の厚さより長く、前記接合
材端部のはみ出し部の厚さが０.１mm 以下である。According to the present invention, there is provided a semiconductor device comprising:
In a semiconductor device in which an insulating substrate, a bonding material, a conductive foil, and a semiconductor element are laminated on a metal base substrate and the conductive foil is bonded to the insulating substrate by the bonding material, the end of the bonding material is the conductive foil end. Existing outside the portion, the length of the protruding portion at the end of the bonding material is longer than the thickness of the bonding material, and the thickness of the protruding portion at the end of the bonding material is 0.1 mm or less.
【０００５】また、本発明の半導体装置は、金属ベース
基板上に絶縁性基板と接合材と導電箔と半導体素子を積
層し該導電箔を該接合材により該絶縁性基板に接合した
半導体装置において、前記接合材の面積が前記導電箔の
面積より広く、前記接合材端部のはみだし部の長さが、
前記接合材の厚さより長く、前記接合材端部のはみ出し
部の厚さが０.１mm 以下である。The semiconductor device of the present invention is a semiconductor device in which an insulating substrate, a bonding material, a conductive foil and a semiconductor element are laminated on a metal base substrate and the conductive foil is bonded to the insulating substrate by the bonding material. The area of the bonding material is wider than the area of the conductive foil, and the length of the protruding portion of the bonding material end is
The thickness of the protruding portion at the end of the bonding material is 0.1 mm or less, which is longer than the thickness of the bonding material.
【０００６】本発明の半導体装置は、金属ベース基板上
に絶縁性基板と接合材と導電箔と半導体素子を積層し該
導電箔を該接合材により該絶縁性基板に接合した半導体
装置において、前記接合材の接合パターンのコーナー部
の端部が前記導電箔の回路パターンのコーナー部の端部
より外側に存在し、前記接合材パターンのコーナー部の
端部の最大はみだし部の長さが、前記接合材の厚さより
長く、前記接合材パターンのコーナー部の端部の最大は
みだし部の厚さが０.１mm 以下である。The semiconductor device of the present invention is a semiconductor device in which an insulating substrate, a bonding material, a conductive foil and a semiconductor element are laminated on a metal base substrate and the conductive foil is bonded to the insulating substrate by the bonding material. The end portion of the corner portion of the bonding pattern of the bonding material is present outside the end portion of the corner portion of the circuit pattern of the conductive foil, the maximum protrusion length of the end portion of the corner portion of the bonding material pattern, It is longer than the thickness of the bonding material, and the thickness of the maximum protruding portion at the end of the corner portion of the bonding material pattern is 0.1 mm or less.
【０００７】本発明の半導体装置は、金属ベース基板上
に絶縁性基板と接合材と導電箔と半導体素子を積層し該
導電箔を該接合材により該絶縁性基板を接合した半導体
装置において、前記接合材の端部が前記導電箔端部より
外側に存在し、前記導電箔が複数の種類の接合材で前記
絶縁性基板に接合され、前記接合材が前記導電箔上にも
ある。The semiconductor device of the present invention is a semiconductor device in which an insulating substrate, a bonding material, a conductive foil, and a semiconductor element are laminated on a metal base substrate, and the conductive foil is bonded to the insulating substrate by the bonding material. An end portion of the bonding material exists outside the end portion of the conductive foil, the conductive foil is bonded to the insulating substrate with a plurality of kinds of bonding materials, and the bonding material is also on the conductive foil.
【０００８】なお上記各半導体装置において、絶縁性基
板と接合材と導電箔の積層されたものが回路基板に相当
する。In each of the above semiconductor devices, a laminate of an insulating substrate, a bonding material and a conductive foil corresponds to a circuit board.
【０００９】本発明によれば、接合材パターンの端部上
に導電箔が無い。このため、接合材パターンの端部下に
位置する絶縁基板の部分が加わる熱応力が低減される。According to the present invention, there is no conductive foil on the end of the bonding material pattern. For this reason, the thermal stress applied to the portion of the insulating substrate located below the end of the bonding material pattern is reduced.
【００１０】[0010]
（実施例１）図１の実施例により、本発明を従来技術と
比較しながら説明する。(Embodiment 1) The present invention will be described with reference to the embodiment of FIG.
【００１１】従来、導電箔回路パターン３が付いた絶縁
性基板１は、次のような方法で作製している。まず、絶
縁性基板１上に接合材２を回路パターン形状に印刷後、
銅箔を被せ、加圧接合する。その後、銅箔をエッチング
し所望の回路パターンを形成する。このとき、接合材２
のパターンは、エッチング後の銅箔の回路パターンと同
一形状になるように作製されていた。Conventionally, the insulating substrate 1 provided with the conductive foil circuit pattern 3 is manufactured by the following method. First, after printing the bonding material 2 in a circuit pattern shape on the insulating substrate 1,
Cover with copper foil and press bond. Then, the copper foil is etched to form a desired circuit pattern. At this time, the bonding material 2
The pattern was prepared so as to have the same shape as the circuit pattern of the copper foil after etching.
【００１２】通常、導電箔回路パターン３は、銅箔から
なり、絶縁性基板１はセラミックスからなる。銅の熱膨
脹率は１７×１０~6／℃であり、セラミックスの熱膨脹
率は、例えば酸化アルミニウムが６.５×１０~6／℃，
窒化アルミニウムが４.５×１０~6／℃である。このた
め、半導体素子４の動作時には、半導体素子４の発熱に
より、導電箔回路パターン３と絶縁性基板１との熱膨脹
率の差により、セラミックス基板上の導電箔回路パター
ン端部１４で最も大きな応力が発生する。Usually, the conductive foil circuit pattern 3 is made of copper foil, and the insulating substrate 1 is made of ceramics. The coefficient of thermal expansion of copper is 17 × 10 6 / ° C., and the coefficient of thermal expansion of ceramics is, for example, 6.5 × 10 6 / ° C. for aluminum oxide,
Aluminum nitride is 4.5 × 10 6 / ° C. Therefore, when the semiconductor element 4 is operating, the heat generated in the semiconductor element 4 causes a difference in coefficient of thermal expansion between the conductive foil circuit pattern 3 and the insulating substrate 1 to cause the greatest stress at the conductive foil circuit pattern end portion 14 on the ceramic substrate. Occurs.
【００１３】さらに、接合材の印刷マスクや回路エッチ
ングパターンの重ね合わせ精度などにより、接合材の端
部１５が導電箔回路パターン端部１４より内側に形成さ
れると前記応力集中が大きくなりセラミックス基板にク
ラックが生じやすくなる。また、導電箔回路パターン３
の厚さが増すほど、セラミックス基板に加わる応力が増
大する。このため、導電箔回路パターン端部１４を段部
を介して薄肉とする方法が特開平5−152461 号公報に開
示されている。しかし、プレス等の機械的手段やエッチ
ング等の化学的手段により端縁を薄くするために、プレ
スの加圧やエッチングによりセラミックス基板にクラッ
クが入る恐れがあった。これに対して、本発明では接合
材２の面積を導電箔回路パターン３の面積より広く設け
ることにより問題を解決した。即ち、導電箔回路パター
ンの端部１４と接合材の端部１５が揃っていないため、
導電箔回路パターン３の厚さにかかわらず、セラミック
ス基板に加わる応力集中が緩和される。導電箔回路パタ
ーン３を接合材２のパターンより内側に設け、セラミッ
クス基板と直接接する接合材２の厚さを回路パターンの
厚さより薄くすることにより、接合材の端部１５に集中
する応力が半分以下にすることが実験結果から明らかと
なった。もちろん、導電箔回路パターン３の端縁にテー
パを付け徐々に薄くしても良い。また従来通りのエッチ
ングを導電箔回路パターン３の端縁に行っても構わな
い。即ち、導電箔回路パターン３の作製方法や断面形状
は如何なるものでも構わない。これにより、電流を多く
流すために導電箔回路パターン３を厚くしてもセラミッ
クス基板の信頼性は確保できる。また、本発明は応力集
中が起こりやすい導電箔回路パターン３のコーナー部に
適用すると特に有効である。Further, when the end portion 15 of the bonding material is formed inside the end portion 14 of the conductive foil circuit pattern due to the printing mask of the bonding material, the overlay accuracy of the circuit etching pattern, and the like, the stress concentration increases and the ceramic substrate Cracks are likely to occur. Also, the conductive foil circuit pattern 3
As the thickness increases, the stress applied to the ceramic substrate increases. Therefore, a method of thinning the conductive foil circuit pattern end portion 14 through the step portion is disclosed in Japanese Patent Laid-Open No. 5-152461. However, since the edge is thinned by a mechanical means such as a press or a chemical means such as an etching, there is a possibility that the ceramic substrate may be cracked by pressurization or etching of the press. On the other hand, in the present invention, the problem is solved by providing the area of the bonding material 2 larger than the area of the conductive foil circuit pattern 3. That is, since the end portion 14 of the conductive foil circuit pattern and the end portion 15 of the bonding material are not aligned,
Regardless of the thickness of the conductive foil circuit pattern 3, stress concentration applied to the ceramic substrate is relieved. By providing the conductive foil circuit pattern 3 inside the pattern of the bonding material 2 and making the thickness of the bonding material 2 that is in direct contact with the ceramic substrate thinner than the thickness of the circuit pattern, the stress concentrated on the end portion 15 of the bonding material is halved. It became clear from the experimental results that the following is done. Of course, the edge of the conductive foil circuit pattern 3 may be tapered to be gradually thinned. Further, conventional etching may be performed on the edge of the conductive foil circuit pattern 3. That is, any method of manufacturing the conductive foil circuit pattern 3 and its cross-sectional shape may be used. As a result, the reliability of the ceramic substrate can be ensured even if the conductive foil circuit pattern 3 is thickened to allow a large amount of current to flow. Further, the present invention is particularly effective when applied to the corner portion of the conductive foil circuit pattern 3 where stress concentration is likely to occur.
【００１４】（実施例２）図２（ａ）に本実施例に用い
た導電箔回路パターン３が付いた絶縁性基板１の平面図
を示す。図２（ｂ）にＡ−Ａ断面図を示す。絶縁性基板
１として窒化アルミニウムを用いた。絶縁性基板１には
窒化アルミニウムの他に、例えば酸化アルミニウムや炭
化硅素などのセラミックスや、金属とセラミックスを積
層した複合材料など、電気絶縁性を備えた材料からなる
基板を用いることができる。接合材２には、銀と銅を主
成分とする銀ろうを用いた。導電箔回路パターン３とセ
ラミックス基板との熱膨脹率の差を緩和させるために、
銀ろうに導電箔回路パターン３の材質とセラミックス基
板の材質の中間の熱膨脹率を示す金属を添加すると良
い。また、好ましくは、窒化アルミニウム基板との接合
強度を上げるため、銀ろうに水素化チタンを添加すると
良い。本実施例では圧延銅箔を用いて導電箔回路パター
ン３を形成した。この導電箔回路パターン３が付いた絶
縁性基板１は、以下のようにして作製した。まず、窒化
アルミニウム基板の両面に、接合材２の銀ろうを所定の
パターンにスクリーン印刷し、乾燥した。次に、銅箔を
前記銀ろうが印刷された窒化アルミニウム基板の表と裏
に接触するように配置した後、スペーサを介して銅箔に
荷重を加えて加熱処理し、銅箔が接合された絶縁性基板
を得た。次に、この銅箔が接合された絶縁性基板をエッ
チング処理して、所定の導電箔回路パターン３を得た。
エッチング処理する際のレジストパターンは、エッチン
グ後の銅箔の回路パターンが最終的に銀ろうのパターン
より内側に形成されるように塗布した。以上の工程によ
り、図２（ａ）に示すように接合材２のパターンが、導
電箔回路パターン３より広い面積を有する絶縁性基板１
を得た。この導電箔回路パターン３が付いた絶縁性基板
１の銅箔に酸化防止処理として、無電解ニッケル−リン
メッキを行った。次にモリブデン製の金属ベース基板８
に前記絶縁性基板１及び電極端子（図示せず）を接合
後、ケース（図示せず）を接合し図１に示すモジュール
を得た。表１に作製したモジュールの−４０℃〜１２５
℃の温度サイクル信頼性試験結果を示す。(Embodiment 2) FIG. 2A shows a plan view of an insulating substrate 1 having a conductive foil circuit pattern 3 used in this embodiment. FIG. 2B shows a sectional view taken along line AA. Aluminum nitride was used as the insulating substrate 1. As the insulating substrate 1, in addition to aluminum nitride, a substrate made of a material having electrical insulation such as ceramics such as aluminum oxide or silicon carbide, or a composite material in which metal and ceramics are laminated can be used. As the bonding material 2, a silver brazing material containing silver and copper as main components was used. In order to reduce the difference in coefficient of thermal expansion between the conductive foil circuit pattern 3 and the ceramic substrate,
It is advisable to add a metal having a coefficient of thermal expansion intermediate to that of the material of the conductive foil circuit pattern 3 and the material of the ceramic substrate to the silver solder. Further, it is preferable to add titanium hydride to the silver brazing material in order to increase the bonding strength with the aluminum nitride substrate. In this example, the rolled copper foil was used to form the conductive foil circuit pattern 3. The insulating substrate 1 provided with the conductive foil circuit pattern 3 was produced as follows. First, silver solder of the bonding material 2 was screen-printed in a predetermined pattern on both surfaces of the aluminum nitride substrate and dried. Next, a copper foil was placed so as to contact the front and back of the aluminum nitride substrate on which the silver solder was printed, and then a load was applied to the copper foil via a spacer to perform heat treatment, and the copper foil was joined. An insulating substrate was obtained. Next, the insulating substrate to which this copper foil was joined was subjected to an etching treatment to obtain a predetermined conductive foil circuit pattern 3.
The resist pattern for the etching treatment was applied so that the circuit pattern of the copper foil after etching was finally formed inside the silver brazing pattern. Through the above steps, the insulating substrate 1 in which the pattern of the bonding material 2 has a larger area than the conductive foil circuit pattern 3 as shown in FIG.
I got Electroless nickel-phosphorus plating was performed on the copper foil of the insulating substrate 1 having the conductive foil circuit pattern 3 as an antioxidant treatment. Next, molybdenum metal base substrate 8
After the insulating substrate 1 and the electrode terminals (not shown) were joined to the above, a case (not shown) was joined to obtain the module shown in FIG. -40 ° C to 125 of the module prepared in Table 1
The temperature cycle reliability test results of ° C are shown.
【００１５】[0015]
【表１】 [Table 1]
【００１６】銀ろうが銅箔よりも広い面積形状を備えた
モジュールは、１０００サイクルの試験後でも、絶縁性
基板１のクラックによる銅箔の剥離は生じずモジュール
は正常に動作した。一方、銀ろうと銅箔が同じ面積形状
であるモジュールは、前記温度サイクル信頼性試験を行
った結果、２００サイクルで絶縁性基板１のクラックに
よる銅箔の剥離が生じた。また、銀ろうが銅箔より内側
にある面積形状の絶縁性基板を用いたモジュールは、２
０サイクルの試験で絶縁性基板のクラックによる銅箔の
剥離が生じた。With respect to the module in which the silver solder has a larger area shape than the copper foil, the copper foil was not peeled off due to cracks in the insulating substrate 1 even after the 1000-cycle test, and the module operated normally. On the other hand, in the module in which the silver solder and the copper foil have the same area shape, as a result of the temperature cycle reliability test, peeling of the copper foil due to cracks in the insulating substrate 1 occurred after 200 cycles. In addition, a module using an area-shaped insulating substrate in which the silver solder is inside the copper foil is
In the 0-cycle test, peeling of the copper foil occurred due to cracks in the insulating substrate.
【００１７】（実施例３）図３に本実施例に用いた導電
箔回路パターン３の平面図を示す。モジュールに大電流
を流すためには、導電箔回路パターン３を広く取ること
が好ましい。このため、導電箔回路パターン３の直線部
分は、接合材３の端部と導電箔回路パターン３の端部を
合わせ、導電箔回路パターン３のコーナー部では導電箔
回路パターン３の端部の曲率半径を接合材２のパターン
の端部の曲率半径より大きくし、導電箔回路パターン３
のコーナー部において、接合材２がはみ出している形状
とした。本実施例のモジュールを用いた温度サイクル試
験を行った結果、１０００サイクルでも絶縁性基板１に
クラックが生じずモジュールは正常に動作した。(Embodiment 3) FIG. 3 shows a plan view of the conductive foil circuit pattern 3 used in this embodiment. In order to pass a large current through the module, it is preferable to make the conductive foil circuit pattern 3 wide. Therefore, the straight portion of the conductive foil circuit pattern 3 is aligned with the end of the bonding material 3 and the end of the conductive foil circuit pattern 3, and the curvature of the end of the conductive foil circuit pattern 3 at the corner of the conductive foil circuit pattern 3. The radius is made larger than the radius of curvature of the end of the pattern of the bonding material 2, and the conductive foil circuit pattern 3 is formed.
In the corner portion of the above, the bonding material 2 is formed to protrude. As a result of a temperature cycle test using the module of the present example, the insulating substrate 1 did not crack even after 1000 cycles, and the module operated normally.
【００１８】本実施例に示すように、必ずしも導電箔回
路パターン３全周に渡って銀ろうが外側にはみ出してい
なくてもよく、導電箔回路パターン３のコーナー部だけ
でも、銀ろうが導電箔より外側にはみ出していればよ
い。As shown in the present embodiment, the silver brazing material does not necessarily have to extend to the outside over the entire circumference of the conductive foil circuit pattern 3, and the silver brazing material is not covered with the conductive foil circuit pattern 3 only at the corners. It only has to protrude to the outside.
【００１９】（実施例４）導電箔回路パターン端部１４
からの接合材端部のはみ出し部１６の長さを種々変えた
モジュールを作製した。モジュールの作製方法は、実施
例１と同様である。本実施例では、導電箔回路パターン
の銅箔の厚さを０.３mm 一定とした。また、接合材の厚
さは０.０３mm 一定とした。図５に導電箔回路パターン
端部１４からの接合材端部のはみ出し部１６の長さを変
えた場合の、クラックが発生した温度サイクル数を示
す。モジュールの実用上、温度サイクル試験５００サイ
クルまではクラックの発生を抑えなければならない。接
合材端部のはみ出し部の長さが０.０２mm のモジュール
は、４００サイクルからクラックが発生し、該はみ出し
部の長さが０.０３mm のモジュールでは８００サイクル
からクラックが発生した。このように、接合材端部のは
み出し部の長さ１６が、接合材の厚さ以上であれば、実
用上、クラックの発生を防ぐことができる。(Embodiment 4) Conductive foil circuit pattern end portion 14
Modules having various lengths of the protruding portion 16 at the end of the joining material from No. 3 were produced. The method of manufacturing the module is the same as that of the first embodiment. In this embodiment, the thickness of the copper foil of the conductive foil circuit pattern is fixed at 0.3 mm. Further, the thickness of the bonding material was fixed to 0.03 mm. FIG. 5 shows the number of temperature cycles in which a crack is generated when the length of the protruding portion 16 at the end of the bonding material from the end 14 of the conductive foil circuit pattern is changed. In practical use of the module, it is necessary to suppress the generation of cracks until the temperature cycle test reaches 500 cycles. The module with the length of the protruding portion at the end of the bonding material of 0.02 mm generated cracks after 400 cycles, and the module with the length of the protruding portion of 0.03 mm generated cracks after 800 cycles. As described above, when the length 16 of the protruding portion at the end of the bonding material is equal to or larger than the thickness of the bonding material, it is possible to practically prevent the generation of cracks.
【００２０】（実施例５）導電箔回路パターン３を形成
する銅箔の厚さを種々変えたモジュールを作製した。モ
ジュールの作製方法は、実施例１と同様である。接合材
２の厚さは0.03mm一定とした。導電箔回路パターン端部
１４からの接合材のはみ出し部１６の長さは０.１mm 一
定とした。導電箔回路パターン３の銅箔の厚さを０.
１，０.３，０.６ ，１，２mmと変えて、温度サイクル
試験を行った。１０００サイクルまで試験したが、いず
れのモジュールにおいてもセラミックス基板にクラック
は発生せずモジュールは正常に動作した。Example 5 Modules having various thicknesses of copper foil forming the conductive foil circuit pattern 3 were produced. The method of manufacturing the module is the same as that of the first embodiment. The thickness of the bonding material 2 was constant at 0.03 mm. The length of the protruding portion 16 of the bonding material from the end portion 14 of the conductive foil circuit pattern was constant at 0.1 mm. The thickness of the copper foil of the conductive foil circuit pattern 3 is set to 0.
A temperature cycle test was conducted by changing to 1, 0.3, 0.6, 1, 2 mm. Although the test was performed up to 1000 cycles, no cracks were generated in the ceramic substrate in any of the modules, and the modules operated normally.
【００２１】（実施例６）図６に本実施例の導電箔回路
パターン３の一部を示す。図６（ｂ）は平面図、図６
（ａ）は図６（ｂ）のＢ−Ｂでの断面図である。接合材
２には、銀ろうを用いている。また導電箔回路パターン
３のコーナー部の下には、銀ろうとは異なる材質の接合
材として、樹脂１１を用いた。樹脂１１としては、シリ
コーン系樹脂を用いた。用いる樹脂は、１５０℃以上の
耐熱性を備えていればシリコーン樹脂以外の樹脂でも良
い。樹脂１１は、回路パターンの端縁の内側から存在
し、端縁からはみ出して存在している。本実施例のモジ
ュールについて温度サイクル試験を行って結果、１００
０サイクルでもセラミックス基板にクラックは生じずモ
ジユールは正常に動作した。(Embodiment 6) FIG. 6 shows a part of a conductive foil circuit pattern 3 of this embodiment. 6 (b) is a plan view, FIG.
FIG. 6A is a sectional view taken along line BB in FIG. Silver solder is used for the bonding material 2. Further, under the corner portion of the conductive foil circuit pattern 3, resin 11 was used as a bonding material made of a material different from silver solder. A silicone-based resin was used as the resin 11. The resin used may be a resin other than the silicone resin as long as it has a heat resistance of 150 ° C. or higher. The resin 11 is present from the inside of the edge of the circuit pattern and is present outside the edge. As a result of performing a temperature cycle test on the module of this example, 100
Even at 0 cycles, the ceramic substrate did not crack and the module operated normally.
【００２２】（実施例７）図７は、本実施例の導電箔回
路パターン３の一部である。導電箔回路パターン３に大
電流を流すためには、該回路パターンの面積をできるだ
け広くとることが好ましい。このため、本実施例では、
導電箔回路パターンの直線部分では、接合材２の端部ま
で該回路パターンを広げ、銀ろうとは異なる材質の接合
材として、樹脂１１を導電箔回路パターンのコーナー部
を用いた。(Embodiment 7) FIG. 7 shows a part of a conductive foil circuit pattern 3 of this embodiment. In order to pass a large current through the conductive foil circuit pattern 3, it is preferable to make the area of the circuit pattern as large as possible. For this reason, in this embodiment,
In the straight line portion of the conductive foil circuit pattern, the circuit pattern was spread to the end of the bonding material 2, and the resin 11 was used as a corner material of the conductive foil circuit pattern as a bonding material made of a material different from silver solder.
【００２３】また、図７に示すように、導電箔回路パタ
ーン端部下の内側１７では、必ずしも全面に樹脂１１が
存在する必要はなく、導電箔回路パターン端部に沿って
存在していれば良い。また、樹脂１１は、導電箔回路パ
ターン端面に包むように存在し、該回路パターンの上に
存在していても良い。本実施例のモジュールを用い温度
サイクル試験を行った結果、１０００サイクルでもセラ
ミックス基板にクラックは生じずモジュールは正常に動
作した。Further, as shown in FIG. 7, the resin 11 does not necessarily need to be present on the entire surface of the inner side 17 under the end portion of the conductive foil circuit pattern, but may be present along the end portion of the conductive foil circuit pattern. . Further, the resin 11 may be present so as to be wrapped around the end face of the conductive foil circuit pattern, and may be present on the circuit pattern. As a result of performing a temperature cycle test using the module of this example, no crack was generated in the ceramic substrate even after 1000 cycles, and the module operated normally.
【００２４】（実施例８）本実施例では、接合材２の銀
ろうの厚さを変えたモジュールを作製した。モジュール
の作製方法は、実施例２と同様である。導電箔回路パタ
ーン３の銅箔の厚さは０.３mm 一定とし、導電箔回路パ
ターン端部１４からの接合材端部のはみ出し部１６の長
さは０.１mm一定とした。接合材２の銀ろうの厚さを０.
０１，0.03，０.０５，０.１，０.２mm と変えて、温度
サイクル試験を行った。銀ろうの厚さが０.２mm のモジ
ュールでは１０００サイクル以下でセラミックス基板に
クラックが生じた。一方、銀ろうの厚さ０.１mm 以下の
モジュールでは、１０００サイクルでもセラミックス基
板にクラックは発生せずモジュールは正常に動作した。(Embodiment 8) In this embodiment, modules in which the thickness of the silver solder of the bonding material 2 was changed were produced. The manufacturing method of the module is the same as that of the second embodiment. The thickness of the copper foil of the conductive foil circuit pattern 3 was constant at 0.3 mm, and the length of the protruding portion 16 from the conductive foil circuit pattern end 14 to the end of the bonding material was constant at 0.1 mm. The thickness of the silver solder of the bonding material 2 is set to 0.
The temperature cycle test was conducted by changing the values to 01, 0.03, 0.05, 0.1 and 0.2 mm. With a module having a silver solder thickness of 0.2 mm, cracks occurred in the ceramic substrate after 1000 cycles or less. On the other hand, in a module having a silver solder thickness of 0.1 mm or less, cracks did not occur in the ceramic substrate even after 1000 cycles, and the module operated normally.
【００２５】（実施例９）図８（ｂ）に本実施例に用い
た導電箔回路パターン３が付いた絶縁性基板１の一部の
平面図を示す。図８（ａ）は図８（ｂ）のＤ−Ｄ断面図
を示す。導電箔回路パターン２上に電極端子１２が端子
接合材１３により接合されている。この電極端子１２の
接合部周辺において、導電箔回路パターン３の接合材２
が図８(ｂ)に示すようにはみ出ている。電極端子１２
は、銅板を折り曲げたものを用い、端子接合材１３は半
田を用いた。モジュールに温度サイクルがかかると、電
極端子１２の熱膨脹により、電極端子下の導電箔回路パ
ターン３を通じてセラミックス基板に応力が発生する。
この場合、電極端子１２周辺の導電箔回路パターンの面
積が小さいと、導電箔回路パターン端部においてセラミ
ックス基板に大きな応力が発生する。接合材２の幅を図
８（ｂ）に示すように導電箔回路パターン３より広くす
ることによって、セラミックス基板に生じる応力を低減
できる。本実施例においては、図８（ｂ）に示すよう
に、電極端子１２周辺に導電箔回路パターン３から接合
材２が最大で０.２mm はみ出した基板を作製し、この基
板に電極端子１２を接合し、モジュールを組み立てた。
このモジュールを用いて、温度サイクル試験を行った結
果、１０００サイクル後も、セラミックス基板にクラッ
クは生じず、モジュールは正常に動作した。(Embodiment 9) FIG. 8B shows a plan view of a part of the insulating substrate 1 having the conductive foil circuit pattern 3 used in this embodiment. FIG. 8A is a sectional view taken along line D-D of FIG. 8B. The electrode terminals 12 are bonded onto the conductive foil circuit pattern 2 with a terminal bonding material 13. Around the joint of the electrode terminal 12, the joint material 2 of the conductive foil circuit pattern 3 is formed.
Is protruding as shown in FIG. 8 (b). Electrode terminal 12
Was a bent copper plate, and the terminal bonding material 13 was solder. When the module is subjected to a temperature cycle, thermal expansion of the electrode terminals 12 causes stress on the ceramic substrate through the conductive foil circuit pattern 3 below the electrode terminals.
In this case, if the area of the conductive foil circuit pattern around the electrode terminal 12 is small, a large stress is generated in the ceramic substrate at the end of the conductive foil circuit pattern. By making the width of the bonding material 2 wider than that of the conductive foil circuit pattern 3 as shown in FIG. 8B, the stress generated in the ceramic substrate can be reduced. In this embodiment, as shown in FIG. 8 (b), a substrate was prepared in which the bonding material 2 protruded from the conductive foil circuit pattern 3 by 0.2 mm at the maximum around the electrode terminal 12, and the electrode terminal 12 was formed on this substrate. Joined and assembled the module.
As a result of performing a temperature cycle test using this module, the ceramic substrate did not crack even after 1000 cycles, and the module operated normally.
【００２６】一方、比較のために、導電箔回路パターン
３端部から接合材がはみ出していない基板を作製した。
電極端子１２をこの基板に接合し、組み立てたモジュー
ルの温度サイクル試験を行った。その結果、１０００サ
イクル後に、モジュールは正常に動作しなかった。この
正常に動作しなかったモジュールを分解してみると、電
極端子１２周辺部のセラミックス基板にクラックが入っ
ていた。On the other hand, for comparison, a substrate was prepared in which the bonding material did not protrude from the end of the conductive foil circuit pattern 3.
The electrode terminal 12 was joined to this substrate, and the assembled module was subjected to a temperature cycle test. As a result, the module did not operate normally after 1000 cycles. When the module that did not operate normally was disassembled, cracks were found in the ceramic substrate around the electrode terminals 12.
【００２７】（実施例１０）図９（ｂ）に本実施例に用
いた導電箔回路パターン３が付いた絶縁性基板１の一部
の平面図示す。図９（ａ）は図９（ｂ）のＥ−Ｅ断面図
を示す。導電箔回路パターン３上に電極端子１２が端子
接合材１３を用いて接合されている。本実施例において
は、隣接する導電箔回路パターン（図示せず）との絶縁
距離を確保し、かつ、できるだけ導電箔回路パターン３
同士を近付けるために、この電極端子１２の接合部周辺
に樹脂１１を用いた。本実施例のモジュールを温度サイ
クル試験を行った結果、１０００サイクル後も、モジュ
ールは正常に動作した。(Embodiment 10) FIG. 9B shows a plan view of a part of the insulating substrate 1 with the conductive foil circuit pattern 3 used in this embodiment. FIG. 9A shows a sectional view taken along line EE of FIG. 9B. The electrode terminals 12 are bonded onto the conductive foil circuit pattern 3 using a terminal bonding material 13. In this embodiment, an insulating distance from an adjacent conductive foil circuit pattern (not shown) is secured, and the conductive foil circuit pattern 3 is formed as much as possible.
In order to bring them closer to each other, the resin 11 was used around the joint of the electrode terminal 12. As a result of performing a temperature cycle test on the module of this example, the module operated normally even after 1000 cycles.
【００２８】（実施例１１）図１０（ａ）及び（ｂ）
は、本発明の実施例である回路基板の端部の部分断面図
である。(Embodiment 11) FIGS. 10A and 10B.
FIG. 3 is a partial cross-sectional view of an end portion of a circuit board that is an embodiment of the present invention.
【００２９】図１０（ａ）においては、銅箔３の厚さが
端部において階段上に薄くなっている。また、図１０
（ｂ）においては、銅箔３の端部にテーパを付けて、銅
箔の厚さを徐々に薄くしている。各図における銅箔はセ
ラミック基板の表面に接合材２により接合され、かつ接
合材２の端部が銅箔３の端部よりも外側に位置する。In FIG. 10A, the thickness of the copper foil 3 is thin on the stairs at the end. FIG.
In (b), the end of the copper foil 3 is tapered to gradually reduce the thickness of the copper foil. The copper foil in each figure is joined to the surface of the ceramic substrate by the joining material 2, and the end of the joining material 2 is located outside the end of the copper foil 3.
【００３０】本実施例によれば、セラミック基板１の接
合材２の端部下に位置する部分における熱応力が低減さ
れる。さらに、セラミック基板１の銅箔３の端部下に位
置する部分の熱応力も低減される。According to this embodiment, the thermal stress in the portion of the ceramic substrate 1 located below the end of the bonding material 2 is reduced. Further, the thermal stress of the portion of the ceramic substrate 1 located below the end of the copper foil 3 is also reduced.
【００３１】なお、銅箔３の端縁と接合材２の端縁の位
置は一致していてもよい。The positions of the edge of the copper foil 3 and the edge of the bonding material 2 may be the same.
【００３２】[0032]
【発明の効果】本発明によれば、回路パターン端部から
絶縁性基板に応じる応力集中を緩和できるため、繰り返
し熱負荷に対する信頼性が向上した半導体装置を提供す
ることができる。According to the present invention, the stress concentration due to the insulating substrate can be relaxed from the end of the circuit pattern, so that it is possible to provide a semiconductor device with improved reliability against repeated thermal loads.
【図１】本発明の実施例によるモジュールの概略断面
図。FIG. 1 is a schematic sectional view of a module according to an embodiment of the present invention.
【図２】本発明の実施例の平面図（ａ）と断面図
（ｂ）。FIG. 2 is a plan view (a) and a sectional view (b) of an embodiment of the present invention.
【図３】本発明の実施例の平面図。FIG. 3 is a plan view of an embodiment of the present invention.
【図４】従来のモジュールの概略断面図。FIG. 4 is a schematic sectional view of a conventional module.
【図５】導電箔回路パターン端部からの接合材端部はみ
出し部の長さとクラックが発生した温度サイクル数の関
係を示す図。FIG. 5 is a diagram showing a relationship between a length of a bonding material end portion protruding from a conductive foil circuit pattern end portion and the number of temperature cycles in which a crack is generated.
【図６】本発明の実施例の断面図（ａ）と平面図
（ｂ）。FIG. 6 is a sectional view (a) and a plan view (b) of an embodiment of the present invention.
【図７】本発明の実施例の断面図（ａ）と平面図
（ｂ）。FIG. 7 is a sectional view (a) and a plan view (b) of an embodiment of the present invention.
【図８】本発明の実施例の断面図（ａ）と平面図
（ｂ）。FIG. 8 is a sectional view (a) and a plan view (b) of an embodiment of the present invention.
【図９】本発明の実施例の断面図（ａ）と平面図
（ｂ）。FIG. 9 is a sectional view (a) and a plan view (b) of an embodiment of the present invention.
【図１０】本発明の実施例の部分断面図（ａ）及び
（ｂ）。FIG. 10 is a partial sectional view (a) and (b) of an embodiment of the present invention.
１…絶縁性基板、２…接合材、３…導電箔回路パター
ン、４…半導体素子、５…ワイヤ、６，７…半田、８…
金属ベース基板、９…グリース、１０…冷却体、１１…
樹脂、１２…電極端子、１３…端子接合材、１４…導電
箔回路パターン端部、１５…接合材の端部、１６…接合
材端部のはみ出し部、１７…導電箔回路パターン端部下
の内側。1 ... Insulating substrate, 2 ... Bonding material, 3 ... Conductive foil circuit pattern, 4 ... Semiconductor element, 5 ... Wire, 6,7 ... Solder, 8 ...
Metal base substrate, 9 ... Grease, 10 ... Cooling body, 11 ...
Resin, 12 ... Electrode terminal, 13 ... Terminal bonding material, 14 ... Conductive foil circuit pattern end portion, 15 ... Bonding material end portion, 16 ... Bonding material end portion protrusion, 17 ... Inside of conductive foil circuit pattern end portion .
───────────────────────────────────────────────────── フロントページの続き (72)発明者 清水 英雄 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 岡田 亘右 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 小池 義彦 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 (72)発明者 山田 一二 茨城県日立市大みか町七丁目１番１号 株 式会社日立製作所日立研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Hideo Shimizu, Inventor Hideo Shimizu, 1-1-1, Omika-cho, Hitachi-shi, Ibaraki Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Wataru Okada, 7-chome, Omika-cho, Hitachi-shi, Ibaraki No. 1-1 Hitachi Ltd., Hitachi Research Laboratory (72) Inventor Yoshihiko Koike Seven-1-1, Omika-cho, Hitachi City, Ibaraki Prefecture Hitachi Ltd. Hitachi Research Laboratory (72) Inventor Kazu Yamada Ibaraki Prefecture Hitachi 7-1 Mika-cho, Oita-shi, Hitachi, Ltd. Hitachi Research Laboratory
Claims (22)
導電箔を該接合材を介して該絶縁性基板に接合した回路
基板において、前記接合材の端部が前記導電箔端部より
外側に存在していることを特徴とする回路基板。1. A circuit board in which an insulating substrate, a bonding material, and a conductive foil are laminated and the conductive foil is bonded to the insulating substrate via the bonding material, and the end of the bonding material is the conductive foil end. A circuit board that is present outside the part.
合材端部のはみだし部の長さが、前記接合材の厚さより
長いことを特徴とする回路基板。2. The circuit board according to claim 1, wherein the length of the protruding portion at the end of the bonding material is longer than the thickness of the bonding material.
合材端部のはみ出し部の厚さが0.1mm以下であることを
特徴とする回路基板。3. The circuit board according to claim 1, wherein the thickness of the protruding portion at the end of the bonding material is 0.1 mm or less.
導電箔を該接合材を介して該絶縁性基板に接合した回路
基板において、前記接合材の面積が前記導電箔の面積よ
り広いことを特徴とする回路基板。4. A circuit board in which an insulating substrate, a bonding material and a conductive foil are laminated and the conductive foil is bonded to the insulating substrate via the bonding material, and the area of the bonding material is the area of the conductive foil. A circuit board that is wider.
合材端部のはみだし部の長さが、前記接合材の厚さより
長いことを特徴とする回路基板。5. The circuit board according to claim 4, wherein the length of the protruding portion at the end of the bonding material is longer than the thickness of the bonding material.
合材端部のはみ出し部の厚さが0.1mm以下であることを
特徴とする回路基板。6. The circuit board according to claim 4, wherein the thickness of the protruding portion at the end of the bonding material is 0.1 mm or less.
導電箔を該接合材を介して該絶縁性基板に接合した回路
基板において、前記接合材の接合パターンのコーナー部
の端部が前記導電箔の回路パターンのコーナー部の端部
より外側に存在していることを特徴とする回路基板。7. A circuit board in which an insulating substrate, a bonding material, and a conductive foil are laminated, and the conductive foil is bonded to the insulating substrate via the bonding material, and an end of a corner portion of a bonding pattern of the bonding material. The circuit board is characterized in that the portion exists outside the end portion of the corner portion of the circuit pattern of the conductive foil.
合材パターンのコーナー部の端部の最大はみだし部の長
さが、前記接合材の厚さより長いことを特徴とする回路
基板。8. The circuit board according to claim 7, wherein the maximum protruding portion at the end of the corner portion of the bonding material pattern is longer than the thickness of the bonding material.
合材パターンのコーナー部の端部の最大はみだし部の厚
さが０.１mm 以下であることを特徴とする回路基板。9. The circuit board according to claim 7, wherein the thickness of the maximum protruding portion at the end of the corner portion of the bonding material pattern is 0.1 mm or less.
導電箔が複数の種類の接合材で前記絶縁性基板に接合さ
れていることを特徴とする回路基板。10. The circuit board according to claim 1, wherein the conductive foil is bonded to the insulating board with a plurality of kinds of bonding materials.
記接合材が前記導電箔上にもあることを特徴とする回路
基板。11. The circuit board according to claim 10, wherein the bonding material is also on the conductive foil.
と導電箔と半導体素子を積層し該導電箔を該接合材を介
して該絶縁性基板に接合した半導体装置において、前記
接合材の端部が前記導電箔端部より外側に存在している
ことを特徴とする半導体装置。12. A semiconductor device in which an insulating substrate, a bonding material, a conductive foil, and a semiconductor element are laminated on a metal base substrate, and the conductive foil is bonded to the insulating substrate via the bonding material. A semiconductor device, wherein an end portion is present outside the end portion of the conductive foil.
前記接合材端部のはみだし部の長さが、前記接合材の厚
さより長いことを特徴とする半導体装置。13. The semiconductor device according to claim 12,
A semiconductor device, wherein a length of a protruding portion at an end portion of the bonding material is longer than a thickness of the bonding material.
前記接合材端部のはみ出し部の厚さが０.１mm 以下であ
ることを特徴とする半導体装置。14. The semiconductor device according to claim 12,
A semiconductor device, wherein the thickness of the protruding portion at the end of the bonding material is 0.1 mm or less.
と導電箔と半導体素子を積層し該導電箔を該接合材を介
して該絶縁性基板に接合した半導体装置において、前記
接合材の面積が前記導電箔の面積より広いことを特徴と
する半導体装置。15. A semiconductor device in which an insulating substrate, a bonding material, a conductive foil, and a semiconductor element are laminated on a metal base substrate and the conductive foil is bonded to the insulating substrate via the bonding material. A semiconductor device having an area larger than that of the conductive foil.
前記接合材端部のはみ出し部の長さが、前記接合材の厚
さより長いことを特徴とする半導体装置。16. The semiconductor device according to claim 15,
The semiconductor device is characterized in that the length of the protruding portion at the end of the bonding material is longer than the thickness of the bonding material.
前記接合材端部のはみ出し部の厚さが０.１mm 以下であ
ることを特徴とする半導体装置。17. The semiconductor device according to claim 15,
A semiconductor device, wherein the thickness of the protruding portion at the end of the bonding material is 0.1 mm or less.
と導電箔と半導体素子を積層し該導電箔を該接合材を介
して該絶縁性基板に接合した半導体装置において、前記
接合材の接合パターンのコーナー部の端部が前記導電箔
の回路パターンのコーナー部の端部より外側に存在して
いることを特徴とする半導体装置。18. A semiconductor device in which an insulating substrate, a bonding material, a conductive foil, and a semiconductor element are laminated on a metal base substrate, and the conductive foil is bonded to the insulating substrate via the bonding material. A semiconductor device, wherein an end portion of a corner portion of the bonding pattern exists outside an end portion of a corner portion of the circuit pattern of the conductive foil.
前記接合材パターンのコーナー部の端部の最大はみだし
部の長さが、前記接合材の厚さより長いことを特徴とす
る半導体装置。19. The semiconductor device according to claim 18,
A semiconductor device, wherein the length of the maximum protruding portion at the end of the corner portion of the bonding material pattern is longer than the thickness of the bonding material.
前記接合材パターンのコーナー部の端部の最大はみだし
部の厚さが０.１mm 以下であることを特徴とする半導体
装置。20. The semiconductor device according to claim 18,
A semiconductor device, wherein the thickness of the maximum protruding portion at the end of the corner portion of the bonding material pattern is 0.1 mm or less.
前記導電箔が複数の種類の接合材で前記絶縁性基板に接
合されていることを特徴とする半導体装置。21. The semiconductor device according to claim 12,
A semiconductor device, wherein the conductive foil is bonded to the insulating substrate with a plurality of kinds of bonding materials.
前記接合材が前記導電箔上にもあることを特徴とする半
導体装置。22. The semiconductor device according to claim 21,
A semiconductor device, wherein the bonding material is also on the conductive foil.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9024733A JPH09275165A (en) | 1996-02-07 | 1997-02-07 | Circuit board and semiconductor device using the same |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8-20897 | 1996-02-07 | ||
| JP2089796 | 1996-02-07 | ||
| JP9024733A JPH09275165A (en) | 1996-02-07 | 1997-02-07 | Circuit board and semiconductor device using the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH09275165A true JPH09275165A (en) | 1997-10-21 |
Family
ID=26357898
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9024733A Pending JPH09275165A (en) | 1996-02-07 | 1997-02-07 | Circuit board and semiconductor device using the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH09275165A (en) |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000049257A (en) * | 1998-07-30 | 2000-02-18 | Kyocera Corp | Head radiation circuit board |
| JP2001168250A (en) * | 1999-12-10 | 2001-06-22 | Sumitomo Electric Ind Ltd | Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate |
| US6261703B1 (en) | 1997-05-26 | 2001-07-17 | Sumitomo Electric Industries, Ltd. | Copper circuit junction substrate and method of producing the same |
| JP2003100965A (en) * | 2001-09-20 | 2003-04-04 | Denki Kagaku Kogyo Kk | Reliability evaluating method of circuit board and circuit board |
| JP2003112980A (en) * | 2001-09-28 | 2003-04-18 | Dowa Mining Co Ltd | Metal-ceramic joined body |
| JP2004014589A (en) * | 2002-06-04 | 2004-01-15 | Dowa Mining Co Ltd | Metal-ceramic junction body and its manufacturing method |
| EP0921565A3 (en) * | 1997-12-08 | 2005-07-27 | Kabushiki Kaisha Toshiba | Package for semiconductor power device and method for assembling the same |
| JP2006286897A (en) * | 2005-03-31 | 2006-10-19 | Dowa Mining Co Ltd | Metal-ceramic bonding substrate |
| JP2006282417A (en) * | 2005-03-31 | 2006-10-19 | Dowa Mining Co Ltd | Metal/ceramic joined substrate |
| JP2006351988A (en) * | 2005-06-20 | 2006-12-28 | Denki Kagaku Kogyo Kk | Ceramic substrate, ceramic circuit board and power control component using same |
| JP2020161842A (en) * | 2015-09-28 | 2020-10-01 | 株式会社東芝 | Circuit substrate and semiconductor device |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02196074A (en) * | 1989-01-25 | 1990-08-02 | Dowa Mining Co Ltd | Production of ceramics-metal joined body |
| JPH03261669A (en) * | 1990-03-13 | 1991-11-21 | Dowa Mining Co Ltd | Bonded product between ceramics and metal and production thereof |
| JPH0477369A (en) * | 1990-07-16 | 1992-03-11 | Showa Denko Kk | Production of metal-ceramic laminated substrate |
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
| JPH05347469A (en) * | 1992-06-12 | 1993-12-27 | Toshiba Corp | Ceramic circuit board |
| JPH0793326B2 (en) * | 1987-06-11 | 1995-10-09 | 三菱電機株式会社 | Semiconductor device |
| JPH104156A (en) * | 1996-06-14 | 1998-01-06 | Mitsubishi Electric Corp | Insulating substrate for semiconductor device and the semiconductor device |
-
1997
- 1997-02-07 JP JP9024733A patent/JPH09275165A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0793326B2 (en) * | 1987-06-11 | 1995-10-09 | 三菱電機株式会社 | Semiconductor device |
| JPH02196074A (en) * | 1989-01-25 | 1990-08-02 | Dowa Mining Co Ltd | Production of ceramics-metal joined body |
| JPH03261669A (en) * | 1990-03-13 | 1991-11-21 | Dowa Mining Co Ltd | Bonded product between ceramics and metal and production thereof |
| JPH0477369A (en) * | 1990-07-16 | 1992-03-11 | Showa Denko Kk | Production of metal-ceramic laminated substrate |
| JPH0590444A (en) * | 1991-09-26 | 1993-04-09 | Toshiba Corp | Ceramic circuit board |
| JPH05347469A (en) * | 1992-06-12 | 1993-12-27 | Toshiba Corp | Ceramic circuit board |
| JPH104156A (en) * | 1996-06-14 | 1998-01-06 | Mitsubishi Electric Corp | Insulating substrate for semiconductor device and the semiconductor device |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6261703B1 (en) | 1997-05-26 | 2001-07-17 | Sumitomo Electric Industries, Ltd. | Copper circuit junction substrate and method of producing the same |
| EP0921565A3 (en) * | 1997-12-08 | 2005-07-27 | Kabushiki Kaisha Toshiba | Package for semiconductor power device and method for assembling the same |
| JP2000049257A (en) * | 1998-07-30 | 2000-02-18 | Kyocera Corp | Head radiation circuit board |
| JP2001168250A (en) * | 1999-12-10 | 2001-06-22 | Sumitomo Electric Ind Ltd | Insulating substrate for semiconductor device, semiconductor device using that and manufacturing method of substrate |
| JP2003100965A (en) * | 2001-09-20 | 2003-04-04 | Denki Kagaku Kogyo Kk | Reliability evaluating method of circuit board and circuit board |
| JP2003112980A (en) * | 2001-09-28 | 2003-04-18 | Dowa Mining Co Ltd | Metal-ceramic joined body |
| JP2004014589A (en) * | 2002-06-04 | 2004-01-15 | Dowa Mining Co Ltd | Metal-ceramic junction body and its manufacturing method |
| JP2006286897A (en) * | 2005-03-31 | 2006-10-19 | Dowa Mining Co Ltd | Metal-ceramic bonding substrate |
| JP2006282417A (en) * | 2005-03-31 | 2006-10-19 | Dowa Mining Co Ltd | Metal/ceramic joined substrate |
| JP4498966B2 (en) * | 2005-03-31 | 2010-07-07 | Ｄｏｗａホールディングス株式会社 | Metal-ceramic bonding substrate |
| JP2006351988A (en) * | 2005-06-20 | 2006-12-28 | Denki Kagaku Kogyo Kk | Ceramic substrate, ceramic circuit board and power control component using same |
| JP2020161842A (en) * | 2015-09-28 | 2020-10-01 | 株式会社東芝 | Circuit substrate and semiconductor device |
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