JP2003168694A - Semiconductor package - Google Patents

Semiconductor package

Info

Publication number
JP2003168694A
JP2003168694A JP2001369080A JP2001369080A JP2003168694A JP 2003168694 A JP2003168694 A JP 2003168694A JP 2001369080 A JP2001369080 A JP 2001369080A JP 2001369080 A JP2001369080 A JP 2001369080A JP 2003168694 A JP2003168694 A JP 2003168694A
Authority
JP
Japan
Prior art keywords
semiconductor chip
semiconductor
bonding paste
die bonding
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2001369080A
Other languages
Japanese (ja)
Inventor
Megumi Kosuda
恵 小須田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP2001369080A priority Critical patent/JP2003168694A/en
Priority to KR1020020045723A priority patent/KR20030047688A/en
Publication of JP2003168694A publication Critical patent/JP2003168694A/en
Pending legal-status Critical Current

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Classifications

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    • H01—ELECTRIC ELEMENTS
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a semiconductor package in which sufficient bonding strength is attained while preventing a die bond material from projecting. <P>SOLUTION: A plurality of recesses 11a are formed in one side of a semiconductor chip 11 and a die pad part 14 for mounting the semiconductor chip fixedly is provided in a package 12. The die pad part 14 has a part 14a for mounting the semiconductor chip, and a part 14c on the periphery of the mounting part provided with a level difference 14b wherein the semiconductor chip 11 is bonded fixedly to the mounting part 14a on the recess 11a side. Furthermore, a groove part 141 may be formed at the mounting part 14a. <P>COPYRIGHT: (C)2003,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【０００１】[0001]

【発明の属する技術分野】この発明は内部に半導体チッ
プを接着固定して収納する半導体パッケージに係り、特
に半導体チップの接着面やダイパッド部に余剰な接着剤
（ダイボンディングペースト）の逃げ場となる凹部や段
差を設けた半導体パッケージに関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor package in which a semiconductor chip is adhered and fixed and accommodated therein, and in particular, a recess serving as an escape area for an excessive adhesive agent (die bonding paste) on a bonding surface of the semiconductor chip or a die pad portion. And a semiconductor package provided with a step.

【０００２】[0002]

【従来の技術】近年の半導体チップの集積度の向上に伴
って、半導体チップの入出力ピンが増加しており、この
結果、半導体チップとパッケージとを繋ぐ金線も微細化
（ファインピッチ化）される傾向にある。このため、半
導体チップの表面に異物が存在すると、半導体パッケー
ジの生産性が低下するばかりでなく、その品質も低下し
てしまう。2. Description of the Related Art The number of input / output pins of a semiconductor chip has increased with the recent increase in the degree of integration of the semiconductor chip. As a result, the gold wire connecting the semiconductor chip and the package has also been miniaturized (fine pitch). Tend to be. Therefore, the presence of foreign matter on the surface of the semiconductor chip not only lowers the productivity of the semiconductor package, but also deteriorates the quality thereof.

【０００３】半導体パッケージでは、内部のダイパッド
部に半導体チップが接着固定されている。例えば、半導
体チップを銀ペーストなどのダイボンディングペースト
で接着固定する際、パッケージ内のダイパッド部にダイ
ボンディングペーストを塗布した後、所定の荷重を加え
つつ、半導体チップをダイパッド部に接着固定してい
る。In a semiconductor package, a semiconductor chip is adhesively fixed to an internal die pad portion. For example, when a semiconductor chip is bonded and fixed with a die bonding paste such as silver paste, the semiconductor chip is bonded and fixed to the die pad while applying a predetermined load after applying the die bonding paste to the die pad inside the package. .

【０００４】ところが、上述した半導体チップの押圧工
程時に、ダイボンディングペーストが半導体チップの表
面などにはみ出してしまうことがあった。However, the die bonding paste sometimes squeezes out on the surface of the semiconductor chip during the above-mentioned semiconductor chip pressing step.

【０００５】また、最近では鉛を含むはんだ材を使用せ
ず、鉛を代替する融点の高い金属を含むはんだ材を使用
する傾向にある。この結果、電子部品のマウント時にお
けるはんだリフロー温度も高温化している。Recently, there is a tendency to use a solder material containing a metal having a high melting point, which replaces lead, instead of using a solder material containing lead. As a result, the solder reflow temperature at the time of mounting the electronic component also becomes high.

【０００６】従って、半導体パッケージを電子基板にマ
ウントする際、はんだリフローにおいて熱ストレスがか
かるため、半導体チップとダイパッド部との接着も該熱
ストレスに耐え得る強度が必要とされる。このため、十
分な接着強度が得られる程度に、ダイボンディングペー
ストの使用量も決定されている。従って、上記はみ出し
を抑制するために、ダイボンディングペーストの使用量
を減らすことはできない。Therefore, when a semiconductor package is mounted on an electronic substrate, thermal stress is applied during solder reflow, and therefore, the bonding between the semiconductor chip and the die pad portion is required to be strong enough to withstand the thermal stress. For this reason, the amount of die bonding paste used is determined so that a sufficient adhesive strength can be obtained. Therefore, the amount of die bonding paste used cannot be reduced in order to suppress the protrusion.

【０００７】上記不具合を解消する半導体パッケージと
して、例えば特開平１０−１６３４０７号公報に開示さ
れるものがある（以下、従来例と呼ぶ）。この従来例で
は、半導体チップが接着固定されるダイパッド部に、半
導体チップが搭載される搭載面である上段部と、搭載面
の周辺に段差を設けた下段部とを設け、この下段部に凹
凸を形成している。このようなダイパッド部を用いるこ
とによって、上記段差によってダイボンディングペース
トの拡がりを視認することができ、凹凸形状によってダ
イボンディングペーストのはみ出しを抑制することがで
きる。As a semiconductor package for solving the above-mentioned problems, for example, there is one disclosed in Japanese Patent Laid-Open No. 10-163407 (hereinafter referred to as a conventional example). In this conventional example, the die pad portion to which the semiconductor chip is adhesively fixed is provided with an upper step portion which is a mounting surface on which the semiconductor chip is mounted, and a lower step portion having a step around the mounting surface, and the lower step portion has unevenness. Is formed. By using such a die pad portion, the spread of the die bonding paste can be visually recognized by the step, and the protrusion of the die bonding paste can be suppressed by the uneven shape.

【０００８】[0008]

【発明が解決しようとする課題】従来の半導体パッケー
ジは以上のように構成されているので、下段部における
ダイボンディングペースト（導電性接着剤）のはみ出し
を抑制することはできるものの、上段部と半導体チップ
との接着強度を向上させるには限界があるという課題が
あった。Since the conventional semiconductor package is configured as described above, it is possible to suppress the protrusion of the die bonding paste (conductive adhesive) in the lower part, but to prevent the die bonding paste (conductive adhesive) from protruding in the upper part and the semiconductor. There is a problem that there is a limit to improving the adhesive strength with the chip.

【０００９】上記課題を具体的に説明すると、従来の半
導体パッケージでは、上段部と半導体チップとの接着強
度を向上させる構成を有していないことから、接着強度
を向上させるためにはダイボンディングペーストの使用
量を増加させる必要がある。これにより、下段部におけ
るダイボンディングペーストのはみ出しを抑制すること
はできるものの、上段部ではダイボンディングペースト
のはみ出しを抑制することができず、半導体チップの側
面及び又は表面にはみ出すことがあった。この結果、例
えば金線の配線に支障をきたし、ひいては半導体パッケ
ージの品質が低下するばかりでなく、生産性も低下して
しまうことになる。The above problem will be described in detail. Since the conventional semiconductor package does not have a structure for improving the adhesive strength between the upper portion and the semiconductor chip, in order to improve the adhesive strength, the die bonding paste is used. Need to increase usage. As a result, the protrusion of the die bonding paste in the lower portion can be suppressed, but the protrusion of the die bonding paste in the upper portion cannot be suppressed, and the protrusion and the side surface of the semiconductor chip may sometimes protrude. As a result, the wiring of, for example, a gold wire is hindered, which eventually deteriorates not only the quality of the semiconductor package but also the productivity.

【００１０】また、上述のようなはみ出しを防止するた
め、ダイボンディングペーストの量を少なくすると、今
度は十分な接着強度が得られなくなってしまう。Further, if the amount of die bonding paste is reduced to prevent the above-mentioned protrusion, sufficient adhesive strength cannot be obtained this time.

【００１１】いずれにしても、従来の半導体パッケージ
では、ダイボンディングペーストの量を多くすると、ダ
イボンディングペーストが半導体チップの側面及び／又
は表面にはみ出すという不具合が生じる。一方、ダイボ
ンディングペーストの量を少なくすると、十分な接着強
度が得られないというものであった。In any case, in the conventional semiconductor package, when the amount of the die bonding paste is increased, the problem that the die bonding paste sticks out to the side surface and / or the surface of the semiconductor chip occurs. On the other hand, if the amount of die bonding paste is reduced, sufficient adhesive strength cannot be obtained.

【００１２】この発明は上記のような課題を解決するた
めになされたもので、半導体チップとダイパッド部との
接着強度を向上させると共に、ダイボンディングペース
トのはみ出しを抑制することができる半導体パッケージ
を得ることを目的とする。The present invention has been made to solve the above problems, and obtains a semiconductor package capable of improving the adhesive strength between a semiconductor chip and a die pad portion and suppressing the protrusion of the die bonding paste. The purpose is to

【００１３】[0013]

【課題を解決するための手段】この発明に係る半導体パ
ッケージは、半導体チップを収納するパッケージ筐体
と、パッケージ筐体内に設けられ、半導体チップを接着
固定するダイパッド部と、半導体チップの接着面に形成
した凹部とを備えるものである。A semiconductor package according to the present invention includes a package housing for accommodating a semiconductor chip, a die pad portion provided in the package housing for adhering and fixing the semiconductor chip, and an adhesive surface of the semiconductor chip. And the formed recessed part.

【００１４】この発明に係る半導体パッケージは、半導
体チップの接着面に複数の凹部を形成したものである。In the semiconductor package according to the present invention, a plurality of recesses are formed on the bonding surface of the semiconductor chip.

【００１５】この発明に係る半導体パッケージは、ダイ
パッド部が、半導体チップが搭載される搭載部と、該搭
載部の周辺部に段差を設けてなる下段部とを備えるもの
である。In the semiconductor package according to the present invention, the die pad portion includes a mounting portion on which a semiconductor chip is mounted, and a lower step portion provided with a step around the mounting portion.

【００１６】この発明に係る半導体パッケージは、搭載
部の半導体チップ搭載面に溝部を形成したものである。In the semiconductor package according to the present invention, a groove is formed on the semiconductor chip mounting surface of the mounting portion.

【００１７】[0017]

【発明の実施の形態】以下、この発明の実施の一形態を
説明する。 実施の形態１．図１はこの発明の実施の形態１による半
導体パッケージを示す断面図である。この図ではダイボ
ンディングペーストの使用量が多い場合を示している。
図において、１１は半導体チップ、１２はパッケージ
（パッケージ筐体）であり、半導体チップ１１がパッケ
ージ１２内に収納されて半導体パッケージ１３となる。
また、パッケージ１２は、基部１２ａと蓋部１２ｂとを
有している。この基部１２ａの下面には複数の入出力ピ
ン１２ｃが設けられており、中央部にはダイパッド部１
４が形成されている。ダイパッド部１４は、半導体チッ
プ１１が搭載される搭載部１４ａと、この搭載部１４ａ
の周囲に段差１４ｂを設けてなる周囲部（下段部）１４
ｃとを有している。BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below. Embodiment 1. 1 is a sectional view showing a semiconductor package according to a first embodiment of the present invention. This figure shows a case where a large amount of die bonding paste is used.
In the figure, 11 is a semiconductor chip and 12 is a package (package housing). The semiconductor chip 11 is housed in the package 12 to form a semiconductor package 13.
Further, the package 12 has a base portion 12a and a lid portion 12b. A plurality of input / output pins 12c are provided on the lower surface of the base portion 12a, and the die pad portion 1 is provided at the center portion.
4 are formed. The die pad portion 14 includes a mounting portion 14a on which the semiconductor chip 11 is mounted, and the mounting portion 14a.
A peripheral part (lower part) 14 in which a step 14b is provided around the
c and.

【００１８】周囲部１４ｃの外周側には、上方に立ち上
がる段差１４ｄが設けられ、この段差１４ｄを介して周
囲部１４ｃに接続面部１５が連続している。また、接続
面部１５には金線１６が接続される。これによって、金
線１６は入出力ピン１２ｃのいずれかに接続されること
になる。また、半導体チップ１１の接着面には複数の凹
部１１ａが形成されており、図示のように波状の断面を
有している。A step 14d rising upward is provided on the outer peripheral side of the peripheral portion 14c, and the connecting surface portion 15 is continuous with the peripheral portion 14c via the step 14d. Further, the gold wire 16 is connected to the connection surface portion 15. As a result, the gold wire 16 is connected to any of the input / output pins 12c. Further, a plurality of recesses 11a are formed on the bonding surface of the semiconductor chip 11 and have a wavy cross section as shown in the figure.

【００１９】次に概要について説明する。半導体パッケ
ージ１３を製造する際には、搭載部１４ａにダイボンデ
ィングペースト１７が塗布される。その後、半導体チッ
プ１１の接着面、つまり、凹部１１ａを下側に向けて、
所定の荷重で半導体チップ１１を搭載部１４ａに押圧
し、半導体チップ１１を搭載部１４ａに接着固定する。
次に、半導体チップ１１と金線１６を接続するとともに
金線１６を接続面部１５に接続する。そして、基部１２
ａに蓋部１２ｂを被せて固定し、半導体パッケージ１３
とする。Next, an outline will be described. When manufacturing the semiconductor package 13, the die bonding paste 17 is applied to the mounting portion 14a. Then, with the adhesive surface of the semiconductor chip 11, that is, the concave portion 11a facing downward,
The semiconductor chip 11 is pressed against the mounting portion 14a with a predetermined load, and the semiconductor chip 11 is adhesively fixed to the mounting portion 14a.
Next, the semiconductor chip 11 and the gold wire 16 are connected and the gold wire 16 is connected to the connection surface portion 15. And the base 12
The semiconductor package 13 is fixed by covering the lid 12a with the lid 12b.
And

【００２０】図１に示すように、ダイボンディングペー
スト１７の使用量が多い場合、半導体チップ１１の接合
面に形成した凹部１１ａにダイボンディングペースト１
７の余剰分が導かれて、半導体チップ１１の接合面全体
に拡がることになる。つまり、凹部１１ａがあたかもダ
イボンディングペースト１７の案内部として作用するこ
とになる。しかも、搭載部１４ａには段差１４ｂを介し
て周囲部１４ｃが連続しているから、余剰分は段差１４
ｂから周囲部１４ｃに落ちる。この結果、ダイボンディ
ングペースト１７の余剰分が半導体チップ１１の側面及
び／又は表面にはみ出すことがなくなる。As shown in FIG. 1, when the die-bonding paste 17 is used in a large amount, the die-bonding paste 1 is formed in the recess 11a formed in the bonding surface of the semiconductor chip 11.
The surplus of 7 is guided and spreads over the entire bonding surface of the semiconductor chip 11. That is, the recess 11a acts as if it were a guide for the die bonding paste 17. Moreover, since the peripheral portion 14c is continuous to the mounting portion 14a via the step 14b, the surplus portion is the step 14c.
It falls from b to the peripheral part 14c. As a result, the surplus portion of the die bonding paste 17 does not overflow to the side surface and / or the surface of the semiconductor chip 11.

【００２１】また、半導体チップと搭載部１４ａとの接
着強度は、ダイボンディングペースト１７の量ばかりで
なく、接着面積にも依存している。これを踏まえると、
上述したように半導体チップ１１の接合面に凹部１１ａ
を形成することで、ダイボンディングペースト１７との
接着面積が広くなることから、接着強度の向上を図るこ
とができる。The adhesive strength between the semiconductor chip and the mounting portion 14a depends not only on the amount of the die bonding paste 17 but also on the adhesive area. Based on this,
As described above, the concave portion 11a is formed on the bonding surface of the semiconductor chip 11.
By forming the, the bonding area with the die bonding paste 17 is widened, so that the bonding strength can be improved.

【００２２】図２は実施の形態１による半導体パッケー
ジにおいてダイボンディングペーストの使用量が少ない
場合を示す断面図である。上述したように、従来では、
ダイボンディングペーストの使用量が少ない場合、接着
強度を向上させることはできなかった。一方、本発明で
は、半導体チップ１１の接合面に凹部１１ａを形成して
実質的に接合面の面積を増加させている。つまり、ダイ
ボンディングペースト１７の使用量が少なくても、接着
強度を向上させることができる。この結果、ダイボンデ
ィングペースト１７の使用量を低減することもできる。FIG. 2 is a sectional view showing a case where the amount of die bonding paste used is small in the semiconductor package according to the first embodiment. As mentioned above, in the past,
When the amount of die bonding paste used was small, the adhesive strength could not be improved. On the other hand, in the present invention, the concave portion 11a is formed in the joint surface of the semiconductor chip 11 to substantially increase the area of the joint surface. That is, the adhesive strength can be improved even if the amount of the die bonding paste 17 used is small. As a result, the amount of die bonding paste 17 used can be reduced.

【００２３】以上のように、この実施の形態１によれ
ば、ダイパッド部１４が搭載部１４ａと、この搭載部１
４ａの周囲に段差１４ｂを設けてなる周囲部１４ｃを有
し、半導体チップ１１の接合面に複数の凹部１１ａを形
成したので、ダイボンディングペースト１７のはみ出し
を防止することができるばかりでなく、接着強度を向上
させることができる。As described above, according to the first embodiment, the die pad portion 14 includes the mounting portion 14a and the mounting portion 1a.
4a has a peripheral portion 14c provided with a step 14b and a plurality of recesses 11a are formed on the bonding surface of the semiconductor chip 11, so that not only can the die bonding paste 17 be prevented from protruding, but also the bonding can be prevented. The strength can be improved.

【００２４】実施の形態２．図３はこの発明の実施の形
態２による半導体パッケージを示す断面図である。図に
おいて、１１ｂは半導体チップ１１の接合面に形成した
複数の凹部であって、矩形状の断面を構成する。なお、
図１と同一構成要素には同一符号を付して重複する説明
を省略する。Embodiment 2. 3 is a sectional view showing a semiconductor package according to a second embodiment of the present invention. In the figure, 11b is a plurality of recesses formed on the bonding surface of the semiconductor chip 11 and constitutes a rectangular cross section. In addition,
The same components as those in FIG. 1 are designated by the same reference numerals, and overlapping description will be omitted.

【００２５】次に概要について説明する。図３に示すよ
うな凹部１１ｂを設けても、ダイボンディングペースト
１７の量が多い場合には、凹部１１ｂによってダイボン
ディングペースト１７の余剰分が導かれて、半導体チッ
プ１１の接合面全体に拡がることになる。しかも、搭載
部１４ａには段差１４ｂを介して周囲部１４ｃが連続し
ているから、余剰分は段差１４ｂから周囲部１４ｃに落
ちる。この結果、ダイボンディングペースト１７の余剰
分が半導体チップ１１の側面及び／又は表面にはみ出す
ことがなくなる。また、ダイボンディングペースト１７
の量が少ない場合でも、凹部１１ｂによって接合面積が
増加していることから、十分な接着強度を得ることがで
きる。Next, an outline will be described. Even if the recess 11b as shown in FIG. 3 is provided, when the amount of the die bonding paste 17 is large, the recess 11b guides the excess of the die bonding paste 17 and spreads over the entire bonding surface of the semiconductor chip 11. become. Moreover, since the peripheral portion 14c is continuous to the mounting portion 14a via the step 14b, the surplus portion falls from the step 14b to the peripheral portion 14c. As a result, the surplus portion of the die bonding paste 17 does not overflow to the side surface and / or the surface of the semiconductor chip 11. In addition, the die bonding paste 17
Even if the amount is small, since the joint area is increased by the recess 11b, sufficient adhesive strength can be obtained.

【００２６】以上のように、この実施の形態２によれ
ば、ダイパッド部１４が搭載部１４ａと、この搭載部１
４ａの周囲に段差１４ｂを設けてなる周囲部１４ｃを有
し、半導体チップ１１の接合面に複数の凹部１１ｂを形
成したので、ダイボンディングペースト１７のはみ出し
を防止することができるばかりでなく、接着強度を向上
させることができる。As described above, according to the second embodiment, the die pad portion 14 has the mounting portion 14a and the mounting portion 1
4a has a peripheral portion 14c provided with a step 14b and a plurality of concave portions 11b are formed in the bonding surface of the semiconductor chip 11, so that the die bonding paste 17 can be prevented from protruding and the adhesive can be adhered. The strength can be improved.

【００２７】実施の形態３．図４はこの発明の実施の形
態３による半導体パッケージを示す断面図である。図に
おいて、１１ｃは半導体チップ１１の接合面に形成した
溝部（凹部）である。また、溝部１１ｃの幅は、半導体
チップ１１の幅よりも狭ければよい。なお、図１と同一
構成要素には同一符号を付して重複する説明を省略す
る。Embodiment 3. 4 is a sectional view showing a semiconductor package according to a third embodiment of the present invention. In the figure, 11c is a groove (recess) formed on the bonding surface of the semiconductor chip 11. Further, the width of the groove 11c may be smaller than the width of the semiconductor chip 11. In addition, the same components as those in FIG. 1 are designated by the same reference numerals, and duplicate description will be omitted.

【００２８】次に概要について説明する。図４に示すよ
うな溝部１１ｃを設けても、ダイボンディングペースト
１７の使用量が多い場合には、溝部１１ｃによってダイ
ボンディングペースト１７の余剰分が導かれると共に、
搭載部１４ａには段差１４ｂを介して周囲部１４ｃが連
続しているから、余剰分は段差１４ｂから周囲部１４ｃ
に落ちる。この結果、ダイボンディングペースト１７の
余剰分が半導体チップ１１の側面及び／又は表面にはみ
出すことがなくなる。また、ダイボンディングペースト
１７の使用量が少ない場合でも、凹部１１ｃによって接
合面積が増加していることから、十分な接着強度を得る
ことができる。Next, an outline will be described. Even if the groove portion 11c as shown in FIG. 4 is provided, when the die bonding paste 17 is used in a large amount, the groove portion 11c guides an excess amount of the die bonding paste 17, and
Since the peripheral portion 14c is continuous to the mounting portion 14a via the step 14b, the surplus portion is transferred from the step 14b to the peripheral portion 14c.
fall into. As a result, the surplus portion of the die bonding paste 17 does not overflow to the side surface and / or the surface of the semiconductor chip 11. Further, even when the die bonding paste 17 is used in a small amount, a sufficient bonding strength can be obtained because the joint area is increased by the recess 11c.

【００２９】以上のように、この実施の形態３によれ
ば、ダイパッド部１４が搭載部１４ａと、この搭載部１
４ａの周囲に段差１４ｂを設けてなる周囲部１４ｃを有
し、半導体チップ１１の接合面に溝部１１ｃを形成した
ので、ダイボンディングペースト１７のはみ出しを防止
することができるばかりでなく、接着強度を向上させる
ことができる。As described above, according to the third embodiment, the die pad portion 14 has the mounting portion 14a and the mounting portion 1
Since the groove portion 11c is formed in the bonding surface of the semiconductor chip 11, the die bonding paste 17 can be prevented from protruding and the adhesive strength can be improved. Can be improved.

【００３０】実施の形態４．図５はこの発明の実施の形
態４による半導体パッケージを示す断面図である。図に
おいて、１４１は搭載部１４ａの中央部に形成した溝
部、１４２，１４３は溝部１４１によって分割された搭
載部１４ａの搭載部分である。また、溝部１４１の幅
は、半導体チップ１１の幅よりも狭ければよい。なお、
図１と同一構成要素には同一符号を付して重複する説明
を省略する。Fourth Embodiment 5 is a sectional view showing a semiconductor package according to a fourth embodiment of the present invention. In the figure, 141 is a groove formed in the center of the mounting portion 14a, and 142 and 143 are mounting portions of the mounting portion 14a divided by the groove 141. The width of the groove 141 may be smaller than the width of the semiconductor chip 11. In addition,
The same components as those in FIG. 1 are designated by the same reference numerals, and overlapping description will be omitted.

【００３１】次に概要について説明する。ダイボンディ
ングペースト１７の使用量が多い場合には、凹部１１ａ
によってダイボンディングペースト１７の余剰分が導か
れて、半導体チップ１１の接合面全体に拡がることにな
る。さらに、搭載部１４ａに溝部１４１が設けられてい
るから、余剰分がこの溝部１４１にも溜まることにな
る。しかも、搭載部１４ａには段差１４ｂを介して周囲
部１４ｃが連続しているから、余剰分は段差１４ｂから
周囲部１４ｃに落ちることになる。この結果、ダイボン
ディングペースト１７の余剰分が半導体チップ１１の側
面及び／又は表面にはみ出すことがなくなる。また、ダ
イボンディングペースト１７の使用量が少ない場合で
も、凹部１１ａによって接合面積が増加していることか
ら、十分な接着強度を得ることができる。Next, an outline will be described. When the die bonding paste 17 is used in a large amount, the recess 11a is formed.
As a result, the surplus of the die bonding paste 17 is guided and spreads over the entire bonding surface of the semiconductor chip 11. Further, since the mounting portion 14a is provided with the groove portion 141, the surplus is also accumulated in this groove portion 141. Moreover, since the peripheral portion 14c is continuous with the mounting portion 14a via the step 14b, the surplus portion falls from the step 14b to the peripheral portion 14c. As a result, the surplus portion of the die bonding paste 17 does not overflow to the side surface and / or the surface of the semiconductor chip 11. Further, even when the die bonding paste 17 is used in a small amount, a sufficient bonding strength can be obtained because the joint area is increased by the recess 11a.

【００３２】以上のように、この実施の形態４によれ
ば、ダイパッド部１４が搭載部１４ａと、この搭載部１
４ａの周囲に段差１４ｂを設けてなる周囲部１４ｃと、
ダイパッド部１４の搭載部１４ａに形成した溝部１４１
と、半導体チップ１１の接合面に複数の凹部１１ａを形
成したので、ダイボンディングペースト１７のはみ出し
を防止することができるばかりでなく、接着強度を向上
させることができる。As described above, according to the fourth embodiment, the die pad portion 14 has the mounting portion 14a and the mounting portion 1
A peripheral portion 14c formed by providing a step 14b around 4a,
Groove portion 141 formed in the mounting portion 14a of the die pad portion 14
Since the plurality of recesses 11a are formed on the joint surface of the semiconductor chip 11, not only the protrusion of the die bonding paste 17 can be prevented, but also the adhesive strength can be improved.

【００３３】なお、図６に示すように、半導体チップ１
１の接合面に複数の凹部１１ｂを形成して、搭載部１４
ａに溝部１４１を形成してもよく、図７に示すように、
半導体チップ１１の接合面に溝部１１ｃを形成し、搭載
部１４ａに溝部１４１を形成してもよい。さらに、図８
に示すように、外部入出力に使用する端子として、針状
でなくボール形状の入出力ピン１２ｄを有するパッケー
ジに適用してもかまわない。As shown in FIG. 6, the semiconductor chip 1
A plurality of recesses 11b are formed on the joint surface of No. 1, and the mounting portion 14
The groove 141 may be formed in a, and as shown in FIG.
The groove 11c may be formed on the bonding surface of the semiconductor chip 11 and the groove 141 may be formed on the mounting portion 14a. Furthermore, FIG.
As shown in, the package may be applied to a package having a ball-shaped input / output pin 12d rather than a needle as a terminal used for external input / output.

【００３４】また、本発明は、モールド樹脂でフレーム
に搭載した半導体チップを硬化させるタイプの半導体パ
ッケージに適用することもできる。図９はこのタイプの
半導体パッケージを示す図であり、本発明の効果を最大
限に得るために、フレーム１８にも、半導体チップ１１
を搭載する搭載部１８ａと、この搭載部１８ａの周囲に
段差１８ｂを設けてなる周囲部（下段部）１８ｃとを設
けておく。このフレーム１８に、上記実施の形態と同様
にして、半導体チップ１１を実装し、モールド樹脂で１
９で硬化させることで、上記と同様の効果を得ることが
できる。さらに、図１０に示すように、入出力ピン１２
ｃ，１２ｄを要しないリードフレームタイプの半導体パ
ッケージに適用しても良い。例えば、表面実装タイプの
ＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）やＳＯ
Ｐ（Ｓｍａｌｌ ＯｕｔｌｉｎｅＰａｃｋａｇｅ）など
のリード形状にも適用できる。この場合、リードフレー
ム２０にも 、半導体チップ１１を搭載する搭載部２０
ａと、この搭載部２０ａの周囲に段差２０ｂを設けてな
る周囲部（下段部）２０ｃとを設けておくことで、本発
明の効果を最大限に得ることができる。The present invention can also be applied to a semiconductor package of a type in which a semiconductor chip mounted on a frame is cured with a molding resin. FIG. 9 is a diagram showing a semiconductor package of this type. In order to maximize the effects of the present invention, the frame 18 and the semiconductor chip 11 are also provided.
A mounting portion 18a for mounting the mounting portion 18a and a peripheral portion (lower portion) 18c provided with a step 18b around the mounting portion 18a are provided. The semiconductor chip 11 is mounted on the frame 18 in the same manner as in the above-described embodiment, and the semiconductor chip 11 is molded with a resin.
By curing at 9, the same effect as above can be obtained. Further, as shown in FIG.
It may be applied to a lead frame type semiconductor package that does not require c and 12d. For example, surface mount type QFP (Quad Flat Package) and SO
It can also be applied to a lead shape such as P (Small Outline Package). In this case, the lead frame 20 is also mounted on the mounting portion 20 on which the semiconductor chip 11 is mounted.
The effect of the present invention can be maximized by providing a and a peripheral portion (lower step) 20c in which a step 20b is provided around the mounting portion 20a.

【００３５】[0035]

【発明の効果】以上のように、この発明によれば、半導
体チップを収納するパッケージ筐体と、パッケージ筐体
内に設けられ、半導体チップを接着固定するダイパッド
部と、半導体チップの接着面に形成した凹部とを備える
ので、ダイボンディングペーストのはみ出しを防止する
ことができるばかりでなく十分な接着強度を得ることが
できるという効果がある。As described above, according to the present invention, a package housing for housing a semiconductor chip, a die pad portion provided inside the package housing for fixing the semiconductor chip by adhesion, and formed on the bonding surface of the semiconductor chip. Since the recesses are provided, not only the die bonding paste can be prevented from protruding, but also sufficient adhesive strength can be obtained.

【００３６】この発明によれば、半導体チップの接着面
に複数の凹部を形成したので、さらに接着強度を向上さ
せることができるという効果がある。According to the present invention, since a plurality of recesses are formed on the bonding surface of the semiconductor chip, there is an effect that the bonding strength can be further improved.

【００３７】この発明によれば、ダイパッド部が、半導
体チップが搭載される搭載部と、該搭載部の周辺部に段
差を設けてなる下段部とを備えるので、ダイボンディン
グペーストのはみ出しを防止することができるという効
果がある。According to the present invention, since the die pad portion includes the mounting portion on which the semiconductor chip is mounted and the lower step portion having a step on the peripheral portion of the mounting portion, the die bonding paste is prevented from protruding. The effect is that you can.

【００３８】この発明によれば、搭載部の半導体チップ
搭載面に溝部を形成したので、ダイボンディングペース
トのはみ出しを防止することができるばかりでなく十分
な接着強度を得ることができるという効果がある。According to the present invention, since the groove portion is formed on the semiconductor chip mounting surface of the mounting portion, it is possible not only to prevent the die bonding paste from protruding but also to obtain a sufficient adhesive strength. .

【図面の簡単な説明】[Brief description of drawings]

【図１】 この発明の実施の形態１による半導体パッケ
ージを示す断面図である。FIG. 1 is a sectional view showing a semiconductor package according to a first embodiment of the present invention.

【図２】 実施の形態１による半導体パッケージにおい
てダイボンディングペーストの使用量が少ない場合を示
す断面図である。FIG. 2 is a cross-sectional view showing a case where the amount of die bonding paste used is small in the semiconductor package according to the first embodiment.

【図３】 この発明の実施の形態２による半導体パッケ
ージを示す断面図である。FIG. 3 is a sectional view showing a semiconductor package according to a second embodiment of the present invention.

【図４】 この発明の実施の形態３による半導体パッケ
ージを示す断面図である。FIG. 4 is a sectional view showing a semiconductor package according to a third embodiment of the present invention.

【図５】 この発明の実施の形態４による半導体パッケ
ージを示す断面図である。FIG. 5 is a sectional view showing a semiconductor package according to a fourth embodiment of the present invention.

【図６】 この発明による半導体パッケージの他の例を
示す断面図である。FIG. 6 is a sectional view showing another example of the semiconductor package according to the present invention.

【図７】 この発明による半導体パッケージのさらに他
の例を示す断面図である。FIG. 7 is a sectional view showing still another example of the semiconductor package according to the present invention.

【図８】 この発明による半導体パッケージのさらに他
の例を示す断面図である。FIG. 8 is a sectional view showing still another example of the semiconductor package according to the present invention.

【図９】 この発明による半導体パッケージのさらに他
の例を示す断面図である。FIG. 9 is a sectional view showing still another example of the semiconductor package according to the present invention.

【図１０】 この発明による半導体パッケージのさらに
他の例を示す断面図である。FIG. 10 is a sectional view showing still another example of the semiconductor package according to the present invention.

【符号の説明】[Explanation of symbols]

１１ 半導体チップ、１１ａ，１１ｂ，１１ｃ 凹部、
１２ パッケージ（パッケージ筐体）、１２ａ 基部、
１２ｂ 蓋部、１２ｃ 入出力ピン、１３ 半導体パッ
ケージ、１４ ダイパッド部、１４ａ，１８ａ，２０ａ
搭載部、１４ｂ，１４ｄ，１８ｂ，２０ｂ 段差、１
４ｃ，１８ｃ，２０ｃ 周囲部（下段部）、１５ 接続
面部、１６ 金線、１７ ダイボンディングペースト、
１８ フレーム、１９ モールド樹脂、２０ リードフ
レーム、１４１ 溝部、１４２，１４３ 搭載部分。11 semiconductor chips, 11a, 11b, 11c recesses,
12 package (package housing), 12a base,
12b lid part, 12c input / output pin, 13 semiconductor package, 14 die pad part, 14a, 18a, 20a
Mounting part, 14b, 14d, 18b, 20b Step, 1
4c, 18c, 20c Surrounding part (lower part), 15 Connection surface part, 16 Gold wire, 17 Die bonding paste,
18 frames, 19 mold resin, 20 lead frames, 141 grooves, 142, 143 mounting parts.

Claims (4)

【特許請求の範囲】[Claims] 【請求項１】 半導体チップを収納するパッケージ筐体
と、 上記パッケージ筐体内に設けられ、上記半導体チップを
接着固定するダイパッド部と、 上記半導体チップの接着面に形成した凹部とを備えた半
導体パッケージ。1. A semiconductor package comprising a package housing for accommodating a semiconductor chip, a die pad portion provided in the package housing for fixing the semiconductor chip by adhesion, and a recess formed on the bonding surface of the semiconductor chip. . 【請求項２】 半導体チップの接着面に複数の凹部を形
成したことを特徴とする請求項１記載の半導体パッケー
ジ。2. The semiconductor package according to claim 1, wherein a plurality of recesses are formed on the bonding surface of the semiconductor chip. 【請求項３】 ダイパッド部は、半導体チップが搭載さ
れる搭載部と、該搭載部の周辺部に段差を設けてなる下
段部とを備えたことを特徴とする請求項１又は請求項２
記載の半導体パッケージ。3. The die pad portion includes a mounting portion on which a semiconductor chip is mounted, and a lower step portion having a step on the periphery of the mounting portion.
The semiconductor package described. 【請求項４】 搭載部の半導体チップ搭載面に溝部を形
成したことを特徴とする請求項３記載の半導体パッケー
ジ。4. The semiconductor package according to claim 3, wherein a groove portion is formed on the semiconductor chip mounting surface of the mounting portion.
JP2001369080A 2001-12-03 2001-12-03 Semiconductor package Pending JP2003168694A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2001369080A JP2003168694A (en) 2001-12-03 2001-12-03 Semiconductor package
KR1020020045723A KR20030047688A (en) 2001-12-03 2002-08-02 Semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2001369080A JP2003168694A (en) 2001-12-03 2001-12-03 Semiconductor package

Publications (1)

Publication Number Publication Date
JP2003168694A true JP2003168694A (en) 2003-06-13

Family

ID=19178547

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001369080A Pending JP2003168694A (en) 2001-12-03 2001-12-03 Semiconductor package

Country Status (2)

Country Link
JP (1) JP2003168694A (en)
KR (1) KR20030047688A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258413A (en) * 2007-04-05 2008-10-23 Rohm Co Ltd Semiconductor light-emitting device
JP2009272359A (en) * 2008-05-01 2009-11-19 Powertech Technology Inc Semiconductor package
JP2012060129A (en) * 2010-09-09 2012-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Chip element equipped with wire insertion groove
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module
KR101423136B1 (en) * 2012-12-28 2014-07-25 한국광기술원 Semiconductor bonding assembly and semiconductor bonding method
KR101455178B1 (en) * 2014-02-27 2014-10-27 한국광기술원 Semiconductor bonding assembly
CN104332448A (en) * 2013-03-05 2015-02-04 弗莱克斯电子有限责任公司 Escape routes
KR101737149B1 (en) * 2009-11-02 2017-05-17 트랜스폼 인크. Electronic component, method of forming an electronic component, assembly, half bridge, and bridge circuit for low emi circuits

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01241828A (en) * 1988-03-23 1989-09-26 Mitsubishi Electric Corp Semiconductor package
JPH01282840A (en) * 1988-05-09 1989-11-14 Nec Kyushu Ltd Ceramic case for semiconductor
JPH04312933A (en) * 1991-03-29 1992-11-04 Mitsubishi Electric Corp Semiconductor device
JPH04332140A (en) * 1991-05-07 1992-11-19 Mitsubishi Electric Corp Package for semiconductor device
JPH05308083A (en) * 1992-04-30 1993-11-19 Nippon Steel Corp Semiconductor device
JPH06196511A (en) * 1992-12-24 1994-07-15 Kawasaki Steel Corp Semiconductor device
KR100201379B1 (en) * 1995-11-17 1999-06-15 김규현 Attaching method of semiconductor chip using a solder ball and structure of the same

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008258413A (en) * 2007-04-05 2008-10-23 Rohm Co Ltd Semiconductor light-emitting device
JP2009272359A (en) * 2008-05-01 2009-11-19 Powertech Technology Inc Semiconductor package
KR101737149B1 (en) * 2009-11-02 2017-05-17 트랜스폼 인크. Electronic component, method of forming an electronic component, assembly, half bridge, and bridge circuit for low emi circuits
JP2012060129A (en) * 2010-09-09 2012-03-22 Commissariat A L'energie Atomique Et Aux Energies Alternatives Chip element equipped with wire insertion groove
JP2013008771A (en) * 2011-06-23 2013-01-10 Nissan Motor Co Ltd Semiconductor module
KR101423136B1 (en) * 2012-12-28 2014-07-25 한국광기술원 Semiconductor bonding assembly and semiconductor bonding method
CN104332448A (en) * 2013-03-05 2015-02-04 弗莱克斯电子有限责任公司 Escape routes
KR101455178B1 (en) * 2014-02-27 2014-10-27 한국광기술원 Semiconductor bonding assembly

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