KR100460072B1 - Semiconductor Package - Google Patents
Semiconductor Package Download PDFInfo
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- KR100460072B1 KR100460072B1 KR10-1998-0025826A KR19980025826A KR100460072B1 KR 100460072 B1 KR100460072 B1 KR 100460072B1 KR 19980025826 A KR19980025826 A KR 19980025826A KR 100460072 B1 KR100460072 B1 KR 100460072B1
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- semiconductor chip
- lead portion
- inner lead
- thickness
- semiconductor package
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
본 발명은 반도체 패키지를 개시한다. 개시된 본 발명의 반도체 패키지는, 상부면에 본딩패드들이 구비된 반도체 칩; 상기 반도체 칩의 상부면에 양면 접착 테이프의 개재하에 부착되는 인너 리드 부분과, 상기 인너 리드 부분으로부터 다운-세트된 형태로 반도체 칩의 외측으로 연장·배치되는 아웃 리드 부분으로 구성되는 리드; 상기 반도체 칩의 본딩패드와 인너 리드 부분의 측면을 전기적으로 접속시키는 범프; 및 상기 반도체 칩의 상부면과 그 상부에 배치된 인너 리드 부분을 밀봉하는 봉지제를 포함하며, 상기 리드들은 반도체 칩의 상부면에 대칭되게 배치됨과 동시에 리드의 인너 리드 부분의 측면은 상기 반도체 칩의 본딩패드와 근접되게 배치되어 있는 것을 특징으로 한다. The present invention discloses a semiconductor package. The disclosed semiconductor package includes a semiconductor chip having bonding pads formed on an upper surface thereof; A lead composed of an inner lead portion attached to an upper surface of the semiconductor chip via a double-sided adhesive tape and an out lead portion extending and arranged outwardly of the semiconductor chip in a form down-set from the inner lead portion; A bump electrically connecting side surfaces of the bonding pad and the inner lead portion of the semiconductor chip; And an encapsulant for sealing an upper surface of the semiconductor chip and an inner lead portion disposed on the upper surface of the semiconductor chip, wherein the leads are symmetrically disposed on the upper surface of the semiconductor chip and at the same time a side surface of the inner lead portion of the lead is formed on the semiconductor chip. It is characterized in that it is disposed in close proximity to the bonding pad.
Description
본 발명은 반도체 패키지에 관한 것으로, 보다 상세하게는, 트림 및 포밍 공정을 삭제시킬 수 있는 반도체 패키지에 관한 것이다. The present invention relates to a semiconductor package, and more particularly, to a semiconductor package capable of eliminating trim and forming processes.
일반적으로, 공지된 공정을 통해 제조된 반도체 칩들은 칩 절단(Sawing), 칩 부착(Die Attach), 와이어 본딩(Wire Bonding), 몰딩(Molding) 및 트림/포밍(Trim/Forming) 등 일련의 어셈블리(Assembly) 공정을 거쳐 반도체 패키지로 제작된다.In general, semiconductor chips manufactured through a known process are a series of assemblies such as chip cutting, die attach, wire bonding, molding and trim / forming. It is manufactured into a semiconductor package through an assembly process.
상기한 어셈블리 공정을 통해 제작된 반도체 패키지의 전형적인 예가 도 1 에 도시되어 있는바, 이를 설명하면 다음과 같다. A typical example of a semiconductor package manufactured through the above assembly process is illustrated in FIG. 1, which will be described below.
도시된 바와 같이, 본딩패드들(1a)이 구비된 반도체 칩(1)은 리드 프레임(Lead Frame)의 다이 패드(Die Pad : 2a) 상에 부착되어 있으며, 반도체 칩(1)의 본딩패드들(1a)과 리드 프레임의 인너 리드(Inner Lead : 2b)는 금속 와이어(3)에 의해 전기적으로 연결되어 있다. As shown, the semiconductor chip 1 with the bonding pads 1a is attached on a die pad 2a of a lead frame, and the bonding pads of the semiconductor chip 1 are attached. The inner lead 2b of the lead frame 1a is electrically connected by the metal wire 3.
그리고, 반도체 칩(1) 및 이에 와이어 본딩된 인너 리드(2b)를 포함한 공간적 영역은 에폭시 수지와 같은 몰딩 컴파운드(Epoxy Molding Compound)에 의해 봉지되어 있고, 몰딩 컴파운드로된 봉지제(4)의 외측으로는 기판에의 실장을 위한 리드 프레임의 아웃 리드(Out Lead : 2c)가 돌출되어 있으며, 아울러, 아웃 리드는 소정의 형태로 절곡되어 있다. The spatial region including the semiconductor chip 1 and the inner lead 2b wire-bonded thereto is encapsulated by an epoxy molding compound such as an epoxy resin, and the outer side of the encapsulant 4 made of the molding compound. An out lead (Out Lead: 2c) of the lead frame for mounting on the substrate protrudes, and the out lead is bent in a predetermined form.
그러나, 상기와 같은 종래의 어셈블리 공정에서는 봉지제를 형성하기 위한 몰딩 공정후에, 리드 프레임들간을 연결하고 있는 댐바를 절단시키기 위한 트림 공정과, 아웃 리드 부분을 소정의 형상으로 절곡시키기 위한 포밍 공정이 실시되는 것으로 인하여 공정이 복잡한 문제점이 있었다. However, in the conventional assembly process as described above, after a molding process for forming an encapsulant, a trim process for cutting the dam bar connecting the lead frames, and a forming process for bending the out lead portion to a predetermined shape There was a complicated problem due to the process being carried out.
따라서, 본 발명은 상기와 같은 문제점을 해결하기 위하여 안출된 것으로, 트림 및 포밍 공정을 삭제시킬 수 있는 반도체 패키지를 제공하는데, 그 목적이 있다. Accordingly, an object of the present invention is to provide a semiconductor package capable of eliminating the trimming and forming process.
상기와 같은 목적을 달성하기 위한 본 발명의 반도체 패키지는, 상부면에 본딩패드들이 구비된 반도체 칩; 상기 반도체 칩의 상부면에 양면 접착 테이프의 개재하에 부착되는 인너 리드 부분과, 상기 인너 리드 부분으로부터 다운-세트된 형태로 반도체 칩의 외측으로 연장·배치되는 아웃 리드 부분으로 구성되는 리드; 상기 반도체 칩의 본딩패드와 인너 리드 부분의 측면을 전기적으로 접속시키는 범프; 및 상기 반도체 칩의 상부면과 그 상부에 배치된 인너 리드 부분을 밀봉하는 봉지제를 포함하며, 상기 리드들은 반도체 칩의 상부면에 대칭되게 배치됨과 동시에 리드의 인너 리드 부분의 측면은 상기 반도체 칩의 본딩패드와 근접되게 배치되어 있는 것을 특징으로 한다. The semiconductor package of the present invention for achieving the above object, the semiconductor chip provided with bonding pads on the upper surface; A lead composed of an inner lead portion attached to an upper surface of the semiconductor chip via a double-sided adhesive tape and an out lead portion extending and arranged outwardly of the semiconductor chip in a form down-set from the inner lead portion; A bump electrically connecting side surfaces of the bonding pad and the inner lead portion of the semiconductor chip; And an encapsulant for sealing an upper surface of the semiconductor chip and an inner lead portion disposed on the upper surface of the semiconductor chip, wherein the leads are symmetrically disposed on the upper surface of the semiconductor chip and at the same time a side surface of the inner lead portion of the lead is formed on the semiconductor chip. It is characterized in that it is disposed in close proximity to the bonding pad.
본 발명에 따르면, 양면 접착 테이프 상에 수 개의 리드들을 부착시키고, 이렇게 제작된 테이프 리드를 반도체 칩 상에 부착시킴으로써, 비교적 간단한 방법으로 반도체 패키지를 제작할 수 있다.According to the present invention, by attaching several leads onto a double-sided adhesive tape and attaching the tape leads thus produced onto a semiconductor chip, a semiconductor package can be manufactured in a relatively simple method.
이하, 첨부한 도면에 의거하여 본 발명의 바람직한 실시예를 보다 상세하게 설명하도록 한다.Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2는 본 발명의 실시예에 따른 테이프 리드를 도시한 평면도로서, 도시된 바와 같이, 테이프 리드(20)는 50 내지 70㎛의 두께로된 양면 접착 테이프(11)와 그의 일측면에 부착되는 75 내지 100㎛ 두께로된 다수개의 리드들(12)로 이루어진다. 2 is a plan view showing a tape lead according to an embodiment of the present invention. As shown, the tape lead 20 is attached to a double-sided adhesive tape 11 having a thickness of 50 to 70 μm and one side thereof. It consists of a plurality of leads 12 of 75 to 100 μm thickness.
여기서, 양면 접착 테이프(11)는 열가소성(Thermoplastic)계 테이프이며, 인너 리드 부분(12a)과 아웃 리드 부분(12b)으로 구성되는 리드(12)는 댐바없이 양면 접착 테이프 상에 각각 부착되고, 아울러, 양면 접착 테이프(11)에 부착되는 인너 리드(12a) 부분의 측면에는 반도체 칩과의 안정적인 전기적 접속을 위해 도전 물질, 즉, 은(Silver, 13)이 플레이팅된다. Here, the double-sided adhesive tape 11 is a thermoplastic tape, and the leads 12 composed of the inner lead portion 12a and the out lead portion 12b are respectively attached onto the double-sided adhesive tape without a dambar, On the side surface of the inner lead 12a attached to the double-sided adhesive tape 11, a conductive material, namely, silver 13 is plated for stable electrical connection with the semiconductor chip.
또한, 도시되지는 않았으나, 아웃 리드 부분(12b)은 다운-세트(Down-Set)의 형태로 절곡되어 있다. In addition, although not shown, the out lead portion 12b is bent in the form of a down-set.
도 3은 상기된 테이프 리드를 이용한 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도이다.3 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention using the above-described tape lead.
도시된 바와 같이, 양면 접착 테이프(11)에 리드들(12)이 부착되어 있는 테이프 리드가 열압착 방식에 의해 상부면에 본딩패드들(도시안됨)이 구비된 반도체 칩(21) 상에 대칭되게 부착되며, 상기 반도체 칩(21)과 리드의 인너 리드 부분(12a)은 금(Au) 범프(22)에 의해 전기적으로 접속된다. 이때, 리드의 인너 리드 부분(12a)은 금 범프에 의해 반도체 칩의 본딩패드와 접속될 수 있도록 상기 본딩패드에 최대한 근접되게 배치되도록 한다. As shown, the tape leads with the leads 12 attached to the double-sided adhesive tape 11 are symmetrical on the semiconductor chip 21 with bonding pads (not shown) on the upper surface by thermocompression bonding. The semiconductor chip 21 and the inner lead portion 12a of the lead are electrically connected by the gold bumps 22. At this time, the inner lead portion 12a of the lead is arranged to be as close to the bonding pad as possible so as to be connected to the bonding pad of the semiconductor chip by gold bumps.
계속해서, 반도체 칩(21)의 상부면, 즉, 액티브면이 외부 영향에 의해 손상되는 것이 방지되도록 반도체 칩(21)의 상부면과 상기 반도체 칩(21) 상에 부착된 리드의 인너 리드 부분(12a)은 실리콘계 또는 에폭시계 레진으로 이루어진 봉지제(23)에 의해 밀봉된다. Subsequently, an inner lead portion of the upper surface of the semiconductor chip 21 and the leads attached to the semiconductor chip 21 so that the upper surface of the semiconductor chip 21, that is, the active surface is prevented from being damaged by external influences. 12a is sealed by the sealing agent 23 which consists of silicone type or epoxy type resin.
상기에서, 금 범프(22)는 그의 높이가 리드의 상부면 보다 높게 되지 않도록 대략 80 내지 100㎛ 높이로 형성되며, 봉지제(23)는 200 내지 300㎛ 두께로 형성된다. 이에 따라, 패키지의 전체적인 두께는 대략 0.5mm 정도가 된다. In the above, the gold bumps 22 are formed to a height of approximately 80 to 100 µm so that their height does not become higher than the upper surface of the lid, and the encapsulant 23 is formed to a thickness of 200 to 300 µm. Accordingly, the overall thickness of the package is about 0.5 mm.
또한, 앞서 설명한 바와 같이, 인너 리드 부분(12a)의 측면에는 은(13)이 플레이팅되어 있기 때문에 이러한 인너 리드(12a)와 반도체 칩(11)의 본딩패드는 금 범프(22)에 의해 안정적으로 전기적 접속이 이루어진다. In addition, as described above, since the silver 13 is plated on the side surface of the inner lead portion 12a, the bonding pads of the inner lead 12a and the semiconductor chip 11 are stable by the gold bumps 22. Electrical connection is made.
한편, 본 발명의 실시예에 따른 반도체 패키지는 반도체 칩의 두께를 175 내지 200㎛, 리드의 두께를 75 내지 100㎛, 양면 접착 테이프의 두께를 50 내지 70㎛, 범프의 두께를 80 내지 100㎛, 봉지제의 두께를 200 내지 300㎛ 정도로 하여 전체적인 패키지의 두께가 0.5mm 정도가 되도록 제작하기 때문에, 종래 1.0mm의 두께를 갖는 TSOP(Thin Small Outline Package) 보다 더 얇게 제작할 수 있다. Meanwhile, the semiconductor package according to the embodiment of the present invention has a thickness of the semiconductor chip 175 to 200㎛, the thickness of the lead 75 to 100㎛, the thickness of the double-sided adhesive tape 50 to 70㎛, bump thickness 80 to 100㎛ Since the thickness of the encapsulant is about 200 to 300 μm, so that the overall package is about 0.5 mm thick, the thickness of the encapsulant may be thinner than that of a conventional TSOP (Thin Small Outline Package) having a thickness of 1.0 mm.
이상에서와 같이, 본 발명은 테이프 리드의 제작시에 인너 리드 부분과 아웃 리드 부분으로 구성되는 리드를 댐바없이 제작함과 동시에 상기 아웃 리드 부분이 다운-세트의 형태가 되도록 함으로써, 어셈블리 공정후에 트림 및 포밍 공정을 실시할 필요가 없게 되고, 이에 따라, 어셈블리 공정의 단순화를 얻을 수 있다. As described above, the present invention trims after the assembly process by making the lead consisting of the inner lead portion and the out lead portion without the dam bar at the time of manufacturing the tape lead, and the out lead portion to be in the form of a down-set. And it is not necessary to perform the forming step, whereby the assembly process can be simplified.
한편, 여기에서는 본 발명의 특정 실시예에 대하여 설명하고 도시하였지만, 당업자에 의하여 이에 대한 수정과 변형을 할 수 있다. 따라서, 이하, 특허청구의 범위는 본 발명의 진정한 사상과 범위에 속하는 한 모든 수정과 변형을 포함하는 것으로 이해할 수 있다.Meanwhile, although specific embodiments of the present invention have been described and illustrated, modifications and variations can be made by those skilled in the art. Accordingly, the following claims are to be understood as including all modifications and variations as long as they fall within the true spirit and scope of the present invention.
도 1은 종래 기술에 따른 반도체 패키지를 도시한 단면도. 1 is a cross-sectional view showing a semiconductor package according to the prior art.
도 2는 본 발명의 실시예에 따른 테이프 리드를 도시한 평면도. 2 is a plan view illustrating a tape lead according to an embodiment of the present invention.
도 3은 본 발명의 실시예에 따른 반도체 패키지를 도시한 단면도. 3 is a cross-sectional view showing a semiconductor package according to an embodiment of the present invention.
(도면의 주요 부분에 대한 부호의 설명)(Explanation of symbols for the main parts of the drawing)
11 : 양면 접착 테이프 12 : 리드11: double-sided adhesive tape 12: lead
12a : 인너 리드 부분 12b : 아웃 리드 부분12a: inner lead portion 12b: out lead portion
13 : 은 20 : 테이프 리드13: silver 20: tape lead
21 : 반도체 칩 22 : 금 범프21: semiconductor chip 22: gold bump
23 : 봉지제23: sealing agent
Claims (5)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025826A KR100460072B1 (en) | 1998-06-30 | 1998-06-30 | Semiconductor Package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR10-1998-0025826A KR100460072B1 (en) | 1998-06-30 | 1998-06-30 | Semiconductor Package |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR20000004394A KR20000004394A (en) | 2000-01-25 |
| KR100460072B1 true KR100460072B1 (en) | 2005-02-24 |
Family
ID=19542214
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR10-1998-0025826A KR100460072B1 (en) | 1998-06-30 | 1998-06-30 | Semiconductor Package |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR100460072B1 (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0444347A (en) * | 1990-06-11 | 1992-02-14 | Hitachi Ltd | Semiconductor device |
| KR970067796A (en) * | 1996-03-23 | 1997-10-13 | 김광호 | LOC package with internal leads directly bonded to bonding pads |
| KR980012307A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Lead-on-Chip (LOC) package with metal bumps |
| KR200157926Y1 (en) * | 1996-06-27 | 1999-10-01 | 김영환 | Lead on chip package |
-
1998
- 1998-06-30 KR KR10-1998-0025826A patent/KR100460072B1/en not_active IP Right Cessation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0444347A (en) * | 1990-06-11 | 1992-02-14 | Hitachi Ltd | Semiconductor device |
| KR970067796A (en) * | 1996-03-23 | 1997-10-13 | 김광호 | LOC package with internal leads directly bonded to bonding pads |
| KR200157926Y1 (en) * | 1996-06-27 | 1999-10-01 | 김영환 | Lead on chip package |
| KR980012307A (en) * | 1996-07-19 | 1998-04-30 | 김광호 | Lead-on-Chip (LOC) package with metal bumps |
Also Published As
| Publication number | Publication date |
|---|---|
| KR20000004394A (en) | 2000-01-25 |
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