JP5149688B2 - Semiconductor package - Google Patents

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JP5149688B2
JP5149688B2 JP2008119501A JP2008119501A JP5149688B2 JP 5149688 B2 JP5149688 B2 JP 5149688B2 JP 2008119501 A JP2008119501 A JP 2008119501A JP 2008119501 A JP2008119501 A JP 2008119501A JP 5149688 B2 JP5149688 B2 JP 5149688B2
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substrate
die
semiconductor package
chip
mounting surface
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JP2009272359A (en
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文正 范
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力成科技股▲分▼有限公司
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
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    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2924/151—Die mounting substrate
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    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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    • H01L2924/351—Thermal stress

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

本発明は、半導体実装技術を使用する半導体装置に係り、詳細には、熱サイクル試験を受ける製品に対する信頼性を向上させるため、外接球接点の移動変化による増益効果がある半導体パッケージに関する。   The present invention relates to a semiconductor device using a semiconductor packaging technology, and more particularly, to a semiconductor package having an effect of increasing profit due to a change in movement of a circumscribed ball contact in order to improve reliability of a product subjected to a thermal cycle test.

半導体パッケージは、内部に封止される半導体チップの様々な集積回路によって異なるパッケージ形態が出来る。例えば、ボールグリッドアレイ（ＢＧＡ、Ball Grid Array） パッケージは製品の底面にソルダリフロー（solder reflow）方式で形成した複数の外接球接点（一般には半田ボールやソルダボールと称する）を設置している。この外接球接点群は、半導体パッケージのＩ／Ｏ接続端末として適当な数量だけを用意して同一接合面に形成され、運算中に外部のプリント回路基板と電気接続して高密度表面接合の要求に達する。接合面は通常基板の露出面を利用し、半導体実装過程において、基板は色々な加熱処理を受け、例えば、ダイアタッチング接着材の加熱硬化、封止樹脂の硬化及び外接球接点のリフローなどがある。更に、運算や熱サイクル試験（ＴＣＴ、Thermal cycle Test）の進行中、熱膨張係数が合わないため半導体パッケージと外部のプリント回路基板との間に熱応力が生じ、基板の周辺や隅部及びチップの周縁にある外接球接点は特に熱応力の作用を受け易くなるので、基板の反り変形と半田ボールの断裂が起き、製品信頼性を低下させる。また、墜落テストにおいて、基板の周辺や隅部にある外接球接点（或は周縁ボールと隅部ボールと称する）は衝撃力に遭い易くなるため落下問題がある。   The semiconductor package can have different package forms depending on various integrated circuits of semiconductor chips sealed inside. For example, a ball grid array (BGA) package has a plurality of circumscribed ball contacts (generally referred to as solder balls and solder balls) formed by a solder reflow method on the bottom surface of a product. This circumscribing ball contact group is prepared on the same joint surface as an I / O connection terminal of a semiconductor package, and is formed on the same joint surface. To reach. The bonding surface normally uses the exposed surface of the substrate, and the substrate is subjected to various heat treatments in the semiconductor mounting process, for example, heat curing of the die attach adhesive, curing of the sealing resin, and reflow of the circumscribed ball contact. . Furthermore, during the course of calculation and thermal cycle test (TCT), the thermal expansion coefficient does not match, so thermal stress is generated between the semiconductor package and the external printed circuit board. The circumscribing ball contact at the periphery of the substrate is particularly susceptible to the effects of thermal stress, causing warpage deformation of the substrate and tearing of the solder balls, thereby reducing product reliability. Further, in the crash test, circumscribed ball contacts (or peripheral balls and corner balls) at the periphery and corners of the substrate are susceptible to impact force, and there is a drop problem.

図１に示すように、周知の半導体パッケージ１００は、 ウインドウ型ＢＧＡ（Ｗ‐ＢＧＡ、Window-Ball Grid Array）形態であり、主に一つの基板１１０、一つのダイアタッチング接着材１２０、一つのチップ１３０、複数の第一列外接球接点１４０及び複数の第二列外接球接点１５０を備える。基板１１０は一つの実装表面１１１、一つの露出表面１１２及び窓口としての貫通スロット１１５を有する。その露出表面１１２に一つの半田マスク層１１７を形成し、半田マスク層１１７は、複数の電気接続素子１６０と外接球接点群１４０、１５０との接合に使用する複数のインナーフィンガー１１６と複数の外接パッド１１８とを露出している。   As shown in FIG. 1, a well-known semiconductor package 100 is a window-type BGA (W-BGA, Window-Ball Grid Array) form, which mainly includes one substrate 110, one die attach adhesive 120, and one chip. 130, a plurality of first row circumscribed ball contacts 140 and a plurality of second row circumscribed ball contacts 150. The substrate 110 has one mounting surface 111, one exposed surface 112, and a through slot 115 as a window. One solder mask layer 117 is formed on the exposed surface 112, and the solder mask layer 117 is composed of a plurality of inner fingers 116 and a plurality of external contacts used for joining the plurality of electrical connection elements 160 and the circumscribed ball contact groups 140 and 150. The pad 118 is exposed.

基板１１０の実装表面１１１に形成したダイアタッチング接着材１２０を介してチップ１３０は基板１１０の上に設置されている。チップ１３０の主面には複数のボンディングパッド１３２があり、複数の電気接続素子１６０（例えばワイヤボンディング方式で形成したボンディングワイヤ）が用いられて貫通スロット１１５を通過し、ボンディングパッド１３２群と基板１１０のインナーフィンガー１１６群とが接続されることによって、チップ１３０と基板１１０とは電気的に相互接続される。また、一つの封止体１７０はトランスファーモールディング方式で基板１１０の実装表面１１１と貫通スロット１１５の内とに設置され、チップ１３０と電気接続素子１６０群とを密封している。   The chip 130 is placed on the substrate 110 through a die attaching adhesive 120 formed on the mounting surface 111 of the substrate 110. The main surface of the chip 130 has a plurality of bonding pads 132, and a plurality of electrical connection elements 160 (for example, bonding wires formed by a wire bonding method) are used to pass through the through slots 115, and the bonding pad 132 group and the substrate 110. When the inner fingers 116 are connected to each other, the chip 130 and the substrate 110 are electrically connected to each other. One sealing body 170 is installed on the mounting surface 111 of the substrate 110 and the inside of the through slot 115 by a transfer molding method, and seals the chip 130 and the group of electrical connection elements 160.

第一列外接球接点１４０群は基板１１０の露出表面１１２にある外接パッド１１８群に設置される。第二列外接球接点１５０群は基板１１０の露出表面１１２にある外接パッド１１８群に設置される。しかし、第二列外接球接点１５０群は、第一列外接球接点１４０群と比較して貫通スロット１１５から遠くに位置するので、第一列外接球接点１４０群よりも中心点との距離が長くなって基板１１０の周縁や隅部に隣接して応力集中領域となってしまう。   The first row circumscribed ball contacts 140 are placed on circumscribed pads 118 on the exposed surface 112 of the substrate 110. The second row circumscribed ball contacts 150 are placed on circumscribed pads 118 on the exposed surface 112 of the substrate 110. However, since the second row circumscribed ball contact 150 group is located farther from the through slot 115 than the first row circumscribed ball contact 140 group, the distance from the center point is larger than the first row circumscribed ball contact 140 group. It becomes long and becomes a stress concentration region adjacent to the peripheral edge or corner of the substrate 110.

上述したダイアタッチング接着材１２０の硬化、封止体１７０の硬化、第一列外接球接点１４０群及び第二列外接球接点１５０群のリフロー接合、後続の熱サイクル試験及び実際の製品運算などは加熱処理を提供し、材料間の熱膨張係数が異なるために発生する熱応力と墜落試験による衝撃応力とを第二列外接球接点１５０群に直接印加すると、第二列外接球接点１５０群の断裂や落下を起し電気接続の品質の悪化に影響する。また、基板１１０は反り変形が起き易く、チップ１３０の側辺の角１３１に隣接する一部の外接球接点１４０、１５０群も断裂や落下の問題がある。なお、ダイアタッチング過程において、温度の上昇と圧力の印加とによってダイアタッチング接着材１２０は流動的であり溢れ或いは登る現象を容易に発生する。   Curing of the above-mentioned die attaching adhesive 120, curing of the sealing body 170, reflow bonding of the first row circumscribed ball contact 140 group and the second row circumscribed ball contact 150 group, the subsequent thermal cycle test and actual product calculation, etc. When heat treatment is provided and thermal stress generated due to different thermal expansion coefficients between materials and impact stress by a crash test are directly applied to the second row circumscribed ball contact 150 group, Rupture or fall will affect the quality of the electrical connection. Further, the substrate 110 is likely to warp, and some circumscribed ball contacts 140 and 150 adjacent to the corners 131 on the side of the chip 130 have a problem of tearing or dropping. In the die attaching process, the die attaching adhesive 120 is fluid and easily overflows or climbs due to an increase in temperature and application of pressure.

本発明の主な目的は外接球接点の移動変化による増益効果がある半導体パッケージを提供することである。このような半導体パッケージにおいて、製品の外観、寸法と厚み及び外接球の接合面に影響せずにダイアタッチング接着材の厚みをチップの周縁に接近すればするほど厚くすると、チップの中心線に遠く位置する外接球接点はチップと比較して移動変化による増益効果を相対的に大きく生じさせることができるので、半導体パッケージの周縁や隅部にある外接球接点は従来より大きい応力に耐えられ、断裂や落下などの現象が発生しないようになる。   A main object of the present invention is to provide a semiconductor package having an effect of increasing profit due to a change in movement of a circumscribed ball contact. In such a semiconductor package, if the thickness of the die-attaching adhesive is made closer to the periphery of the chip without affecting the appearance, dimensions and thickness of the product and the joint surface of the circumscribed sphere, the distance from the center line of the chip The circumscribed ball contacts located on the periphery of the semiconductor package can withstand a greater stress than conventional chips, because the effect of increasing the movement due to the change in movement can be relatively large compared to the chip. Phenomenon such as falling or falling will not occur.

本発明のもう一つの目的は外接球接点の移動変化による増益効果がある半導体パッケージを提供することである。このような半導体パッケージにおいて、チップの側辺の角にもっと厚いダイアタッチング接着材を提供することで、チップの側辺の角から外接球接点に印加する応力作用を減少させ外接球接点の断裂を避けることができる。
本発明の更にもう一つの目的は外接球接点の移動変化による増益効果がある一種の半導体パッケージを提供することである。このような半導体パッケージにおいて、基板の梯形溝をダイアタッチング接着材の収容空間として利用することができるため、ダイアタッチング接着材の溢れを制御する。 Another object of the present invention is to provide a semiconductor package having an effect of increasing profits due to a change in movement of a circumscribed ball contact. In such a semiconductor package, by providing a thicker die-attaching adhesive at the corner of the chip, the stress applied to the circumscribed ball contact from the corner of the chip is reduced, and the circumscribed ball contact is broken. Can be avoided.
Still another object of the present invention is to provide a kind of semiconductor package which has an effect of increasing profits due to the movement change of the circumscribed ball contact. In such a semiconductor package, since the trapezoidal groove of the substrate can be used as a housing space for the die attaching adhesive, the overflow of the die attaching adhesive is controlled.

上述目的を達成するために本発明では、次に述べる技術が提案されている。本発明に係る半導体パッケージは、一つの基板、一つのダイアタッチング接着材、一つのチップ、複数の第一列外接球接点及び複数の第二列外接球接点を備える。基板は一つの実装表面と一つの露出表面とを有し、実装表面には一つのダイアタッチング領域を有しかつダイアタッチング接着材を形成して、ダイアタッチング領域にチップの照準を合わせダイアタッチング接着材を介してチップを基板の実装表面に設置させる。第一列外接球接点は基板の露出表面に設置され、第二列外接球接点も基板の露出表面に設置されるが、第一列外接球接点と比較してダイアタッチング領域の中心線から遠くに位置している。また、基板は更に少なくとも一つの梯形溝を有し、この梯形溝が実装表面に形成されることにより、この梯形溝内にある基板の厚みはダイアタッチング領域の中心線から遠ざかる方向に向かって階段のように漸次薄くなっている。なお、ダイアタッチング接着材を梯形溝内に充填させる。 In order to achieve the above object, the following technique is proposed in the present invention. The semiconductor package according to the present invention includes one substrate, one die attach adhesive, one chip, a plurality of first row circumscribed ball contacts, and a plurality of second row circumscribed ball contacts. The substrate has one mounting surface and one exposed surface. The mounting surface has one die attach area and a die attach adhesive is formed so that the chip is aimed at the die attach area and die attach adhesive. The chip is placed on the mounting surface of the substrate through the material. The first column circumscribed sphere contact points are disposed on the exposed surface of the substrate, the second column circumscribed sphere Proximity is also installed on the exposed surface of the substrate, the center of the die-attaching area compared to the first row circumscribed sphere Proximity Located far from the line. Further, the substrate further has at least one trapezoidal groove, and the trapezoidal groove is formed on the mounting surface, whereby the thickness of the substrate in the trapezoidal groove is stepped in a direction away from the center line of the die attachment region. It becomes thinner gradually. A die attaching adhesive is filled in the trapezoidal groove.

また、梯形溝の領域内に第二列外接球接点の照準を合わせてもよい。
また、第二列外接球接点は梯形溝の対称になる両平行周縁に隣接してもよい。
また、第二列外接球接点は梯形溝の周辺に隣接してもよい。
また、梯形溝により、基板は第一列外接球接点と第二列外接球接点との上にそれぞれ一つの第一基板厚みと一つの第二基板厚みとを有し、第二基板厚みは第一基板厚みよりも厚さが薄くなってもよい。 It may also be aimed for the second column circumscribed sphere contact point territory region of trapezoidal grooves.
The second column circumscribed sphere contact point may be adjacent to both parallel peripheral become symmetrical trapezoidal groove.
The second column circumscribed sphere contact point may be adjacent the periphery of the trapezoidal groove.
Further, the trapezoidal groove, the substrate and a second substrate thickness of one and one of the first substrate thickness, respectively on the first row circumscribed sphere contact point and the second column circumscribed sphere contact point, the second substrate thickness May be thinner than the first substrate thickness.

また、チップはダイアタッチング接着材と接触する一つの側辺の角を有してもよく、この側辺の角は第二列外接球接点の配列方向と略平行になり、かつ梯形溝はダイアタッチング領域の外にありかつ側辺の角と平行する一つの周縁を有する。
また、側辺の角と第二列外接球接点との間のダイアタッチング接着材は基板よりも厚さが厚くなる。 The chip may have a corner of one of the sides in contact with the die-attaching adhesive, the corners of the sides becomes substantially parallel to the direction of arrangement of the second row circumscribed sphere contact point and trapezoidal groove It has one perimeter that is outside the die attach area and parallel to the corners of the side.
Also, die-attaching adhesive between the corner and the second column circumscribed sphere Proximity sides has a thickness thicker than the substrate.

また、更にチップと基板との電気接続用とする複数の電気接続素子を備えてもよい。
また、電気接続素子は複数のボンディングワイヤを有してもよい。
また、基板は一つの貫通スロットを有してもよく、この貫通スロットは実装表面と露出表面とを貫通して電気接続素子を通過させる。
また、更に基板の実装表面上と貫通スロット内とに形成した一つの封止体を備えてもよい。 Further, a plurality of electrical connection elements for electrical connection between the chip and the substrate may be provided.
The electrical connection element may have a plurality of bonding wires.
Further, the substrate may have a single through-slot, the through slot passing electrical connection element through the mounting surface and the exposed surface.
Further, a single sealing body formed on the mounting surface of the substrate and in the through slot may be provided.

また、更にチップの上に背中合わせに積層される一つの第二チップを有してもよい。
また、基板は複数のインナーフィンガーを有してもよく、そのインナーフィンガーは実装表面上及び梯形溝の外に形成される。
また、ダイアタッチング接着材をチップの一つの主面に貼付してもよい。
また、ダイアタッチング接着材をチップの一つの背面に貼付してもよい。 Moreover, you may have one 2nd chip | tip laminated | stacked back to back on a chip | tip further.
Further, the substrate may have a plurality of inner fingers, the inner finger over are formed on the outer on the mounting surface and trapezoidal grooves.
Moreover, you may affix a die-attaching adhesive material to one main surface of a chip | tip.
Moreover, you may affix a die-attaching adhesive material on one back surface of a chip | tip.

（第１実施形態）
本発明の第１実施形態による半導体パッケージを図２と図３に示す。半導体パッケージ２００は主に一つの基板２１０、一つのダイアタッチング接着材２２０、一つのチップ２３０、複数の第一列外接球接点２４０及び複数の第二列外接球接点２５０を備える。
基板２１０は一つの実装表面２１１、一つの露出表面２１２及び一つの貫通スロット２１５を有し、実装表面２１１にはチップ２３０と略同一寸法の一つのダイアタッチング領域２１３（図４参照）を有する。 (First embodiment)
A semiconductor package according to the first embodiment of the present invention is shown in FIGS. The semiconductor package 200 mainly includes one substrate 210, one die attach adhesive 220, one chip 230, a plurality of first row circumscribed ball contacts 240, and a plurality of second row circumscribed ball contacts 250.
The substrate 210 has one mounting surface 211, one exposed surface 212, and one through slot 215, and the mounting surface 211 has one die attach region 213 (see FIG. 4) having substantially the same dimensions as the chip 230.

第二列外接球接点２５０群はダイアタッチング領域２１３の中心線と平行するように配列され、かつ第一列外接球接点２４０群と比較して中心線から遠くに位置している。本実施形態において、上述の中心線はおよそチップ２３０のボンディングパッド２３２に位置している。
基板２１０の実装表面２１１と露出表面２１２とを貫通した貫通スロット２１５はウインドウ型ＢＧＡパッケージのワイヤボンディング窓口として使用される。基板２１０は更に露出表面２１２にある複数の外接パッド２１８と複数のインナーフィンガー２１６とを有し、外接パッド２１８群は多列配置やグリッドアレイ形態になってもよい。また、基板２１０の露出表面２１２には一つの半田マスク層２１７を形成し、この半田マスク層２１７は導線を被覆するが、後続に導電素子、例えばボンディングワイヤや半田ボールとの接合用になるインナーフィンガー２１６群と外接パッド２１８群とを露出させる。なお、基板２１０のコストを低下するため、単層配線を有するプリント回路基板を基板２１０にすれば好ましい。 The second row circumscribing ball contact 250 group is arranged to be parallel to the center line of the die attachment region 213 and is located farther from the center line than the first row circumscribed ball contact 240 group. In the present embodiment, the above-described center line is located approximately at the bonding pad 232 of the chip 230.
The through slot 215 that penetrates the mounting surface 211 and the exposed surface 212 of the substrate 210 is used as a wire bonding window of the window type BGA package. The substrate 210 further includes a plurality of circumscribed pads 218 and a plurality of inner fingers 216 on the exposed surface 212, and the circumscribed pads 218 may be arranged in a multi-row arrangement or a grid array. In addition, a single solder mask layer 217 is formed on the exposed surface 212 of the substrate 210, and this solder mask layer 217 covers the conductive wire, but the inner layer is subsequently joined to a conductive element such as a bonding wire or a solder ball. The finger 216 group and the circumscribed pad 218 group are exposed. Note that a printed circuit board having a single-layer wiring is preferably used as the board 210 in order to reduce the cost of the board 210.

また、図２及び図５に示すように、基板２１０は更に実装表面２１１に形成される少なくとも一つの梯形溝２１４を有し、この梯形溝２１４内にある基板２１０の厚さはチップ２３０の中心線から遠ざかる方向に向かって階段のように漸次薄くなって行く。梯形溝２１４は異なる寸法の開口を有する多数のサブー基板を積層することにより形成されている。なお、本発明では梯形溝の数量を制限せず、本実施形態において、基板２１０の両辺にそれぞれ一個の梯形溝２１４を形成している。   2 and 5, the substrate 210 further has at least one trapezoidal groove 214 formed on the mounting surface 211, and the thickness of the substrate 210 within the trapezoidal groove 214 is the center of the chip 230. It gradually becomes thinner like a staircase in the direction away from the line. The trapezoidal groove 214 is formed by stacking a number of sub-substrates having openings of different sizes. In the present invention, the number of trapezoidal grooves is not limited. In the present embodiment, one trapezoidal groove 214 is formed on each side of the substrate 210.

ダイアタッチング接着材２２０は、基板２１０の実装表面２１１に形成され、材料として液体エポキシ、Ｂ‐ステージ接着剤或は他にマルチステージ硬化可能のダイアタッチング部材を任意に採用してもよく、かつチップ実装過程の前或は前半作業中に基板２１０の上にダイアタッチング接着材２２０を予め形成することができ、形成方法としてドロップコディング或は印刷などの液体塗布がある。   The die attaching adhesive 220 is formed on the mounting surface 211 of the substrate 210, and a liquid epoxy, B-stage adhesive or other multi-stage curable die attaching member may be arbitrarily adopted as a material, and a chip. The die attach adhesive 220 can be formed in advance on the substrate 210 before or during the first half of the mounting process, and a liquid coating method such as drop coding or printing can be used as a forming method.

また、図３及び図４に示すように、ダイアタッチング領域２１３にチップ２３０の照準を合わせ、かつダイアタッチング接着材２２０を介してチップ２３０を基板２１０の実装表面２１１上に設置する。本実施形態において、チップ２３０は主面にある複数のボンディングパッド２３２を有し、ボンディングパッド２３２群は単列か二列で主面の中央区域に並んでいる。ダイアタッチング接着材２２０をチップ２３０の主面に貼付し、かつ、貫通スロット２１５の内にボンディングパッド２３２群の照準を合わせる。   Further, as shown in FIGS. 3 and 4, the chip 230 is aimed at the die attaching region 213, and the chip 230 is placed on the mounting surface 211 of the substrate 210 through the die attaching adhesive 220. In this embodiment, the chip 230 has a plurality of bonding pads 232 on the main surface, and the bonding pad 232 group is arranged in a central area of the main surface in a single row or two rows. A die attaching adhesive 220 is attached to the main surface of the chip 230, and the bonding pad 232 group is aimed in the through slot 215.

また、再び図３及び図４に示すように、チップ２３０はダイアタッチング接着材２２０と接触する一つの側辺の角２３１を有し、この側辺の角２３１は第二列外接球接点２５０群の配列方向と略平行している。梯形溝２１４は一つの周縁２１４Ａを有し、この周縁２１４Ａはダイアタッチング領域２１３の外に位置して側辺の角２３１と平行することにより、側辺の角２３１と第二列外接球接点２５０群との間にあるダイアタッチング接着材２２０の厚みを厚くすることができるので、チップ２３０の側辺の角２３１から第二列外接球接点２５０群に印加する応力作用が軽減される。 3 and 4, the chip 230 has one side corner 231 that contacts the die attach adhesive 220, and the side corner 231 is the second row circumscribed ball contact 250 group. It is substantially parallel to the arrangement direction. The trapezoidal groove 214 has one peripheral edge 214A, and the peripheral edge 214A is located outside the die attaching region 213 and parallel to the side corner 231 so that the side edge 231 and the second row circumscribed ball contact 250 Since the thickness of the die-attaching adhesive 220 between the groups can be increased, the stress action applied to the second row circumscribed ball contact 250 group from the side corner 231 of the chip 230 is reduced.

図２及び図４に示すように、第一列外接球接点２４０群は基板２１０の露出表面２１２にある外接パッド２１８群に設置され、第二列外接球接点２５０群も基板２１０の露出表面２１２にある外接パッド２１８群に設置されるが、第一列外接球接点２４０群と比較してダイアタッチング領域２１３の中心線から遠くに位置している。即ち、基板２１０の中心線からの距離や中心点からの距離（ＤＮＰ、Distance from Neutral Point）により、外接球接点群を複数の第一列外接球接点２４０と複数の第二列外接球接点２５０に分けることが可能となり、ここで、断面構造において第二列外接球接点２５０群は第一列外接球接点２４０よりも基板２１０の中心点から遠くに位置している。具体的に言えば、第一列外接球接点２４０群と第二列外接球接点２５０群とは金属ボール、ソルダペースト（solder paste）、接触パッド或は接触ピンを含む。よって、半導体パッケージ２００は第一列外接球接点２４０群と第二列外接球接点２５０群とを介して外部のプリント回路基板（図示せず）と接合することができる。なお、第一列外接球接点２４０群と第二列外接球接点２５０群との間に一列や多列の外接球接点を設置してもよい。   As shown in FIGS. 2 and 4, the first row of circumscribed ball contacts 240 are disposed on the circumscribed pad 218 group on the exposed surface 212 of the substrate 210, and the second row of circumscribed ball contacts 250 are also exposed on the exposed surface 212 of the substrate 210. However, it is located farther from the center line of the die attachment region 213 than the first row circumscribed ball contact 240 group. That is, according to the distance from the center line of the substrate 210 and the distance from the center point (DNP, Distance from Neutral Point), the circumscribed ball contact group is divided into a plurality of first row circumscribed ball contacts 240 and a plurality of second row circumscribed ball contacts 250. Here, in the cross-sectional structure, the second row circumscribed ball contact 250 group is located farther from the center point of the substrate 210 than the first row circumscribed ball contact 240. Specifically, the first row circumscribed ball contact 240 group and the second row circumscribed contact 250 group include metal balls, solder paste, contact pads or contact pins. Therefore, the semiconductor package 200 can be joined to an external printed circuit board (not shown) via the first row circumscribed ball contact 240 group and the second row circumscribed ball contact 250 group. Note that one or more rows of circumscribed ball contacts may be installed between the first row circumscribed ball contacts 240 group and the second row circumscribed ball contacts 250 group.

具体的に言えば、図５に示すように、基板２１０は基板厚みＳ０を有し、この基板厚みＳ０は実際に実装表面２１１と露出表面２１２との間の距離である。また、梯形溝２１４を介して、第一列外接球接点２４０群の上と梯形溝２１４との間にある基板２１０は第一基板厚みＳ１を有し、第二列外接球接点２５０群の上と梯形溝２１４との間にある基板２１０は第二基板厚みＳ２を有し、ここで、第二基板厚みＳ２は第一基板厚みＳ１より薄くなってもよく、第一基板厚みＳ１は基板厚みＳ０より薄くなってもよい。半田マスク層２１７、ダイアタッチング接着材２２０及び封止体の膨張係数により、第一基板厚みＳ１と第二基板厚みＳ２とを適当な厚さに調整することができるので、温度変化による基板の反り変形を防止することができる。具体的に言えば、梯形溝２１４の領域内に第二列外接球接点２５０群の照準を合わせることが可能であるとともに、第二列外接球接点２５０群は梯形溝２１４の対称になる両平行周縁２１４Ａに隣接することができる。そのために、第二列外接球接点２５０群からチップ２３０までの最短距離において、ダイアタッチング接着材２２０に占められる比率を比較的に多く確保することができ、基板２１０の占め率よりも多くなる。また、第二列外接球接点２５０群を梯形溝２１４の周辺に隣接させることはこのましく、これにより、第二列外接球接点２５０群の上にあるダイアタッチング接着材２２０は比較的に厚くなることで応力緩和効率を向上させ、集中作用を受け易い第二列外接球接点２５０群は大きい移動変化に耐えることができ、断裂や落下などの不具合が起きない。 More specifically, as shown in FIG. 5, the substrate 210 has a substrate thickness S0, which is actually the distance between the mounting surface 211 and the exposed surface 212. In addition, the substrate 210 between the trapezoidal groove 214 and the first row circumscribed ball contact 240 group via the trapezoidal groove 214 has a first substrate thickness S1, and the second row circumscribed ball contact 250 group upper And the trapezoidal groove 214 has a second substrate thickness S2, where the second substrate thickness S2 may be less than the first substrate thickness S1, and the first substrate thickness S1 is the substrate thickness. It may be thinner than S0. The first substrate thickness S1 and the second substrate thickness S2 can be adjusted to appropriate thicknesses according to the expansion coefficient of the solder mask layer 217, the die attach adhesive 220, and the sealing body. Deformation can be prevented. Specifically, with it is possible to aim the second column circumscribed sphere contacts 250 groups territory region trapezoidal groove 214, the second column circumscribed sphere contacts 250 group both parallel to be symmetrical trapezoidal groove 214 Adjacent to the periphery 214A. Therefore, a relatively large proportion of the die attach adhesive 220 can be secured at the shortest distance from the second row circumscribed ball contact 250 group to the chip 230, which is larger than the substrate 210. In addition, it is preferable that the second row circumscribed ball contact 250 group is adjacent to the periphery of the trapezoidal groove 214, so that the die attach adhesive 220 on the second row circumscribed contact 250 group is relatively thick. As a result, the stress relaxation efficiency is improved, and the second row circumscribed ball contact 250 group, which is easily subjected to a concentration action, can withstand a large movement change, and does not suffer from problems such as tearing and dropping.

図３及び図４に示すように、ダイアタッチング作業を行う時、基板２１０の実装表面２１１に液体塗布方式でダイアタッチング接着材２２０を塗布してチップ２３０の貼付用とする。なお、梯形溝２１４はダイアタッチング領域２１３に隣接することによってダイアタッチング接着材２２０の収容空間として利用されて溢れによる汚染を減少することが可能である。それゆえ、ダイアタッチング接着材２２０が基板２１０へ向かって溢れ流れることを制限する功能がある梯形溝２１４は、適当にダイアタッチング接着材２２０の溢れを制御することができる。図３に示すように、ダイアタッチング接着材２２０は、基板２１０の周辺と貫通スロット２１５の内とに溢れ流れなくなり、かつ、チップ２３０の側面での登る高さを更に低くすることができるので、封止体２７０によりダイアタッチング接着材２２０の完全密封を促進して半導体パッケージ２００の品質を確保している。   As shown in FIG. 3 and FIG. 4, when performing a die attaching operation, a die attaching adhesive 220 is applied to the mounting surface 211 of the substrate 210 by a liquid application method to attach the chip 230. The trapezoidal groove 214 is adjacent to the die attaching region 213 so that it can be used as a housing space for the die attaching adhesive 220 to reduce contamination due to overflow. Therefore, the trapezoidal groove 214, which serves to limit the overflow of the die attach adhesive 220 toward the substrate 210, can appropriately control the overflow of the die attach adhesive 220. As shown in FIG. 3, the die attaching adhesive 220 does not flow over the periphery of the substrate 210 and the inside of the through slot 215, and can further increase the climbing height on the side surface of the chip 230. The sealing body 270 promotes complete sealing of the die attaching adhesive 220 to ensure the quality of the semiconductor package 200.

具体的に言えば、図３に示すように、ダイアタッチング接着材２２０は実際に梯形溝２１４に充填され、側辺の角２３１と第二列外接球接点２５０群との間にあるダイアタッチング接着材２２０の厚みは、側辺の角２３１と第二列外接球接点２５０群との間にある基板２１０の厚みよりも厚くなる。そのため、製品の外観、寸法と厚み及び外接球の接合面に影響せずに、ダイアタッチング接着材２２０の厚みはチップ２３０の周縁に接近すればするほど厚くなって、ダイアタッチング領域２１３の中心から遠くに位置する第二列外接球接点２５０群はチップ２３０と比較して移動変化による増益効果が相対的に大きく生じるため、半導体パッケージ２００の周縁や隅部にある第二列外接球接点２５０群は従来より大きい応力を耐えられ、断裂や落下などの現象が発生しなくなる。   Specifically, as shown in FIG. 3, the die attach adhesive 220 is actually filled in the trapezoidal groove 214, and the die attach adhesive located between the side corner 231 and the second row circumscribed ball contact 250 group. The thickness of the material 220 is greater than the thickness of the substrate 210 between the side corner 231 and the second row circumscribed ball contact 250 group. Therefore, without affecting the appearance, dimensions and thickness of the product, and the joint surface of the circumscribed sphere, the thickness of the die attaching adhesive 220 becomes thicker as it approaches the periphery of the chip 230, and from the center of the die attaching area 213. The second row circumscribed ball contact 250 group located far away has a relatively large profit increase effect due to the movement change as compared with the chip 230, so the second row circumscribed ball contact 250 group at the periphery or corner of the semiconductor package 200. Can withstand more stress than before, and phenomena such as tearing and dropping do not occur.

本実施例形態において、図２に示すように、基板２１０のインナーフィンガー２１６群は露出表面２１１に形成されて貫通スロット２１５と隣接している。半導体パッケージ２００は更に複数の電気接続素子２６０を備え、この電気接続素子２６０群はチップ２３０のボンディングパッド２３２群と基板２１０のインナーフィンガー２１６群との電気接続に利用され、ワイヤボンディング方式で形成したボンディングワイヤを使用してもよい。   In this embodiment, as shown in FIG. 2, the group of inner fingers 216 of the substrate 210 is formed on the exposed surface 211 and is adjacent to the through slot 215. The semiconductor package 200 further includes a plurality of electrical connection elements 260, which are used for electrical connection between the bonding pads 232 of the chip 230 and the inner fingers 216 of the substrate 210, and are formed by a wire bonding method. Bonding wires may be used.

半導体パッケージ２００は更に一つの封止体２７０を備え、この封止体２７０は、基板２１０の実装表面２１１上と貫通スロット２１５の内とに形成され、チップ２３０と電気接続素子２６０群とを汚染させないように外部と隔離して密封している。本実施形態において、封止体２７０はトランスファーモールディング方式で形成されてチップ２３０と電気接続素子２６０群とを完全密封している。或は、他の実施形態において、封止体２７０はチップ２３０の側面のみを密封してチップ２３０の背面を露出させる場合もあり、これはベアチップ（bare chip）形態（図示せず）である。   The semiconductor package 200 further includes one sealing body 270, which is formed on the mounting surface 211 of the substrate 210 and in the through slot 215, and contaminates the chip 230 and the electrical connection element 260 group. It is sealed and isolated from the outside so as not to let it go. In this embodiment, the sealing body 270 is formed by a transfer molding method and completely seals the chip 230 and the electrical connection element 260 group. Alternatively, in another embodiment, the encapsulant 270 may seal only the side surface of the chip 230 to expose the back surface of the chip 230, which is in the form of a bare chip (not shown).

（第２実施形態）
本発明の第２実施形態による半導体パッケージは、背中合わせデュアルダイパッケージのウインドウ型ボールグリッドアレイパッケージ（back-to-back dual die package window BGA package）製品に運用されることができ、そして、第１実施形態と同様な主要素子を持つため、ここでは同じ図号を使用して説明して行く。例えば、図６に示す半導体パッケージは、基板２１０、ダイアタッチング接着材２２０、第一チップ２３０、第一列外接球接点２４０群及び第二列外接球接点２５０群を備える。上述半導体パッケージは更に一つの第二チップ２８０を備え、この第二チップ２８０は背中合わせ第一チップ２３０の背面上に積層される。しかし、制限せずより多いチップ、例えば二個、三個或はもっと多いチップを積層可能でマルチチップ積層パッケージの構成となって効果的に運転できる。具体的に言うと、第二チップ２８０の主面には複数の第二ボンディングパッド２８１を有し、複数の第二電気接続素子２９０（例えば、ワイヤボンディング方式で形成したボンディングワイヤ）を介して第二ボンディングパッド２８１群と基板２１０の実装表面２１１にある複数の第二インナーフィンガー２１９とを接続することより、第二チップ２８０と基板２１０との電気相互接続ができる。また、半田マスク層２１７、ダイアタッチング接着材２２０及び封止体２７０の膨張係数と全体の実装高さにより、梯形溝２１４の厚さと数量を適当に調整することができるので、温度変化による基板２１０の反り変形を防止することができる。梯形溝２１４の領域内に第二列外接球接点２５０群の照準を合わせることより優れた応力緩和性が得られ、実際の製品運算や熱サイクル試験の進行中に第二列外接球接点２５０群は断裂や接合不良などの不具合を発生させず、半導体パッケージの電気接続品質と耐用性を確保可能となる。 (Second Embodiment)
The semiconductor package according to the second embodiment of the present invention can be used in a back-to-back dual die package window BGA package product, and the first implementation. Since the main element is similar to the form, the same symbol is used here for explanation. For example, the semiconductor package shown in FIG. 6 includes a substrate 210, a die attach adhesive 220, a first chip 230, a first row circumscribed ball contact 240 group, and a second row circumscribed ball contact 250 group. The semiconductor package further includes one second chip 280, which is stacked on the back surface of the back-to-back first chip 230. However, without limitation, more chips, for example, two, three or more chips can be stacked, and the multi-chip stacked package configuration can be operated effectively. Specifically, the main surface of the second chip 280 has a plurality of second bonding pads 281, and the second chip 280 has a plurality of second electrical connection elements 290 (for example, bonding wires formed by a wire bonding method) through the second chip 280. By connecting the two bonding pads 281 and the plurality of second inner fingers 219 on the mounting surface 211 of the substrate 210, the second chip 280 and the substrate 210 can be electrically interconnected. In addition, the thickness and quantity of the trapezoidal groove 214 can be appropriately adjusted according to the expansion coefficients of the solder mask layer 217, the die attach adhesive 220, and the sealing body 270 and the overall mounting height. It is possible to prevent warping deformation. Excellent stress relaxation properties than that aim the second column circumscribed sphere contacts 250 group obtained territory region trapezoidal groove 214, the actual product mathematical operation and the second column circumscribed sphere contacts 250 groups during the course of the heat cycle test Does not cause defects such as tearing or poor bonding, and can ensure the electrical connection quality and durability of the semiconductor package.

（第３実施形態）
本発明の第３実施形態による半導体パッケージは、図７に示すように、主要に一つの基板３１０、一つのダイアタッチング接着材３２０、一つのチップ３３０、複数の第一列外接球接点３４０及び複数の第二列外接球接点３５０を備える。基板３１０は一つの実装表面３１１と一つの露出表面３１２とを有し、実装表面３１１には一つのダイアタッチング領域３１３（図８参照）を有し、ダイアタッチング領域３１３の寸法はチップ３３０と略一致する。基板３１０の露出表面３１２に一つの半田マスク層３１７を形成し、この半田マスク層３１７は絶縁性材料を用い、導線を被覆する一つの電気絶縁層として形成されるが、第一列外接球接点３４０群と第二列外接球接点３５０群とが複数の外接パッド３１８と接合できるように外接パッド３１８群を露出させる。また、図７に示すように、基板３１０は更に少なくとも一つの梯形溝３１４を有し、この梯形溝３１４は実装表面３１１に形成されることによって、梯形溝３１４の内にある基板３１０の厚みはダイアタッチング領域３１３の中心点から遠ざかる方向に向かって階段のように漸次薄くなって行く。図８に示すように、梯形溝３１４はダイアタッチング領域３１３よりも寸法が少し大きくなる。本実施形態において、基板３１０は更に複数のインナーフィンガー３１６を有し、図８に示すように、インナーフィンガー３１６群は実装表面３１１上に形成されて梯形溝３１４の外に位置している。 (Third embodiment)
As shown in FIG. 7, the semiconductor package according to the third embodiment of the present invention mainly includes one substrate 310, one die attach adhesive 320, one chip 330, a plurality of first row circumscribed ball contacts 340, and a plurality of contacts. The second row circumscribed ball contact 350 is provided. The substrate 310 has one mounting surface 311 and one exposed surface 312, and the mounting surface 311 has one die attach region 313 (see FIG. 8). The size of the die attach region 313 is substantially the same as that of the chip 330. Match. A solder mask layer 317 is formed on the exposed surface 312 of the substrate 310, and this solder mask layer 317 is formed of an insulating material and is formed as a single electrically insulating layer covering the conductive wire. The circumscribed pad 318 group is exposed so that the 340 group and the second row circumscribed ball contact 350 group can be joined to the plurality of circumscribed pads 318. Further, as shown in FIG. 7, the substrate 310 further has at least one trapezoidal groove 314, and the trapezoidal groove 314 is formed on the mounting surface 311, so that the thickness of the substrate 310 in the trapezoidal groove 314 is as follows. It gradually becomes thinner like a staircase in a direction away from the center point of the die attaching region 313. As shown in FIG. 8, the trapezoidal groove 314 is slightly larger in size than the die attaching region 313. In the present embodiment, the substrate 310 further includes a plurality of inner fingers 316, and the group of inner fingers 316 is formed on the mounting surface 311 and positioned outside the trapezoidal groove 314 as shown in FIG.

図７に示すように、ダイアタッチング接着材３２０は、基板３１０の実装表面３１１に形成され、一般に液体エポキシ、Ｂ‐ステージ接着剤或は加熱して液体や稠密体のダイアタッチング材を使用してよいが、Ｂ‐ステージ接着剤を使用すれば好ましい。なお、ダイアタッチング接着材３２０を半導体チップ実装作業の前或は前半に予め基板３１０の上に形成することができる。   As shown in FIG. 7, the die attach adhesive 320 is formed on the mounting surface 311 of the substrate 310, and generally uses liquid epoxy, B-stage adhesive, or heated liquid or dense die attach material. Although it is good, it is preferable to use a B-stage adhesive. The die attaching adhesive 320 can be formed on the substrate 310 in advance before or during the semiconductor chip mounting operation.

ダイアタッチング領域３１３にチップ３３０の照準を合わせ、そして、ダイアタッチング接着材３２０を介してチップ３３０を基板３１０の実装表面３１１に設置させる。本実施形態においては、チップ３３０の一つの背面にダイアタッチング接着材３２０を貼付している。チップ３３０の主面は複数のボンディングパッド３３２を有し、このボンディングパッド３３２群は主面の周辺区域に単列や多列で並んで複数の電気接続素子３６０（例えばボンディングワイヤ）を介して基板３１０のインナーフィンガー３１６群と電気接続される。その上に、再び一つの封止体３７０を用いチップ３３０と電気接続素子３６０群とを適当に保護するように密封している。また、梯形溝３１４は、インナーフィンガー３１６群の汚染を避けるため実装表面３１１上に溢れるダイアタッチング接着材３２０の制御ができ、かつ封止体３７０によってダイアタッチング接着材３２０の完全密封ができる。   The chip 330 is aimed at the die attaching region 313, and the chip 330 is placed on the mounting surface 311 of the substrate 310 through the die attaching adhesive 320. In the present embodiment, a die attaching adhesive 320 is attached to one back surface of the chip 330. The main surface of the chip 330 has a plurality of bonding pads 332, and the group of bonding pads 332 is arranged in a single row or multiple rows in the peripheral area of the main surface through a plurality of electrical connection elements 360 (for example, bonding wires). It is electrically connected to the 310 inner fingers 316 group. In addition, a single sealing body 370 is used again to seal the chip 330 and the electrical connection element 360 group appropriately. Further, the trapezoidal groove 314 can control the die attaching adhesive 320 overflowing on the mounting surface 311 in order to avoid contamination of the inner fingers 316 group, and the die attaching adhesive 320 can be completely sealed by the sealing body 370.

再び図７に示すように、第一列外接球接点３４０群は基板３１０上の露出表面３１２中央に接近する部分の外接パッド３１８に設置され、第二列外接球接点３５０群は基板３１０上の露出表面３１２中央から遠い部分の外接パッド３１８に設置され、第二列外接球接点３５０群は第一列外接球接点３４０群と比較してダイアタッチング領域３１３の中心線から遠くに位置し、即ち、第二列外接球接点３５０群は第一列外接球接点３４０群よりも基板３１０の中心点から更に遠く位置している。基板３１０の半田マスク層３１７により梯形溝３１４の数量と溝の深さは設けられる。また、第二列外接球接点３５０群の落球や断裂に起因する基板３１０の反り変形を防止するようにダイアタッチング接着材３２０と封止体３７０との膨張係数を適当に調整している。   As shown in FIG. 7 again, the first row of circumscribed ball contacts 340 are disposed on the circumscribed pad 318 at a portion approaching the center of the exposed surface 312 on the substrate 310, and the second row of circumscribed contacts 350 are arranged on the substrate 310. The second row circumscribed ball contact 350 group is located farther from the center line of the die attach area 313 than the first row circumscribed ball contact 340 group. The second row circumscribed ball contact 350 group is located farther from the center point of the substrate 310 than the first row circumscribed contact 340 group. The solder mask layer 317 of the substrate 310 provides the number of trapezoidal grooves 314 and the depth of the grooves. Further, the expansion coefficient of the die attaching adhesive 320 and the sealing body 370 is appropriately adjusted so as to prevent the warp deformation of the substrate 310 due to falling balls or tearing of the second row circumscribed ball contact 350 group.

再び図７に示すように、チップ３３０はダイアタッチング接着材３２０と接触する一つの側辺の角３３１を有すれば好ましく、この側辺の角３３１は第二列外接球接点３５０群の配列方向と略平行になる。図７及び図８に示すように、梯形溝３１４はダイアタッチング領域３１３の外にありかつ側辺の角３３１と平行する一つの周縁３１４Ａを有し、この周縁３１４Ａにより、側辺の角３３１と第二列外接球接点３５０群との間にあるダイアタッチング接着材３２０の厚みを厚くすることができるので、チップ３３０の側辺の角３３１から第二列外接球接点３５０群に印加する応力作用が軽減される。 As shown in FIG. 7 again, it is preferable that the chip 330 has one side corner 331 that contacts the die attach adhesive 320, and this side corner 331 is the arrangement direction of the second row circumscribed ball contact 350 group. And become almost parallel. As shown in FIGS. 7 and 8, the trapezoidal groove 314 has one peripheral edge 314A that is outside the die attaching region 313 and parallel to the side corner 331, and the peripheral edge 314A causes the side corner 331 and Since the thickness of the die-attaching adhesive 320 between the second row circumscribed ball contacts 350 group can be increased, the stress action applied to the second row circumscribed ball contacts 350 group from the corner 331 on the side of the chip 330. Is reduced.

また、ダイアタッチング接着材３２０が基板３１０へ向かって溢れ流れることを制限する功能がある梯形溝３１４は、ダイアタッチング接着材３２０が基板３１０の側辺（図７参照）へ溢れ流れないように適当に制御することができ、半導体パッケージ３００の品質を確保している。
以上、本発明をその好適な実施例に基づいて説明したが、本発明の保護範囲は特許請求範囲で限定されて、この保護範囲を基準にして、本発明の精神と範囲内に触れるどんな変更や修正も本発明の保護範囲に属する。 In addition, the trapezoidal groove 314 that is effective in limiting the overflow of the die attaching adhesive 320 toward the substrate 310 is suitable for preventing the die attaching adhesive 320 from overflowing to the side of the substrate 310 (see FIG. 7). Therefore, the quality of the semiconductor package 300 is ensured.
Although the present invention has been described based on the preferred embodiments thereof, the scope of protection of the present invention is limited by the scope of claims, and any modification that comes within the spirit and scope of the present invention based on this scope of protection. And modifications also belong to the protection scope of the present invention.

周知の半導体パッケージを示す断面図である。It is sectional drawing which shows a known semiconductor package. 本発明の第１実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by 1st Embodiment of this invention. 本発明の第１実施形態による半導体パッケージの一部を示す断面図である。It is sectional drawing which shows a part of semiconductor package by 1st Embodiment of this invention. 本発明の第１実施形態による半導体パッケージの基板を示す平面図である。It is a top view which shows the board | substrate of the semiconductor package by 1st Embodiment of this invention. 本発明の第１実施形態による半導体パッケージの基板の一部を示す一部切欠き斜視図である。1 is a partially cutaway perspective view showing a part of a substrate of a semiconductor package according to a first embodiment of the present invention. 本発明の第２実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by 2nd Embodiment of this invention. 本発明の第３実施形態による半導体パッケージを示す断面図である。It is sectional drawing which shows the semiconductor package by 3rd Embodiment of this invention. 本発明の第３実施形態による半導体パッケージの基板を示す斜視図である。It is a perspective view which shows the board | substrate of the semiconductor package by 3rd Embodiment of this invention.

符号の説明Explanation of symbols

Ｓ０：基板厚み、Ｓ１：第一基板厚み、Ｓ２：第二基板厚み、２００：半導体パッケージ、２１０：基板、２１１：実装表面、２１２：露出表面、２１３：ダイアタッチング領域、２１４：梯形溝、２１５：貫通スロット、２１６：インナーフィンガー、２１７：半田マスク層、２１８：外接パッド、２１９：第二インナーフィンガー、２２０：ダイアタッチング接着材、２３０：チップ、２３１：側辺の角、２４０：第一列外接球接点、２５０：第二列外接球接点、２６０：電気接続素子、２７０：封止体、２８０：第二チップ、２８１：ボンディングパッド、２９０：第二電気接続素子、３００：半導体パッケージ、３１０：基板、３１１：実装表面、３１２：露出表面、３１３：ダイアタッチング領域、３１４：梯形溝、３１４Ａ：周縁、３１６：インナーフィンガー、３１７：半田マスク層、３１８：外接パッド、３２０：ダイアタッチング接着材、３３０：チップ、３３１：側辺の角、３３２：ボンディングパッド、３４０：第一列外接球接点、３５０：第二列外接球接点、３６０：電気接続素子、３７０：封止体   S0: substrate thickness, S1: first substrate thickness, S2: second substrate thickness, 200: semiconductor package, 210: substrate, 211: mounting surface, 212: exposed surface, 213: die attach area, 214: trapezoidal groove, 215 : Through slot, 216: inner finger, 217: solder mask layer, 218: circumscribed pad, 219: second inner finger, 220: die attaching adhesive, 230: chip, 231: side corner, 240: first row Circumscribed ball contact, 250: second row circumscribed ball contact, 260: electrical connection element, 270: sealing body, 280: second chip, 281: bonding pad, 290: second electrical connection element, 300: semiconductor package, 310 : Substrate, 311: mounting surface, 312: exposed surface, 313: die attaching region, 314: trapezoidal groove, 314A: circumference 316: inner finger, 317: solder mask layer, 318: circumscribing pad, 320: die attach adhesive, 330: chip, 331: side corner, 332: bonding pad, 340: first row circumscribed ball contact, 350 : Second row circumscribed ball contact, 360: Electrical connection element, 370: Sealed body

Claims (17)

一つの実装表面と一つの露出表面とを有し、前記実装表面は一つのダイアタッチング領域を有する一つの基板と、
前記基板の前記実装表面に形成される一つのダイアタッチング接着材と、
照準を前記ダイアタッチング領域に合わせ、かつ前記ダイアタッチング接着材を介して前記基板の前記実装表面上に設置される一つのチップと、
前記基板の前記露出表面に設置され、外部の回路基板に電気接続することの可能な複数の第一列外接球接点と、
前記基板の前記露出表面に設置され、複数の前記第一列外接球接点と比較して前記ダイアタッチング領域の中心線から遠くに位置し、外部の回路基板に電気接続することの可能な複数の第二列外接球接点と、
前記基板の前記実装表面に形成される梯形溝であって、前記梯形溝内にある前記基板の厚みは前記ダイアタッチング領域の中心線から遠ざかる方向に向かって階段のように漸次薄くなっており、かつ内に前記ダイアタッチング接着材が充填される少なくとも一つの前記梯形溝と、
を備え、
前記梯形溝の領域内に複数の前記第二列外接球接点の照準を合わせることを特徴とする半導体パッケージ。 One mounting surface and one exposed surface, the mounting surface having one die attach region, and one substrate,
One die attach adhesive formed on the mounting surface of the substrate;
One chip that is positioned on the mounting surface of the substrate with the aiming at the die attach area and via the die attach adhesive;
A plurality of first row circumscribed ball contacts installed on the exposed surface of the substrate and capable of being electrically connected to an external circuit board ;
Placed on the exposed surface of the substrate, as compared to the plurality of the first row circumscribed sphere Proximity located farther from the center line of the die-attaching region, a plurality possible be electrically connected to an external circuit board A second row of circumscribed ball contacts,
A trapezoidal groove formed on the mounting surface of the substrate, and the thickness of the substrate in the trapezoidal groove is gradually reduced like a staircase in a direction away from the center line of the die attaching region; And at least one of the trapezoidal grooves filled with the die attaching adhesive,
With
Semiconductor package, characterized in that aim the plurality of the second column circumscribed sphere contact point territory region of the trapezoidal groove. 複数の前記第二列外接球接点は前記梯形溝の対称となる両平行周縁に隣接していることを特徴とする請求項１に記載の半導体パッケージ。 The semiconductor package of claim 1, a plurality of the second column circumscribed sphere contact points, characterized in that adjacent to both parallel peripheral which are symmetrical of the trapezoidal groove. 前記梯形溝により、前記基板は複数の前記第一列外接球接点と複数の前記第二列外接球接点との上にそれぞれ一つの第一基板厚みと一つの第二基板厚みとを有し、前記第二基板厚みは前記第一基板厚みよりも厚さが薄いことを特徴とする請求項１に記載の半導体パッケージ。 By the trapezoidal groove, the substrate is perforated and a second substrate thickness of one and one of the first substrate thickness, respectively on the plurality of the first row circumscribed sphere contact point and a plurality of the second column circumscribed sphere Proximity The semiconductor package according to claim 1, wherein the thickness of the second substrate is smaller than the thickness of the first substrate. 前記チップは前記ダイアタッチング接着材と接触する一つの側辺の角を有し、前記側辺の角は複数の前記第二列外接球接点の配列方向と略平行となり、かつ前記梯形溝は前記ダイアタッチング領域の外にありかつ前記側辺の角と平行する一つの周縁を有することを特徴とする請求項１に記載の半導体パッケージ。 The chip has a corner of one of the sides in contact with the die-attaching adhesive, corners of the side edges become substantially parallel to the array direction of the plurality of the second column circumscribed sphere contact point, and the trapezoidal groove The semiconductor package according to claim 1, wherein the semiconductor package has one peripheral edge that is outside the die attaching region and is parallel to a corner of the side edge. 前記側辺の角と複数の前記第二列外接球接点との間の前記ダイアタッチング接着材は基板よりも厚さが厚くなることを特徴とする請求項４に記載の半導体パッケージ。 The semiconductor package of claim 4 wherein the die-attaching adhesive material, characterized in that the thickness than the substrate becomes thicker between the corners and the plurality of the second column circumscribed sphere contact point of the side edge. 更に前記チップと前記基板との電気接続用とする複数の電気接続素子を備えることを特徴とする請求項１に記載の半導体パッケージ。   The semiconductor package according to claim 1, further comprising a plurality of electrical connection elements for electrical connection between the chip and the substrate. 前記ダイアタッチング接着材を前記チップの一つの主面に貼付し、前記基板は一つの貫通スロットを有し、前記貫通スロットは前記実装表面と前記露出表面とを貫通して複数の前記電気接続素子を通過させることを特徴とする請求項１に記載の半導体パッケージ。 The die-attaching adhesive is attached to one main surface of the chip, the substrate has one through slot, and the through slot penetrates the mounting surface and the exposed surface, and a plurality of the electrical connection elements. The semiconductor package according to claim 1, wherein the child is passed. 更に前記基板の前記実装表面上と前記貫通スロット内に形成された一つの封止体を備えることを特徴とする請求項７に記載の半導体パッケージ。   The semiconductor package according to claim 7, further comprising a sealing body formed on the mounting surface of the substrate and in the through slot. 更に前記チップの上に背中合わせ積層される一つの第二チップを有し、前記基板は複数のインナーフィンガーを有し、複数の前記インナーフィンガーは前記実装表面上及び前記梯形溝の外に形成されることを特徴とする請求項７に記載の半導体パッケージ。 Further comprising a one second chip which are back-to-back stacked on the chip, the substrate has a plurality of inner fingers, the plurality of the inner finger over is formed outside the mounting surface and the trapezoidal groove The semiconductor package according to claim 7. 前記ダイアタッチング接着材を前記チップの一つの背面に貼付し、前記基板は複数のインナーフィンガーを有し、複数の前記インナーフィンガーは前記実装表面上及び前記梯形溝の外に形成されることを特徴とする請求項１に記載の半導体パッケージ。 Sticking the die-attaching adhesive to the back of one of the chip, the substrate has a plurality of inner fingers, the plurality of the inner fingers over which is formed on the outside of the mounting surface and the trapezoidal groove The semiconductor package according to claim 1, wherein: 一つの実装表面と一つの露出表面とを有し、前記実装表面は一つのダイアタッチング領域を有する一つの基板と、
前記基板の前記実装表面に形成される一つのダイアタッチング接着材と、
照準をダイアタッチング領域に合わせ、かつ前記ダイアタッチング接着材を介して前記基板の前記実装表面上に設置される一つのチップと、
前記基板の前記露出表面に設置され、外部の回路基板に電気接続することの可能な複数の外接球接点と、
前記基板の前記実装表面に形成される梯形溝であって、前記梯形溝内にある前記基板の厚みは前記ダイアタッチング領域の中心線から遠ざかる方向に向かって階段のように漸次薄くなっており、かつ内に前記ダイアタッチング接着材が充填される少なくとも一つの前記梯形溝と、
前記チップに設けられ、前記ダイアタッチング接着材と接触し、複数の前記外接球接点の配列方向と略平行する一つの側辺の角と、
前記梯形溝に設けられ、ダイアタッチング領域の外にあり、前記側辺の角と平行する一つの周縁と、
を備え、
前記梯形溝の領域内に複数の前記外接球接点の照準を合わせることを特徴とする半導体パッケージ。 One mounting surface and one exposed surface, the mounting surface having one die attach region, and one substrate,
One die attach adhesive formed on the mounting surface of the substrate;
A chip that is positioned on the mounting surface of the substrate with the aiming at the die attach area and via the die attach adhesive;
A plurality of circumscribed ball contacts installed on the exposed surface of the substrate and capable of being electrically connected to an external circuit board ;
A trapezoidal groove formed on the mounting surface of the substrate, and the thickness of the substrate in the trapezoidal groove is gradually reduced like a staircase in a direction away from the center line of the die attaching region; And at least one of the trapezoidal grooves filled with the die attaching adhesive,
Provided in the chip, in contact with the die-attaching adhesive, a corner of one side edge substantially parallel to the arrangement direction of the plurality of the circumscribed sphere contact point,
One circumferential edge provided in the trapezoidal groove, outside the die attach region, and parallel to the corner of the side;
With
Semiconductor package, characterized in that to combining the sight of the plurality of the circumscribed sphere contact point territory region of the trapezoidal groove. 前記側辺の角と複数の前記外接球接点との間の前記ダイアタッチング接着材は基板よりも厚さが厚くなることを特徴とする請求項１１に記載の半導体パッケージ。 The semiconductor package of claim 11 wherein the die-attaching adhesive material, characterized in that the thickness than the substrate becomes thicker between the corners and the plurality of the circumscribed sphere contact point of the side edge. 更に前記チップと前記基板との電気接続用とする複数の電気接続素子を備えることを特徴とする請求項１１に記載の半導体パッケージ。   The semiconductor package according to claim 11, further comprising a plurality of electrical connection elements for electrical connection between the chip and the substrate. 前記ダイアタッチング接着材を前記チップの一つの主面に貼付し、前記基板は一つの貫通スロットを有し、前記貫通スロットは前記実装表面と前記露出表面とを貫通して複数の前記電気接続素子の通過をさせることを特徴とする請求項１３に記載の半導体パッケージ。 The die-attaching adhesive is attached to one main surface of the chip, the substrate has one through slot, and the through slot penetrates the mounting surface and the exposed surface, and a plurality of the electrical connection elements. The semiconductor package according to claim 13 , wherein the child is allowed to pass therethrough. 更に前記基板の前記実装表面上と前記貫通スロット内に形成された一つの封止体を備えることを特徴とする請求項１４に記載の半導体パッケージ。 The semiconductor package according to claim 14 , further comprising a sealing body formed on the mounting surface of the substrate and in the through slot. 更に前記チップの上に背中合わせ積層される一つの第二チップを有し、前記基板は複数のインナーフィンガーを有し、複数の前記インナーフィンガーは前記実装表面上及び前記梯形溝の外に形成されることを特徴とする請求項１４に記載の半導体パッケージ。 Further comprising a one second chip which are back-to-back stacked on the chip, the substrate has a plurality of inner fingers, the plurality of the inner finger over is formed outside the mounting surface and the trapezoidal groove The semiconductor package according to claim 14 . 前記ダイアタッチング接着材を前記チップの一つの背面に貼付し、前記基板は複数のインナーフィンガーを有し、複数の前記インナーフィンガーは前記実装表面上及び前記梯形溝の外に形成されることを特徴とする請求項１１に記載の半導体パッケージ。 Sticking the die-attaching adhesive to the back of one of the chip, the substrate has a plurality of inner fingers, the plurality of the inner fingers over which is formed on the outside of the mounting surface and the trapezoidal groove The semiconductor package according to claim 11, wherein
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