JPS60171733A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS60171733A
JPS60171733A JP59027095A JP2709584A JPS60171733A JP S60171733 A JPS60171733 A JP S60171733A JP 59027095 A JP59027095 A JP 59027095A JP 2709584 A JP2709584 A JP 2709584A JP S60171733 A JPS60171733 A JP S60171733A
Authority
JP
Japan
Prior art keywords
tab
pellet
leads
semiconductor
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59027095A
Other languages
Japanese (ja)
Other versions
JPH0546098B2 (en
Inventor
Kazunari Suzuki
一成 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP59027095A priority Critical patent/JPS60171733A/en
Publication of JPS60171733A publication Critical patent/JPS60171733A/en
Publication of JPH0546098B2 publication Critical patent/JPH0546098B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29005—Structure
    • H01L2224/29007—Layer connector smaller than the underlying bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To enable a large-sized semiconductor pellet to be packaged without deteriorating the mechanical strength, by providing a smaller tab than conventional ones and elongating inner leads so that the semiconductor pellet is mounted on the tab and the tips of the inner leads. CONSTITUTION:A tab 2 carrying a semiconductor pellet 11 is supported by tab suspension leads 6. A lead frame 7 is composed of the tab 2, the tab suspension leads 6, inner leads 4, outer leads 8 and frames 9. In this case, the tab 2 is minituarized while the inner leads are elongated by that much. Therefore, the inner leads can be buried deep in the resin sealing material, whereby the mechanical strength of the leads is improved. Thus, a semiconductor device with high reliability can be obtained.

Description

【発明の詳細な説明】 〔技術分野〕 本発明は半導体装置に関し、特に、新規なペレット付構
造を有する樹脂封止型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a semiconductor device, and particularly to a resin-sealed semiconductor device having a novel pellet-attached structure.

〔背景技術〕[Background technology]

従来の半導体フラスチックパッケージは、リードフレー
ムのタブに半導体ベレット（チンプ）をマウントし、こ
の半導体ベレットとリードフレームのリードとをコネク
タワイヤによりワイヤボンディングし、樹脂封止を行う
構造のものが一般的であった。Conventional semiconductor plastic packages generally have a structure in which a semiconductor bullet (chimp) is mounted on the tab of a lead frame, the semiconductor bullet and the leads of the lead frame are wire-bonded using connector wire, and then resin-sealed. Met.

しかし、半導体ベレットは増々大形化する傾向にあり、
小さいプラスチックパッケージ内に大ベレットを収納せ
ざるを得ない。このような小パッケージに大ベレットを
収納するパッケージ構造では、樹脂封止されたリード部
分（インナーリード）が短くなり、機械的強度の点で問
題を生じてきた。However, semiconductor pellets tend to become larger and larger.
I have no choice but to store a large pellet inside a small plastic package. In such a package structure in which a large pellet is housed in a small package, the resin-sealed lead portion (inner lead) becomes short, causing a problem in terms of mechanical strength.

〔発明の目的〕[Purpose of the invention]

本発明は、大型の半導体ベレットを実装することができ
、機械的強度を低減させることなく、むしろ機械的強度
を向上させた半導体装置を提供することにある。An object of the present invention is to provide a semiconductor device that can be mounted with a large semiconductor pellet and has improved mechanical strength rather than reduced mechanical strength.

本発明の前記ならびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

〔発明の概要〕[Summary of the invention]

本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.

すなわち、タブを従来のものより小さくし、かつインナ
ーリード部分を長くして半導体ぺｌ／フットタブおよび
インナーリードの先端部分にマウントすることにより、
上記目的を達成するものである。That is, by making the tab smaller than the conventional one and making the inner lead part longer and mounting it on the tip of the semiconductor Pel/foot tab and the inner lead,
This aims to achieve the above objectives.

〔実施例〕〔Example〕

以下、本発明の実施例を図面罠従い説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第１図はＤ　Ｉ　Ｐ　（Ｄｕａｌ　Ｉｎ　−Ｌｉｎｅ　
Ｉ’ａｃｋａｇｅ　）タイプの半導体プラスチックパッ
ケージの断面図、第２図はリードフレームの平面図であ
り、本発明による半導体装置は、その半導体ベレット１
がタブ２上に接合材料３により固着（マウント）されて
いるほか、インナーリード４上に絶縁層５を介して固着
（マウント）されている。すなわち、本発明半導体装置
はこのようなペレット付構造を有してなる。Figure 1 shows DIP (Dual In-Line)
FIG. 2 is a plan view of a lead frame, and the semiconductor device according to the present invention has a semiconductor pellet 1 of the semiconductor device according to the present invention.
is fixed (mounted) on the tab 2 with the bonding material 3, and is also fixed (mounted) on the inner lead 4 via the insulating layer 5. That is, the semiconductor device of the present invention has such a pellet-attached structure.

上記半導体ベレット１はたとえばシリコン単結晶基板か
ら構成さ第１、周知の技術によって、このベレット内に
は多数の回路素子が形成され、１つの回路機能を与えて
いる。回路素子はたとえば絶縁ゲート型電界効果トラン
ジスタ（ＭＯＳ）ランジスタ）からなり、これらの回路
素子によって、たとえば論理回路およびメモリ回路機能
が形成されている。The semiconductor pellet 1 is made of, for example, a silicon single crystal substrate. A large number of circuit elements are formed within the pellet by well-known techniques to provide one circuit function. The circuit elements consist of, for example, insulated gate field effect transistors (MOS) transistors, which form, for example, logic circuit and memory circuit functions.

第２図に示すように、半導体ベレット１を搭載している
タブ２はタブ吊りリード６により支持さ−れており、リ
ードフレーム７はこのタブ２、タブ吊りリード６、イン
ナーリード４、アウターリード８およびフレーム枠９よ
り構成される。As shown in FIG. 2, the tab 2 on which the semiconductor pellet 1 is mounted is supported by the tab suspension lead 6, and the lead frame 7 consists of the tab 2, the tab suspension lead 6, the inner lead 4, and the outer lead. 8 and a frame frame 9.

当該リート：フレームはたとえば４２アロイ合金などの
金属材料により構成される。The REIT/frame is made of a metal material such as a 42 alloy.

半導体ベレット１をタブ２上に回着させる接合材料３に
は、Ａ　ｕ　／　Ｓ　ｉ共晶、ハンダ、Ａｇペースト等
の樹脂接着材等が使用できる。但しＡｕ／Ｓｉ共晶、ハ
ンダ、Ａｇペースト等で、ベレットｌとタブ２間の導電
性をとる必要がある場合、あらかじめベレット１の裏面
周辺、あるいはインナーリード４の先端に絶縁層５を形
成しておかねばならない。ベレット１とタブ２間に導電
性が必要ない場合、絶縁層５は接合材料３と同じ、例え
ばポリイミド又はエポキシ樹脂あるいは絶縁性ベースト
などの絶縁性接着材を用い、ペレット付けと同時に形成
させることもできる。あるいは従来半導体ペレットａ面
の酸化膜を除去してから、ペレット付けをおこなってい
るが、この酸化膜を残しておくなど、何らかの絶縁処理
を施し【おくこともよい。The bonding material 3 for rotating the semiconductor pellet 1 onto the tab 2 may be a resin adhesive such as Au/Si eutectic, solder, or Ag paste. However, if it is necessary to provide electrical conductivity between the pellet 1 and the tab 2 using Au/Si eutectic, solder, Ag paste, etc., an insulating layer 5 should be formed in advance around the back surface of the pellet 1 or at the tip of the inner lead 4. I have to keep it. If electrical conductivity is not required between the pellet 1 and the tab 2, the insulating layer 5 may be formed at the same time as the pellet is attached using the same insulating adhesive as the bonding material 3, for example, polyimide, epoxy resin, or insulating base. can. Alternatively, although the oxide film on the a-side of the semiconductor pellet has conventionally been removed before pellet attachment, it is also possible to perform some kind of insulation treatment, such as leaving this oxide film.

半導体素子１をタブ２およびインナーリード４上にマウ
ント後、第１図に示すように、半導体索子１の電極（バ
ット）１０に、たとえばＡｕ腺で構成さｉするコネクタ
ワイヤエ１の端部を接続し、コネクタワイヤ１１の他端
部をインナーリード４土に接続し、半導体素子１からの
＆号をインナーリード４および外部リード８を通して外
部に導出する。After mounting the semiconductor element 1 on the tab 2 and the inner lead 4, as shown in FIG. The other end of the connector wire 11 is connected to the inner lead 4, and the & sign from the semiconductor element 1 is led out through the inner lead 4 and the outer lead 8.

このようなワイヤボンディング後、トランスファーモー
ルドなどにより樹脂封止を行い、樹脂封止体１２を形成
する。ここに使用される樹脂にはたとえばエポキシ樹脂
があげられる。After such wire bonding, resin sealing is performed by transfer molding or the like to form a resin sealing body 12. Examples of resins used here include epoxy resins.

〔効果〕〔effect〕

（１）　タブを小さくし、その分インナーリードを長（
したので、インナーリードが樹脂封正体中深く埋め込ま
れ、したがって従来インナーリードが大ベレットの搭載
に従い増々短くなる傾向にあり、リードの機械強度が問
題となっていたがこれを解消できた。すなわち、高信頼
度の半導体装置を提供できた。(1) Make the tab smaller and make the inner lead longer (
As a result, the inner leads are deeply embedded in the resin sealing body, and this has solved the problem of the mechanical strength of the leads, which conventionally had a tendency to become shorter as larger pellets were mounted. In other words, a highly reliable semiconductor device could be provided.

（２）半導体素子をタブおよびインナーリードに搭載し
た構造と成したので大口径の半導体ベレットにあっても
、実装可能と成すことができる。(2) Since the semiconductor element is mounted on the tab and the inner lead, it can be mounted even on a large diameter semiconductor pellet.

（３Ｆ　タブを省略して半導体ペレｙ）をリード上に固
着してなる半導体装置よりもタブを有している分生導体
ベレットの放熱性がよく、またペレット付の作業性も良
く、さらにボンディング作業もし易くなった。The heat dissipation of a distributed conductor pellet with a tab is better than that of a semiconductor device formed by fixing a 3F (semiconductor pellet with the tab omitted) on a lead, and the workability of attaching the pellet is also good, and bonding Work has become easier.

以上本発明者圧よってｈされた発明を実施例にもとすき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で神々変更可
能であることはいうまでもない。たとえば半導体ベレッ
トとリードとの接続は、上述のワイヤボンディングの他
に、フェイスタウン方式にてベレットの各電極をリード
に直接的に固定することも可能である。Although the invention developed by the present inventor has been specifically explained using examples, the present invention is not limited to the above-mentioned examples, and can be modified without departing from the gist thereof. Needless to say. For example, to connect the semiconductor pellet and the lead, in addition to the wire bonding described above, it is also possible to directly fix each electrode of the pellet to the lead using a face town method.

〔利用分野］ 以上の説明では主として本発明者によってなされた発明
をその背景となった利用分野であるＤＩＬのプラスチッ
クスタイブバ、ケージについて適用した例を示したが、
フラー／ドパツクタイプパッケージやサーディツプタイ
プパッケージなどについても適用することができる。[Field of Application] In the above explanation, an example was mainly given in which the invention made by the present inventor is applied to DIL's plastic stub bar and cage, which is the field of application that formed the background of the invention.
It can also be applied to fuller/dippack type packages, cerdip type packages, etc.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本発明の実施例を示す断面図、第２図は、本
発明の実施例を示す平面図である。 １・・・半導体ベレット、２・・・タブ、３・・・接合
材料、４・・・インナーリード、５・・・絶縁（処理）
層、６・・・タブ吊りリード、７・・・リードフレーム
、８・・・アウターリード、９・・・フレーム枠、１０
・・・電極（パッド）、１１・・・コネクタワイヤ、１
２・・・樹脂封止体。 第　２　図FIG. 1 is a sectional view showing an embodiment of the invention, and FIG. 2 is a plan view showing an embodiment of the invention. 1... Semiconductor pellet, 2... Tab, 3... Bonding material, 4... Inner lead, 5... Insulation (processing)
layer, 6... tab suspension lead, 7... lead frame, 8... outer lead, 9... frame frame, 10
... Electrode (pad), 11 ... Connector wire, 1
2...Resin sealing body. Figure 2

Claims (1)

【特許請求の範囲】[Claims] １、半導体ベレットをリードフレームのタブおよびイン
ナーリード先端部に搭載してなるペレット付構造を有す
る半導体装置。1. A semiconductor device having a pellet-attached structure in which a semiconductor pellet is mounted on the tab of a lead frame and the tip of an inner lead.
JP59027095A 1984-02-17 1984-02-17 Semiconductor device Granted JPS60171733A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59027095A JPS60171733A (en) 1984-02-17 1984-02-17 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59027095A JPS60171733A (en) 1984-02-17 1984-02-17 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS60171733A true JPS60171733A (en) 1985-09-05
JPH0546098B2 JPH0546098B2 (en) 1993-07-13

Family

ID=12211518

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59027095A Granted JPS60171733A (en) 1984-02-17 1984-02-17 Semiconductor device

Country Status (1)

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JP (1) JPS60171733A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6366941A (en) * 1986-09-08 1988-03-25 Mitsubishi Electric Corp Semiconductor device
JPS6348618U (en) * 1986-09-19 1988-04-02
JPS6457566A (en) * 1987-08-26 1989-03-03 Matsushita Electric Ind Co Ltd Thermobattery
US4868635A (en) * 1988-01-13 1989-09-19 Texas Instruments Incorporated Lead frame for integrated circuit
US4943843A (en) * 1985-03-25 1990-07-24 Hitachi, Ltd. Semiconductor device
US5550402A (en) * 1992-11-27 1996-08-27 Esec Sempac S.A. Electronic module of extra-thin construction
WO2000068993A1 (en) * 1999-05-07 2000-11-16 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
KR20010008823A (en) * 1999-07-05 2001-02-05 이중구 BLP package

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57114261A (en) * 1981-01-07 1982-07-16 Hitachi Ltd Lead frame structure
JPS5811247U (en) * 1981-07-13 1983-01-25 三菱電機株式会社 semiconductor equipment

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5811247B2 (en) * 1979-10-09 1983-03-02 三菱油化株式会社 gas mixing device

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57114261A (en) * 1981-01-07 1982-07-16 Hitachi Ltd Lead frame structure
JPS5811247U (en) * 1981-07-13 1983-01-25 三菱電機株式会社 semiconductor equipment

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4943843A (en) * 1985-03-25 1990-07-24 Hitachi, Ltd. Semiconductor device
US5126821A (en) * 1985-03-25 1992-06-30 Hitachi, Ltd. Semiconductor device having inner leads extending over a surface of a semiconductor pellet
JPS6366941A (en) * 1986-09-08 1988-03-25 Mitsubishi Electric Corp Semiconductor device
JPS6348618U (en) * 1986-09-19 1988-04-02
JPS6457566A (en) * 1987-08-26 1989-03-03 Matsushita Electric Ind Co Ltd Thermobattery
US4868635A (en) * 1988-01-13 1989-09-19 Texas Instruments Incorporated Lead frame for integrated circuit
US5550402A (en) * 1992-11-27 1996-08-27 Esec Sempac S.A. Electronic module of extra-thin construction
WO2000068993A1 (en) * 1999-05-07 2000-11-16 Maxim Integrated Products, Inc. Semiconductor devices with improved lead frame structures
KR20010008823A (en) * 1999-07-05 2001-02-05 이중구 BLP package

Also Published As

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JPH0546098B2 (en) 1993-07-13

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