JPH0334912Y2 - - Google Patents
Info
- Publication number
- JPH0334912Y2 JPH0334912Y2 JP1984035771U JP3577184U JPH0334912Y2 JP H0334912 Y2 JPH0334912 Y2 JP H0334912Y2 JP 1984035771 U JP1984035771 U JP 1984035771U JP 3577184 U JP3577184 U JP 3577184U JP H0334912 Y2 JPH0334912 Y2 JP H0334912Y2
- Authority
- JP
- Japan
- Prior art keywords
- bed
- resin
- back surface
- conductive layer
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 14
- 229920005989 resin Polymers 0.000 claims description 9
- 239000011347 resin Substances 0.000 claims description 9
- 238000000465 moulding Methods 0.000 claims description 2
- 238000007789 sealing Methods 0.000 claims 2
- 239000000853 adhesive Substances 0.000 claims 1
- 230000001070 adhesive effect Effects 0.000 claims 1
- 239000003822 epoxy resin Substances 0.000 description 5
- 229920000647 polyepoxide Polymers 0.000 description 5
- 239000000463 material Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910003271 Ni-Fe Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】
〔考案の技術分野〕
本考案は、メモリーチツプ等の半導体チツプを
マウントしたリードフレームを、樹脂モールド部
材で封止した樹脂封止型半導体装置に係り、特に
熱変化に伴う樹脂モールド部材の亀裂を防止しう
る樹脂封止型半導体装置に関する。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a resin-sealed semiconductor device in which a lead frame on which a semiconductor chip such as a memory chip is mounted is sealed with a resin molding member. The present invention relates to a resin-sealed semiconductor device that can prevent cracks in a resin molded member.
従来、DIP（dual inline package）の樹脂封止
型半導体装置として、例えば第１図ａ，ｂのよう
なものがある。この半導体装置は、板状のベツド
１ａとこのベツド１ａの周囲に離間して配置され
たリード１ｂとを有するリードフレーム１と、ボ
ンデイングパツド（チツプ電極端子）を有しベツ
ド１ａの表面にマウントされる大型の半導体チツ
プ２と、この半導体チツプ２のボンデイングパツ
ドとリード１ｂの内方後との間を接続するボンデ
イングワイヤ３と、ベツド１ａ、半導体チツプ
２、ボンデイングワイヤ３及びリード１ｂの内方
部を封止するエポキシ樹脂等の樹脂モールド部材
４とより構成されている。
2. Description of the Related Art Conventionally, as a DIP (dual inline package) resin-sealed semiconductor device, there are devices such as those shown in FIGS. 1a and 1b, for example. This semiconductor device includes a lead frame 1 having a plate-shaped bed 1a and leads 1b arranged at a distance around the bed 1a, and a lead frame 1 having bonding pads (chip electrode terminals) and mounted on the surface of the bed 1a. A large semiconductor chip 2 to be bonded, a bonding wire 3 that connects the bonding pad of the semiconductor chip 2 to the inner rear of the lead 1b, and a bonding wire 3 that connects the bonding pad of the semiconductor chip 2 to the inner rear of the lead 1b. It is comprised of a resin mold member 4 made of epoxy resin or the like that seals the sides.
ここで、リードフレーム１は銅系の材料か、ま
たはNi−Fe合金（例えば、Ni；42％、Fe；57％
等からなる商品名「42Alloy」）等の材料が使用
されている。 Here, the lead frame 1 is made of a copper-based material or a Ni-Fe alloy (for example, Ni: 42%, Fe: 57%).
Materials such as 42Alloy (product name: 42Alloy) are used.
42Alloyは電気的特性や機械的特性等が優れて
いるためリードフレーム１として多く用いられて
いる。しかし42Alloyのリードフレーム１を使用
して大型の半導体チツプ２を小型のDIP内に高分
子材であるエポキシ樹脂を用いて封止すると、
42Alloyとエポキシ樹脂の熱膨張係数αの相異に
より、高温−低温の熱衝撃を与えた場合、モール
ドしたエポキシ樹脂の裏面に、例えば第１図ｂに
示すような亀裂Ａが生じていた。これは42Alloy
の熱膨張係数α42Allpy（＝0.5×10-5）とエポキシ樹
脂の熱膨張係数αモ哀襯票 42Alloy is often used as the lead frame 1 because of its excellent electrical and mechanical properties. However, when a large semiconductor chip 2 is sealed inside a small DIP using a 42Alloy lead frame 1 using epoxy resin, which is a polymeric material,
Due to the difference in thermal expansion coefficient α between 42Alloy and the epoxy resin, cracks A as shown in FIG. 1b, for example, were generated on the back surface of the molded epoxy resin when a high-temperature-low temperature thermal shock was applied. This is 42Alloy
The thermal expansion coefficient α of 42Allpy (=0.5×10 -5 ) and the thermal expansion coefficient α of epoxy resin
Claims (1)
とを有するリードフレームと、 ボンデイングパツドを有し、前記ベツドの表面
上にマウントされる半導体チツプと、 この半導体チツプのボンデイングパツドと前記
リードの内方部との間を接続するボンデイングワ
イヤと、 前記ベツドと半導体チツプとボンデイングワイ
ヤとリードの内方部とを封止する樹脂モールド部
材と、 を具えた樹脂封止型半導体装置において、 前記樹脂モールド部材と前記ベツドのそれぞれ
の熱膨張係数の中間の値の熱膨張係数を有し、前
記封止時に前記樹脂モールド部材によつて一体的
に封止される導電性層が、前記樹脂モールド部材
でおおわれる前記ベツドの裏面と、その裏面とそ
の裏面に対してほぼ直角をなす側面とによつて形
成される外縁綾線部分と、を被うものとして形成
されており、 前記導電性層を前記ベツドの裏面に、前記導電
性層と前記樹脂モールド部材との間のせん断応力
よりも大きい接着力をもつて接着させたことを特
徴とする、樹脂封止型半導体装置。[Claims for Utility Model Registration] A lead frame having a plate-shaped bed, leads arranged at a distance around the bed, and a semiconductor having a bonding pad and mounted on the surface of the bed. a chip; a bonding wire connecting between a bonding pad of the semiconductor chip and the inner part of the lead; a resin molding member sealing the base, the semiconductor chip, the bonding wire, and the inner part of the lead; , a resin molded semiconductor device having a thermal expansion coefficient between the respective coefficients of thermal expansion of the resin mold member and the bed, and which is integrally formed by the resin mold member during the sealing. The conductive layer sealed in the bed includes a back surface of the bed covered with the resin molded member, and an outer edge twill line portion formed by the back surface and a side surface substantially perpendicular to the back surface. The conductive layer is bonded to the back surface of the bed with an adhesive force greater than the shear stress between the conductive layer and the resin molded member. A resin-sealed semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3577184U JPS60149137U (en) | 1984-03-13 | 1984-03-13 | Resin-encapsulated semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3577184U JPS60149137U (en) | 1984-03-13 | 1984-03-13 | Resin-encapsulated semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60149137U JPS60149137U (en) | 1985-10-03 |
| JPH0334912Y2 true JPH0334912Y2 (en) | 1991-07-24 |
Family
ID=30540352
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3577184U Granted JPS60149137U (en) | 1984-03-13 | 1984-03-13 | Resin-encapsulated semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60149137U (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2552158Y2 (en) * | 1992-05-08 | 1997-10-27 | 株式会社三井ハイテック | Lead frame |
| JPH06295970A (en) * | 1993-04-08 | 1994-10-21 | Seiko Epson Corp | Semiconductor device and manufacture of semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5311964B2 (en) * | 1974-10-18 | 1978-04-26 |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5040549Y2 (en) * | 1971-12-07 | 1975-11-19 | ||
| JPS563966Y2 (en) * | 1976-07-12 | 1981-01-28 |
-
1984
- 1984-03-13 JP JP3577184U patent/JPS60149137U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5311964B2 (en) * | 1974-10-18 | 1978-04-26 |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60149137U (en) | 1985-10-03 |
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