JPH02189959A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH02189959A JPH02189959A JP1009036A JP903689A JPH02189959A JP H02189959 A JPH02189959 A JP H02189959A JP 1009036 A JP1009036 A JP 1009036A JP 903689 A JP903689 A JP 903689A JP H02189959 A JPH02189959 A JP H02189959A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- heat sink
- heat
- integrated circuit
- semiconductor integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 239000011347 resin Substances 0.000 claims abstract description 40
- 229920005989 resin Polymers 0.000 claims abstract description 40
- 230000017525 heat dissipation Effects 0.000 claims description 10
- 230000035882 stress Effects 0.000 abstract description 7
- 239000000853 adhesive Substances 0.000 abstract description 5
- 230000001070 adhesive effect Effects 0.000 abstract description 5
- 230000008646 thermal stress Effects 0.000 abstract description 5
- 239000012530 fluid Substances 0.000 abstract description 2
- 239000002184 metal Substances 0.000 description 15
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 239000011345 viscous material Substances 0.000 description 2
- 239000000919 ceramic Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000008602 contraction Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置に関し、特に樹脂により封止さ
れた樹脂封止パッケージタイプの半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a resin-sealed package type semiconductor device sealed with resin.
第２図は従来の半導体装置を示す断面図である。 FIG. 2 is a sectional view showing a conventional semiconductor device.
同図に示される半導体装置の構成を、製造手順に従って
説明すると、まずダイパッド等の放熱用金属板１上に半
導体集積回路チップ２をダイボンディングし、つづいて
金属フレーム３と半導体集積回路チップ２とを電気接続
用ワイＡ７−４によりそれぞれ接続する。その後、放熱
用金属板１上において半導体集積回路デツプ２を、金属
フレーム３の一部とともに樹脂５で覆うように、高温下
で樹脂モールドを行ない、つづいて樹脂５を常温まで冷
２Ｊ１させて固化ざぜ、樹脂５により半導体集積回路チ
ップ２を保護するようにしている。The structure of the semiconductor device shown in the figure will be explained according to the manufacturing procedure. First, a semiconductor integrated circuit chip 2 is die-bonded onto a heat dissipating metal plate 1 such as a die pad, and then a metal frame 3 and a semiconductor integrated circuit chip 2 are bonded together. are connected to each other by electrical connection wire A7-4. Thereafter, resin molding is performed at high temperature so that the semiconductor integrated circuit depth 2 and a part of the metal frame 3 are covered with the resin 5 on the heat dissipation metal plate 1, and then the resin 5 is cooled to room temperature 2J1 and solidified. The semiconductor integrated circuit chip 2 is protected by the resin 5.
この半導体装置において、半導体集積回路デツプ２の動
作によって発生した熱は、放熱用金属板１を伝って半導
体装置外部に放出される。In this semiconductor device, heat generated by the operation of the semiconductor integrated circuit deep 2 is transmitted through the heat dissipation metal plate 1 and released to the outside of the semiconductor device.
しかしながら、従来の半導体装置では、熱膨張係数の異
なる各要素、すなわち放熱用金属板１等の金属と、樹脂
５等のプラスチックと、半導体集積回路デツプ２とが一
体化され、しかも熱膨張係数が非常に異なる放熱用金属
板１と樹脂５とが広い面積で密着しているため、高温下
ぶ樹脂モールドを行なった後冷却していく際に、熱膨張
係数の相違により放熱用金属板１と樹脂５との間に応力
が発生し、半導体装置が反ってしまったり、あるいは半
導体集積回路チップ２が破損してしまう雪、熱ス１〜レ
スに対し信頼性に劣るという問題があつｌこ 。However, in conventional semiconductor devices, elements with different coefficients of thermal expansion, that is, metal such as the heat dissipating metal plate 1, plastic such as the resin 5, and semiconductor integrated circuit depth 2, are integrated. Since the metal plate 1 for heat dissipation and the resin 5, which are very different, are in close contact over a wide area, when the resin is molded at high temperature and then cooled down, the metal plate 1 for heat dissipation There is a problem of poor reliability against snow and heat stains, which can cause stress between the semiconductor device and the resin 5, warping the semiconductor device, or damaging the semiconductor integrated circuit chip 2.
この発明は、上記従来技術の問題を解消し、熱ストレス
に対し十分な信頼性を備え、しかも十分な放熱性を備え
た半導体装置を提供することを［１的とする。An object of the present invention is to solve the problems of the prior art described above, and to provide a semiconductor device having sufficient reliability against thermal stress and sufficient heat dissipation.
上記目的を達成するため、この発明の半導体装置は、一
面に半導体集積回路チップが搭載されたダイボンド板を
、その細面の一領域を除いて前記半導体集積回路チップ
とともに樹脂により月止し、放熱板を、前記ダイボンド
板の前記一領域を覆つ“Ｃ前記樹脂どの間に実質的に隙
間をもたせるように配設するとともに、前記ダイボンド
板の前記一領域ど、その一領域に対応する前記放熱板ど
の間に粘性部材を充填している。In order to achieve the above object, the semiconductor device of the present invention includes a die-bonding plate on which a semiconductor integrated circuit chip is mounted on one side, and a die-bonding plate with a semiconductor integrated circuit chip mounted on one side, except for one area of the narrow side thereof, together with the semiconductor integrated circuit chip, and a heat dissipating plate. are disposed so as to leave a substantial gap between the resin grooves that cover the one area of the die bond plate, and the heat sink corresponding to the one area of the die bond plate. A viscous material is filled between the two.
（作用）
この発明にｊＪ３ Ｌ：Ｊる゛Ｖ導体装置は、樹脂との
間に実質的に隙間をありで放熱板を配設しているため、
両者の熱１１６ｊ張係数の差異に基づく応力の発生が抑
制され、また半導体集積回路チップの動作にＪ：り発生
する熱は、ダイボンド板、粘性部材および放熱板を伝っ
て外部へ効率良く放出される。(Function) Since the jJ3 L:JRUV conductor device of the present invention has a heat sink disposed with a substantial gap between it and the resin,
The generation of stress due to the difference in thermal tensile coefficients between the two is suppressed, and the heat generated due to the operation of the semiconductor integrated circuit chip is efficiently released to the outside through the die bond plate, the viscous member, and the heat sink. Ru.
（実施例）
第１図はこの発明の一実施例である半導体装置を示す断
面図である。同図に示すように、この半導体装置は、装
置本体Ａと、金属製放熱板１１からなる。装置本体Ａに
おいては、金属により構成されるダイボンド板１０の一
面に半導体集積回路チップ１２が搭載されるとともに、
半導体集積回路デツプ１２の図示しない複数のパッド部
が複数の金属ル−ｌ＼１３にそれぞれ電気接続用ワイヤ
１４を介して接続される。また、ダイボンド板１０、半
導体集積回路チップ１２および金属フレム１３の一部を
覆う樹脂１５には、ダイボンド板１０の細面の一領域が
露出するように接続用穴１６が形成されている。(Embodiment) FIG. 1 is a sectional view showing a semiconductor device which is an embodiment of the present invention. As shown in the figure, this semiconductor device consists of a device main body A and a metal heat sink 11. In the device main body A, a semiconductor integrated circuit chip 12 is mounted on one surface of a die bonding plate 10 made of metal, and
A plurality of pad portions (not shown) of the semiconductor integrated circuit deep 12 are connected to a plurality of metal loops 13 via electrical connection wires 14, respectively. Furthermore, a connection hole 16 is formed in the resin 15 covering part of the die bond plate 10, the semiconductor integrated circuit chip 12, and the metal frame 13 so that a region of the narrow surface of the die bond plate 10 is exposed.
一方、放熱板１１には、上記接続用穴１６に対応して接
続用突部１７が一体的に形成されており、この接続用突
部１７の先端とダイボンド板１０の−・領域との間には
、弾性樹脂、流動性樹脂またはゲル状樹脂等からなる粘
性部材１８が充填されている。放熱板１１は、樹脂１５
との間でところどころ部分的に配設された図示しない接
着剤を用いて、樹脂１５との間に実質的に隙間を設（プ
るようにして装置本体Ａに接着されている。On the other hand, a connection protrusion 17 is integrally formed on the heat sink 11 in correspondence with the connection hole 16, and between the tip of the connection protrusion 17 and the - region of the die bonding plate 10. is filled with a viscous member 18 made of elastic resin, fluid resin, gel-like resin, or the like. The heat sink 11 is made of resin 15
The resin 15 is bonded to the device main body A by using an adhesive (not shown) partially disposed here and there between the resin 15 and the resin 15 so as to substantially leave gaps therebetween.
この半導体装置の製造手順は、半導体集積回路チップ１
２をダイボンド板１０にダイボンディングし、半導体集
積回路チップ１２と金属フレーム１３とを電気接続用ワ
イヤー１４により電気的に接続する。次に、半導体集積
回路チップ１２をダイボンド板１０とともにダイボンド
板１０の一領域を除いて樹脂１５により覆われるにうに
、図示しない金型を用いて高温下で樹脂−［−ルドを行
なう。その後、常温まで冷却して樹脂１５を固化さＵで
から、樹脂１５の接続用穴１６内に粘性部材１８を収容
し、放熱板１１の接続用突部１７を接続用穴１６に嵌め
込むにうにして、その放熱板１６を樹脂１５との間でと
ころどころ部分的に配設された図示しない接着剤により
樹脂１５に接着し、こうして半導体装置を製造する。The manufacturing procedure of this semiconductor device is as follows: semiconductor integrated circuit chip 1
2 is die-bonded to a die-bonding plate 10, and the semiconductor integrated circuit chip 12 and metal frame 13 are electrically connected by electrical connection wires 14. Next, the semiconductor integrated circuit chip 12 and the die-bonding plate 10 are resin-molded at a high temperature using a mold (not shown) so that the die-bonding plate 10 is covered with the resin 15 except for one area of the die-bonding plate 10. Thereafter, the resin 15 is solidified by cooling to room temperature, and then the viscous member 18 is accommodated in the connection hole 16 of the resin 15, and the connection protrusion 17 of the heat sink 11 is fitted into the connection hole 16. In this way, the heat dissipation plate 16 is adhered to the resin 15 using an adhesive (not shown) that is partially disposed between the heat dissipation plate 16 and the resin 15, thereby manufacturing a semiconductor device.
この半導体装置によれば、装置本体Ａの樹脂１５と放熱
板１１とが実質的に分離して接続されているため、両者
の熱膨張係数の差異に基づく応力の発生が抑制され、熱
ス］・レスに対し十分な信頼性が１ｑられる１、また、
ダイボンド板１０と放熱板１１との間に粘性部材１８を
充填しているため、半導体集積回路チップ１２の動作に
Ｊ：って生じる熱は、ダイボンド板１０．粘性部材１８
および放熱板１１を伝って外部に効率良く放出され、十
分な放熱性をも備えている。なお、放熱板１１の接続用
突部１７の先端とダイボンド板１０の−・領域どの間隔
を非常に小さく設定し、その隙間に充填される粘性部材
１８に伝熱性の優れたものを用いることにより、放熱効
率を一層向上させることができる。According to this semiconductor device, since the resin 15 of the device main body A and the heat sink 11 are connected to each other while being substantially separated, the generation of stress due to the difference in coefficient of thermal expansion between the two is suppressed, and the heat sink・Sufficient reliability for responses is 1q, and
Since the viscous member 18 is filled between the die bond plate 10 and the heat sink 11, the heat generated by the operation of the semiconductor integrated circuit chip 12 is transferred to the die bond plate 10. Viscous member 18
The heat is efficiently released to the outside through the heat sink 11, and has sufficient heat dissipation. In addition, by setting the distance between the tip of the connecting protrusion 17 of the heat sink 11 and the die bonding plate 10 to be very small, and using a material with excellent heat conductivity as the viscous member 18 filled in the gap, , heat dissipation efficiency can be further improved.
また、ダイボンド板１０ど放熱板１１どの間に粘性部材
１８が充填されているため、例えば半導体装置を実装す
る際に放熱板１１に何等かの外力が加わったとしても、
粘性部材１８の弾性伸縮あるいは流動により上記外力が
吸収され、半導体集積回路デツプ１２に上記外力等、外
部の機械的ストレスが及ぶようなことはない。Furthermore, since the viscous member 18 is filled between the die bond plate 10 and the heat sink 11, even if some external force is applied to the heat sink 11 when mounting a semiconductor device, for example,
The above-mentioned external force is absorbed by the elastic expansion/contraction or flow of the viscous member 18, and no external mechanical stress such as the above-mentioned external force is applied to the semiconductor integrated circuit depth 12.
また、高価なセラミックを使用けず、安価な樹脂１５を
用いながら熱ストレスに対し信頼性の高い半導体装置を
得ることができる。Furthermore, it is possible to obtain a semiconductor device that is highly reliable against thermal stress while using the inexpensive resin 15 without using expensive ceramics.
なお、上記実施例においては、放熱板１１を樹脂１５に
接続する際に、接着剤を用いているが、放熱板１１の接
続方法は接着剤だけに限られず、例えば放熱板１１と樹
脂１５とのそれぞれの対向面にそれぞれ凹凸を形成し、
嵌め込みによって接続するようにしてもよい。要は放熱
板１１と樹脂１５との間に実質的に隙間が形成されるよ
うな接続方法であればどのような方法を用いてもよい。In the above embodiment, adhesive is used to connect the heat sink 11 to the resin 15, but the method of connecting the heat sink 11 is not limited to adhesive. forming unevenness on each opposing surface,
The connection may be made by fitting. In short, any connection method may be used as long as a gap is substantially formed between the heat sink 11 and the resin 15.
以」二のように、この発明の半導体装置によれば、細面
の−・領域を除いてタイボンド−板を樹脂により封止し
、樹脂との間に実質的に隙間をあけて放熱板を接続して
その放熱板とダイボンド板の一領域との間に粘性部材を
充填しているため、樹脂と放熱板どの熱膨張係数の差異
に基づく応力の発生が抑制されて熱ス１〜レスに対し十
分な信頼性が得られるとともに、半導体集積回路チップ
の動作によって生じる熱は、ダイボンド板９弾性部材お
よび放熱板を介して外部へ効率よく放出できるという効
果が得られる。As described above, according to the semiconductor device of the present invention, the tie bond plate is sealed with resin except for the narrow area, and the heat sink is connected with a substantial gap between the tie bond plate and the resin. Since a viscous material is filled between the heat sink and a region of the die bond plate, the generation of stress due to the difference in thermal expansion coefficient between the resin and the heat sink is suppressed, and thermal stress is reduced. Sufficient reliability is obtained, and the heat generated by the operation of the semiconductor integrated circuit chip can be efficiently radiated to the outside via the elastic member of the die-bonding plate 9 and the heat sink.
第１図はこの発明の一実施例である半導体装置を示づ断
面図、第２図は従来の半導体装置を示す断面図である。
図において、１０はダイボンド板、１１は放熱板、１２
は半導体集積回路チップ、１３は金属フレーム、１／Ｉ
は電気接続用ワイＡ７−１５は樹脂１（３は接続用穴、
１７は接続用突部、１８は粘性部材である。
なお、各図中同一符号は同一または相当部分をボす。FIG. 1 is a sectional view showing a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a sectional view showing a conventional semiconductor device. In the figure, 10 is a die bond plate, 11 is a heat sink, 12
is a semiconductor integrated circuit chip, 13 is a metal frame, 1/I
is the electrical connection wire A7-15 is the resin 1 (3 is the connection hole,
17 is a connecting protrusion, and 18 is a viscous member. Note that the same reference numerals in each figure indicate the same or corresponding parts.
Claims (1)
ンド板を、その他面の一領域を除いて前記半導体集積回
路チップとともに樹脂により封止し、放熱板を、前記ダ
イボンド板の前記一領域を覆って前記樹脂との間に実質
的に隙間をもたせるように配設するとともに、前記ダイ
ボンド板の前記一領域と、その一領域に対応する前記放
熱板との間に粘性部材を充填したことを特徴とする半導
体装置。(1) A die-bonding board on which a semiconductor integrated circuit chip is mounted on one side is sealed with a resin together with the semiconductor integrated circuit chip except for one area on the other side, and a heat dissipation plate is placed to cover the one area of the die-bonding plate. and the resin, and a viscous member is filled between the one region of the die bond plate and the heat sink corresponding to the one region. semiconductor device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1009036A JPH02189959A (en) | 1989-01-18 | 1989-01-18 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1009036A JPH02189959A (en) | 1989-01-18 | 1989-01-18 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02189959A true JPH02189959A (en) | 1990-07-25 |
Family
ID=11709425
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1009036A Pending JPH02189959A (en) | 1989-01-18 | 1989-01-18 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02189959A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993006621A1 (en) * | 1991-09-27 | 1993-04-01 | Vlsi Technology, Inc. | Exposed die-attach heatsink package |
| WO2002075755A1 (en) * | 2001-03-21 | 2002-09-26 | Shin-Etsu Chemical Co., Ltd. | Electromagnetic wave absorbing thermally conductive composition and thermosoftening electromagnetic wave absorbing heat dissipation sheet and method of heat dissipation work |
| JP2018082113A (en) * | 2016-11-18 | 2018-05-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
-
1989
- 1989-01-18 JP JP1009036A patent/JPH02189959A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1993006621A1 (en) * | 1991-09-27 | 1993-04-01 | Vlsi Technology, Inc. | Exposed die-attach heatsink package |
| WO2002075755A1 (en) * | 2001-03-21 | 2002-09-26 | Shin-Etsu Chemical Co., Ltd. | Electromagnetic wave absorbing thermally conductive composition and thermosoftening electromagnetic wave absorbing heat dissipation sheet and method of heat dissipation work |
| US7417078B2 (en) | 2001-03-21 | 2008-08-26 | Shin-Etsu Chemical Co., Ltd. | Electromagnetic wave absorbing thermally conductive composition and thermosoftening electromagnetic wave absorbing heat dissipation sheet and method of heat dissipation work |
| JP2018082113A (en) * | 2016-11-18 | 2018-05-24 | 三菱電機株式会社 | Semiconductor device and manufacturing method of the same |
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