JPS63107156A - Resin packaged type semiconductor device - Google Patents
Resin packaged type semiconductor deviceInfo
- Publication number
- JPS63107156A JPS63107156A JP61251710A JP25171086A JPS63107156A JP S63107156 A JPS63107156 A JP S63107156A JP 61251710 A JP61251710 A JP 61251710A JP 25171086 A JP25171086 A JP 25171086A JP S63107156 A JPS63107156 A JP S63107156A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- chip
- coat film
- semiconductor chip
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 47
- 229920005989 resin Polymers 0.000 title abstract description 41
- 239000011347 resin Substances 0.000 title abstract description 41
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 239000004642 Polyimide Substances 0.000 claims description 5
- 239000003822 epoxy resin Substances 0.000 claims description 4
- 229920002857 polybutadiene Polymers 0.000 claims description 4
- 229920000647 polyepoxide Polymers 0.000 claims description 4
- 229920002379 silicone rubber Polymers 0.000 claims description 4
- 239000004945 silicone rubber Substances 0.000 claims description 4
- 229920002050 silicone resin Polymers 0.000 claims description 3
- 125000005647 linker group Chemical group 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 abstract description 7
- 238000000576 coating method Methods 0.000 abstract description 7
- 230000001070 adhesive effect Effects 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract 4
- 230000015556 catabolic process Effects 0.000 abstract 2
- 239000005022 packaging material Substances 0.000 abstract 1
- 239000000463 material Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 230000001351 cycling effect Effects 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 4
- ZSLUVFAKFWKJRC-IGMARMGPSA-N 232Th Chemical compound [232Th] ZSLUVFAKFWKJRC-IGMARMGPSA-N 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 3
- 229910052776 Thorium Inorganic materials 0.000 description 3
- 229910052770 Uranium Inorganic materials 0.000 description 3
- 239000000945 filler Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000035882 stress Effects 0.000 description 3
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 229920001971 elastomer Polymers 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000007257 malfunction Effects 0.000 description 2
- 239000005060 rubber Substances 0.000 description 2
- 239000000565 sealant Substances 0.000 description 2
- 239000003566 sealing material Substances 0.000 description 2
- 230000008646 thermal stress Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 208000032368 Device malfunction Diseases 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 239000011668 ascorbic acid Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000005336 cracking Methods 0.000 description 1
- 238000006073 displacement reaction Methods 0.000 description 1
- 230000003993 interaction Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 229920001296 polysiloxane Polymers 0.000 description 1
- 239000007779 soft material Substances 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、樹脂封止型半導体装置に関し、特に、樹脂封
止材の温度変化による影響を低減する技術に適用して有
効な技術に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a resin-sealed semiconductor device, and particularly to a technique that is effective when applied to a technique for reducing the effects of temperature changes on a resin-sealing material. It is.
一般に、半導体集積回路（以下、ＩＣという）の全体構
造は、第１図に示すように構成されている。第１図にお
いて、１はリードフレーム、２は半導体チップ取付は用
基板（タブ）、３はベレットボンディング用接合材、４
は半導体チップ、５はボンディングワイヤ、６はチップ
コート膜、７はモールドレジンである。Generally, the overall structure of a semiconductor integrated circuit (hereinafter referred to as IC) is as shown in FIG. In Fig. 1, 1 is a lead frame, 2 is a substrate (tab) for attaching a semiconductor chip, 3 is a bonding material for bullet bonding, and 4 is a board for attaching a semiconductor chip.
5 is a semiconductor chip, 5 is a bonding wire, 6 is a chip coat film, and 7 is a mold resin.
前記ＩＣにおいて、前記チップコート膜６は、モールド
レジン７中のシリカフィラーに含まれるウラン、トリウ
ムから出るアルファ粒子による素子の誤動作を防止し、
かつモールドレジン７の応力によって素子面が損傷を受
けるのを防止する目的で施されている。チップコート膜
６の材料としては、通常シリコーン樹脂系のゲル（非常
に軟らかいゲル状のもの）又はゴム（硬さＪＩＳＡ２０
〜７０．ヤング率＜ ０ 、５ ｋｇｆ／ｍｍ２） 、
あるいはポリイミド系樹脂材料（ヤング率”Ｅ ３００
ｋｇｆ／ｍｍ２）が使われている。In the IC, the chip coat film 6 prevents malfunction of the device due to alpha particles emitted from uranium and thorium contained in the silica filler in the mold resin 7,
This is also done to prevent the element surface from being damaged by the stress of the mold resin 7. The material for the chip coat film 6 is usually silicone resin gel (very soft gel-like material) or rubber (hardness JISA 20).
~70. Young's modulus < 0, 5 kgf/mm2),
Or polyimide resin material (Young's modulus "E 300")
kgf/mm2) is used.
また、モールドレジン７としては、その線膨張係数αが
Ｌ７Ｘ１０°″／℃〜３０ Ｘ １０°ｆ′／℃の範囲
のものが使われている。Moreover, as the mold resin 7, one whose linear expansion coefficient α is in the range of L7×10°″/°C to 30×10°f′/°C is used.
しかしながら、発明者は、かかる技術を検討した結果、
次のような問題点を見出した。However, as a result of considering such technology, the inventor found that
We found the following problems.
温度サイクル寿命試験（通常−５５℃で３０分、１５０
℃で３０分のサイクル）で約５００サイクルからボンデ
ィングワイヤ５のポールネック部で断線してしまう。Temperature cycle life test (normally -55℃ for 30 minutes, 150℃
The bonding wire 5 breaks at the pole neck after about 500 cycles.
このボンディングワイヤ５の断線のメカニズムは、次の
ように考えられる。The mechanism of this disconnection of the bonding wire 5 can be considered as follows.
ボンディングワイヤ５の半導体チップ４側接合部Ａとそ
の周辺について考えると、ボンディングワイヤ５は、前
記接合部Ａで半導体チップ４に接合され、また、点Ｂで
モールドレジン７によって固定されている。一方、接合
部Ａと点８間は、比較的柔らかいチップコート膜６の材
料で囲まれているため、相互作用力は小さい。Considering the bonding portion A of the bonding wire 5 on the semiconductor chip 4 side and its surroundings, the bonding wire 5 is bonded to the semiconductor chip 4 at the bonding portion A, and is fixed by the mold resin 7 at a point B. On the other hand, since the area between the joint A and the point 8 is surrounded by the relatively soft material of the chip coat film 6, the interaction force is small.
ここで、温度サイクル試験において八Ｔなる温度変化を
受けると、パッケージ全体は、ある変形をし、また内部
の接合部Ａと点Ｂも相対的に変位をし、その結果距離Ａ
ＢがＡ’Ｂ’となり、式（１）で示す歪みεがボンディ
ングワイヤ５のに１間に発生する。Here, when subjected to a temperature change of 8T in a temperature cycle test, the entire package undergoes a certain deformation, and the internal joints A and B also undergo relative displacement, resulting in a distance of A.
B becomes A'B', and the strain ε shown in equation (1) is generated between 1 and 1 of the bonding wire 5.
温度サイクル試験では、ボンディングワイヤ５は、繰り
返し±εの歪みを受けることになり、その結果量も弱い
ボールのすぐ上部のネック部が疲労破壊し、断線に到る
。In the temperature cycle test, the bonding wire 5 is repeatedly subjected to strain of ±ε, and as a result, the neck portion immediately above the ball, which is weak in amount, suffers fatigue failure and breaks.
また、例えば、シリコーンゲル又はゴムからなるチップ
コート膜６の場合では、チップコート膜６に接している
モールドレジン７が温度変化により容易に動き、半導体
チップ４のコーナ一部分のモールドレジンに応力が集中
してレジンクラックが発生する。For example, in the case of a chip coat film 6 made of silicone gel or rubber, the mold resin 7 in contact with the chip coat film 6 moves easily due to temperature changes, and stress is concentrated on the mold resin at a part of the corner of the semiconductor chip 4. Resin cracks occur.
また、前記チップコート６がポリイミド系のチップコー
ト膜からなる場合では、この膜が硬いためにモールドレ
ジン７の熱応力が吸収できないので、半導体チップ４面
に損傷を与え、半導体チップ４が電気的特性不良となる
場合がある。Furthermore, in the case where the chip coat 6 is made of a polyimide-based chip coat film, this film is hard and cannot absorb the thermal stress of the mold resin 7, which may damage the semiconductor chip 4 surface and cause the semiconductor chip 4 to become electrically unstable. This may result in poor characteristics.
本発明の目的は、チップコート膜を有する樹脂封止型半
導体装置において、温度サイクル時におけるボンディン
グワイヤの断線を防止し、また、モールドレジンのクラ
ックを防止することができる技術を提供することにある
。An object of the present invention is to provide a technology that can prevent bonding wires from breaking during temperature cycling and also prevent mold resin from cracking in a resin-sealed semiconductor device having a chip coat film. .
本発明の他の目的は、チップコート膜を有する樹脂封止
型半導体装置において、温度サイクル時における半導体
チップの損傷を防止することができる技術を提供するこ
とにある。Another object of the present invention is to provide a technique that can prevent damage to a semiconductor chip during temperature cycling in a resin-sealed semiconductor device having a chip coat film.
本発明の他の目的は、チップコート膜を有する樹脂封止
型半導体装置の信頼性を向上することができる技術を提
供することにある。Another object of the present invention is to provide a technique that can improve the reliability of a resin-sealed semiconductor device having a chip coat film.
本発明の前記ならびにその他の目的と新規な特徴は、本
明細書の記述及び添付図面によって明らかになるであろ
う。The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.
本願において開示される発明のうち、代表的なものの概
要を簡単に説明すれば、下記のとおりである。A brief overview of typical inventions disclosed in this application is as follows.
基板上に半導体チップを塔載し、ワイヤボンディングし
、該半導体チップの活性領域側上にチップコート膜を設
けた後、モールドレジンで樹脂封止した樹脂封止型半導
体装置であって、前記チップコート膜のヤング率（縦弾
性係数）を１ ｋｇｆ／ｍｍ２〜１００ ｋｇｆ／ｍｍ
２とし、また、チップコート膜とモールドレジンの界面
における接着性を付与したものである。A resin-sealed semiconductor device in which a semiconductor chip is mounted on a substrate, wire-bonded, a chip coat film is provided on the active region side of the semiconductor chip, and then resin-sealed with a mold resin. The Young's modulus (longitudinal elastic modulus) of the coating film is 1 kgf/mm2 to 100 kgf/mm.
2, and also has adhesion at the interface between the chip coat film and the mold resin.
前記した手段によれば、前記チップコート膜のヤング率
を１ ｋｇｆｌｏｎ” 〜１００ ｋｇｆｌｏｎ”とし
、かつモールドレジンをチップコート膜に良く接着させ
たことにより、温度サイクル時におけるモールドレジン
（樹脂封止材）の熱歪みがチップコート膜によって緩和
され、かつモールドレジンとチップコート膜の界面にお
いてもずれが生じがたいため、ボンディングワイヤの断
線及びレジンクラックの発生を防止することができ、ま
た、チップコート膜がポリイミド等によりやわらかいた
めに半導体チップの損傷を防止することができる。According to the above-mentioned means, by setting the Young's modulus of the chip coat film to 1 kgflon'' to 100 kgflon'' and adhering the mold resin well to the chip coat film, the mold resin (resin sealant ) is alleviated by the chip coat film, and the interface between the mold resin and the chip coat film is less prone to misalignment, making it possible to prevent bonding wire breakage and resin cracks. Since the film is made of polyimide or the like and is soft, damage to the semiconductor chip can be prevented.
以下１本発明の一実施例を具体的に説明する。 An embodiment of the present invention will be specifically described below.
本実施例の樹脂封止型半導体装置の基本的構成は、第１
図と同じであるが、異なる点は、前記チップコート膜６
のヤング率（縦弾性係数）を１ｋｇｆ／ｍｍ２〜１００
ｋｇｆｌｏｎ２とし、かつチップコート膜６にモール
ドレジン７との接着性を付与したことである。The basic configuration of the resin-sealed semiconductor device of this example is as follows:
It is the same as the figure, but the difference is that the chip coat film 6
Young's modulus (longitudinal elastic modulus) of 1 kgf/mm2 to 100
kgflon2, and the chip coat film 6 is given adhesiveness to the mold resin 7.
すなわち１本実施例の樹脂封止型半導体装置は。That is, the resin-sealed semiconductor device of this embodiment is as follows.
半導体チップ取付は用基板２上に半導体チップ４を塔載
し、ボンディングワイヤ５で半導体チップ４とリードフ
レーム１とを電気的に接続し、前記半導体チップ４の活
性領域側上にチップコート膜６を設けた後、モールドレ
ジン７で樹脂封止したものである。そして、前記チップ
コート膜６のヤング率（縦弾性係数）を１ ｋｇｆ／＋
ａｍ” 〜１００ ｋｇｆｌｏｎ２とし、また、チップ
コート膜６にモールドレジン７との接着性を付与したも
のである。The semiconductor chip is mounted by mounting the semiconductor chip 4 on the substrate 2, electrically connecting the semiconductor chip 4 and the lead frame 1 with bonding wires 5, and applying a chip coat film 6 on the active region side of the semiconductor chip 4. After this, the molded resin 7 is used to seal the molded resin. Then, the Young's modulus (longitudinal elastic modulus) of the chip coat film 6 is set to 1 kgf/+
am'' to 100 kgflon2, and the chip coat film 6 has adhesive properties with the mold resin 7.
前記半導体チップ取付は用基板２及びリードフレーム１
は、例えば、銅（Ｃｕ）系、鉄（Ｆａ）系等の材料を用
いる。又はその他の材料を用いてもよい。The semiconductor chip is mounted on a board 2 and a lead frame 1.
For example, a material such as copper (Cu) or iron (Fa) is used. Or other materials may be used.
前記チップコート膜６は１例えば、分子構造中にエポキ
シレジンとの化学反応による結合基又は相溶性（分子同
志がからみ合って接着力を生じること）を有する基を備
えたシリコーン系樹脂、エポキシレジンをポリブタジェ
ンゴム分子又はシリコーンゴム分子で変成して低弾性化
したもの、ポリイミドにポリブタジェンゴム又はシリコ
ーンゴムを導入して変成し、低弾性化したもの等を用い
る。The chip coat film 6 is made of, for example, silicone resin or epoxy resin, which has a bonding group in its molecular structure due to a chemical reaction with epoxy resin or a group having compatibility (molecules are entangled with each other to generate adhesive force). Used are polyimides modified with polybutadiene rubber or silicone rubber molecules to have low elasticity, and polyimide modified by introducing polybutadiene rubber or silicone rubber to have low elasticity.
前記モールドレジン７としては、例えば、その線膨張係
数αが１７ Ｘ １０−” ／ ”Ｃ〜３０ Ｘ １０
−’ ／ ℃の範囲のものを用いる。For example, the mold resin 7 has a linear expansion coefficient α of 17×10−”/”C to 30×10
-'/°C range is used.
このように、前記チップコート膜６のヤング率を１ ｋ
ｇｆ／ａｍ２〜１００ ｋｇｆｌｏｎ”としかつモール
ドレジンとの接着性にとぼしい材料については接着性を
付与することにより、温度サイクル時におけるモールド
レジン（樹脂封止材）７の熱歪み及び熱変形を低減する
ことができるので、ボンディングワイヤ５の断線及びレ
ジンクラックの発生及び半導体チップ４の損傷を防止す
ることができる。これと同時に、チップコート膜６の本
来の目的を達成することができる。すなわち、モールド
レジン７中のシリカフィラーに含まれるウラン、トリウ
ムから出るアルファ粒子による素子の誤動作を防止する
ことができる。これにより、樹脂封止型半導体装置の信
頼性を向上することができる。In this way, the Young's modulus of the chip coat film 6 is set to 1 k
gf/am2 to 100 kgflon" and impart adhesiveness to materials that have poor adhesion to the mold resin, thereby reducing thermal strain and thermal deformation of the mold resin (resin sealing material) 7 during temperature cycling. Therefore, it is possible to prevent disconnection of the bonding wire 5, generation of resin cracks, and damage to the semiconductor chip 4.At the same time, the original purpose of the chip coat film 6 can be achieved. It is possible to prevent device malfunctions due to alpha particles emitted from uranium and thorium contained in the silica filler in the resin 7. Thereby, the reliability of the resin-sealed semiconductor device can be improved.
以上、本発明を実施例にもとづき具体的に説明したが、
本発明は、前記実施例に限定されるものではなく、その
要旨を逸脱しない範囲において種々変更可能であること
は言うまでもない。The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.
例えば、前記実施例では、ＤＩＬ型の半導体パッケージ
を用いて説明したが、本発明は、そのパッケージ形状は
ＰＬＣＣ，ＳＯＪ、ＺＩＰ、、Ｓ。For example, in the embodiment described above, a DIL type semiconductor package was used, but in the present invention, the package shape is PLCC, SOJ, ZIP, or S.
Ｐ等のタイプの半導体パッケージでも良い。A type of semiconductor package such as P type may also be used.
また、本発明は、アルファ線ソフトエラーが問題となる
メモリＩＣ、モールドレジン７の応力によって素子面が
損傷を受は易いゲートアレイ、マイコン等のＩＣ１半田
実装時の熱ストレスによって耐湿信頼性が劣化し易い面
付実装型の薄型パッケージのＩＣ等チップコートを必要
とするレジンモールド型ＩＣ等にも適用できる。In addition, the present invention is applicable to memory ICs where alpha ray soft errors are a problem, gate arrays where the element surface is easily damaged by the stress of the mold resin 7, and IC1s such as microcontrollers whose moisture resistance is degraded by thermal stress during solder mounting. It can also be applied to resin-molded ICs that require chip coating, such as surface-mount thin package ICs that are easy to apply.
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとおりであ
る。A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.
すなわち、チップコート膜のヤング率を１ ｋｇｆ／ｌ
１ｍ２〜１０ｏｋｇｆ／ｍｍ２とし、かつチップコート
膜にモールドレジンとの接着性を付与したことにより、
温度サイクル時におけるモールドレジン（樹脂封止材）
の熱歪み及び熱変形を低減することができるので、ボン
ディングワイヤの断線及びレジンクラックの発生及び半
導体チップの損傷を防止することができる。これと同時
に、チップコート膜の本来の目的を達成することができ
る。すなわち、モールドレジン中のシリカフィラーに含
まれるウラン、トリウムから出るアルファ粒子による素
子の誤動作を防止することができる。これにより、樹脂
封止型半導体装置の信頼性を向上することができる。That is, the Young's modulus of the chip coat film is 1 kgf/l.
1m2 to 10okgf/mm2, and by giving the chip coat film adhesiveness with the mold resin,
Mold resin (resin sealant) during temperature cycling
Since thermal distortion and thermal deformation of the bonding wire can be reduced, disconnection of the bonding wire, generation of resin cracks, and damage to the semiconductor chip can be prevented. At the same time, the original purpose of the chip coat film can be achieved. That is, malfunction of the device due to alpha particles emitted from uranium and thorium contained in the silica filler in the mold resin can be prevented. Thereby, the reliability of the resin-sealed semiconductor device can be improved.
第１図は、一般の半導体集積回路の全体構造を示す断面
図である。
図中、１・・・リードフレーム、２・・・半導体チップ
取付は用基板（タブ）、３・・・ペレットボンディング
用接合材、４・・・半導体チップ、５・・・ボンディン
グワイヤ、６・・・チップコート膜、７・・・モールド
レジンである。FIG. 1 is a cross-sectional view showing the overall structure of a general semiconductor integrated circuit. In the figure, 1...Lead frame, 2...Semiconductor chip mounting substrate (tab), 3...Jointing material for pellet bonding, 4...Semiconductor chip, 5...Bonding wire, 6... ...Chip coat film, 7...Mold resin.
Claims (1)
グし、該半導体チップの活性領域側上にチップコート膜
を設けた後、樹脂封止した樹脂封止型半導体装置であっ
て、前記チップコート膜のヤング率を１ｋｇｆ／ｍｍ＾
２〜１００ｋｇｆ／ｍｍ＾２としたことを特徴とする樹
脂封止型半導体装置。 ２ 前記チップコート膜は、分子構造中にエポキシレジ
ンとの結合基又は相溶性を有する基を備えたシリコーン
系樹脂からなることを特徴とする特許請求の範囲第１項
に記載の樹脂封止型半導体装置。 ３ 前記チップコート膜は、エポキシレジンをポリブタ
ジエンゴム分子又はシリコーンゴム分子で変成して低弾
性化したものからなることを特徴とする特許請求の範囲
第１項に記載の樹脂封止型半導体装置。 ４ 前記チップコート膜は、ポリイミドに、ポリブタジ
エンゴム又はシリコーンゴムを導入して変成し、低弾性
化したものからなることを特徴とする特許請求の範囲第
１項に記載の樹脂封止型半導体装置。[Claims] 1. A resin-sealed semiconductor device in which a semiconductor chip is mounted on a substrate, wire bonded, a chip coat film is provided on the active region side of the semiconductor chip, and then resin-sealed. Then, the Young's modulus of the chip coat film is 1 kgf/mm^
A resin-sealed semiconductor device characterized in that it has a power of 2 to 100 kgf/mm^2. 2. The resin-sealed type according to claim 1, wherein the chip coat film is made of a silicone resin having a bonding group or a group having compatibility with an epoxy resin in its molecular structure. Semiconductor equipment. 3. The resin-sealed semiconductor device according to claim 1, wherein the chip coat film is made of an epoxy resin modified with polybutadiene rubber molecules or silicone rubber molecules to have low elasticity. 4. The resin-sealed semiconductor device according to claim 1, wherein the chip coat film is made of polyimide modified by introducing polybutadiene rubber or silicone rubber to make the elasticity lower. .
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251710A JPS63107156A (en) | 1986-10-24 | 1986-10-24 | Resin packaged type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61251710A JPS63107156A (en) | 1986-10-24 | 1986-10-24 | Resin packaged type semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63107156A true JPS63107156A (en) | 1988-05-12 |
Family
ID=17226840
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61251710A Pending JPS63107156A (en) | 1986-10-24 | 1986-10-24 | Resin packaged type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63107156A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH02120840U (en) * | 1989-03-15 | 1990-09-28 | ||
| US5229646A (en) * | 1989-01-13 | 1993-07-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a copper wires ball bonded to aluminum electrodes |
| US5287003A (en) * | 1991-02-26 | 1994-02-15 | U.S. Philips Corporation | Resin-encapsulated semiconductor device having a passivation reinforcement hard polyimide film |
| JPH0786461A (en) * | 1993-09-02 | 1995-03-31 | Internatl Business Mach Corp <Ibm> | Module of sealed semiconductor chip, and module forming method |
| KR100472286B1 (en) * | 2002-09-13 | 2005-03-10 | 삼성전자주식회사 | Semiconductor chip package that adhesive tape is attached on the bonding wire |
| WO2006103962A1 (en) * | 2005-03-25 | 2006-10-05 | Sumitomo Bakelite Co., Ltd. | Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulation |
-
1986
- 1986-10-24 JP JP61251710A patent/JPS63107156A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5229646A (en) * | 1989-01-13 | 1993-07-20 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device with a copper wires ball bonded to aluminum electrodes |
| JPH02120840U (en) * | 1989-03-15 | 1990-09-28 | ||
| US5287003A (en) * | 1991-02-26 | 1994-02-15 | U.S. Philips Corporation | Resin-encapsulated semiconductor device having a passivation reinforcement hard polyimide film |
| JPH0786461A (en) * | 1993-09-02 | 1995-03-31 | Internatl Business Mach Corp <Ibm> | Module of sealed semiconductor chip, and module forming method |
| KR100472286B1 (en) * | 2002-09-13 | 2005-03-10 | 삼성전자주식회사 | Semiconductor chip package that adhesive tape is attached on the bonding wire |
| WO2006103962A1 (en) * | 2005-03-25 | 2006-10-05 | Sumitomo Bakelite Co., Ltd. | Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulation |
| JP4935670B2 (en) * | 2005-03-25 | 2012-05-23 | 住友ベークライト株式会社 | Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for sealing |
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