JPH0685132A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0685132A
JPH0685132A JP23831492A JP23831492A JPH0685132A JP H0685132 A JPH0685132 A JP H0685132A JP 23831492 A JP23831492 A JP 23831492A JP 23831492 A JP23831492 A JP 23831492A JP H0685132 A JPH0685132 A JP H0685132A
Authority
JP
Japan
Prior art keywords
die pad
semiconductor chip
semiconductor device
resin sealing
sealing body
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP23831492A
Other languages
Japanese (ja)
Inventor
Ko Shimomura
興 下村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP23831492A priority Critical patent/JPH0685132A/en
Publication of JPH0685132A publication Critical patent/JPH0685132A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To provide a semiconductor device, in which a characteristic deterioration in a semiconductor chip caused by interfacial flaking between a die pad and a resin sealing body as well as destruction of a resin sealing material is prevented. CONSTITUTION:A semiconductor device comprises a semiconductor chip 1, a plurality of lead members 4, one end of which is connected to the semiconductor device 1, a die pad 7 having on one side an uneven face 7c and an adhesive face 7a for mounting the semiconductor device 1, and a resin sealing body 8 for sealing the semiconductor chip 1 with each one end of the lead members 4 firmly to the die pad 7 after the other face 7b of the die pad 7 is exposed.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】この発明は、半導体チップをレジ
ン封止した樹脂封止型半導体装置に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device in which a semiconductor chip is resin-sealed.

【0002】[0002]

【従来の技術】図2は従来の半導体装置の断面図であ
る。図において、1は半導体チップ、2は半導体チップ
1を載置し接着剤3で接着するダイパッド、4はダイパ
ッド2と略同一面でダイパッド2の両側にあって側方に
延びる複数のリード片、5は半導体チップ1とリード片
4のダイパッド2側とを接続するボンディングワイヤ、
6は上記構成要素1〜5をリード片4の一部が側方に突
出するようにして包囲し封止固定するレジン封止体でこ
の場合エポキシ樹脂ベースのものが主流であり有機高分
子と無機充填材により構成されている。
2. Description of the Related Art FIG. 2 is a sectional view of a conventional semiconductor device. In the figure, 1 is a semiconductor chip, 2 is a die pad on which the semiconductor chip 1 is mounted and adhered with an adhesive 3, 4 is a plurality of lead pieces extending on the both sides of the die pad 2 on the same plane as the die pad 2 and extending laterally, 5 is a bonding wire for connecting the semiconductor chip 1 and the die pad 2 side of the lead piece 4,
Reference numeral 6 denotes a resin encapsulating body which encloses and fixes the above-mentioned constituent elements 1 to 5 so that a part of the lead piece 4 projects laterally, and in this case, an epoxy resin-based resin is the mainstream, It is composed of an inorganic filler.

【0003】次に動作について説明する。ダイパッド2
上に半導体チップ1を搭載し、ボンディングワイヤ5に
より半導体チップ1とリード片4を電気的に接続した半
導体装置はレジン封止体6により成形,封止,絶縁され
る。この成形は通常低圧トランスファー法にて180℃
前後の温度でなされる。上記プロセスで製造された樹脂
封止型の半導体装置は、一般に異なる物性値(熱膨張係
数,弾性率,他)をもつ材料で構成されている。
Next, the operation will be described. Die pad 2
The semiconductor device having the semiconductor chip 1 mounted thereon and electrically connecting the semiconductor chip 1 and the lead pieces 4 by the bonding wires 5 is molded, sealed and insulated by the resin sealing body 6. This molding is usually performed at 180 ° C by the low pressure transfer method.
Made at around temperature. The resin-encapsulated semiconductor device manufactured by the above process is generally made of materials having different physical property values (coefficient of thermal expansion, elastic modulus, etc.).

【0004】[0004]

【発明が解決しようとする課題】従来の半導体装置は以
上のように構成されているので、特に表面実装型半導体
装置では装置全体が実装時に昇温され、保管時に樹脂吸
収した水分の急激な水蒸気化により、ダイパッドの裏面
とレジン封止体との界面剥離(図3に示す9)が発生し
半導体チップの特性変化,ボンディングワイヤ部の強度
劣化、あるいは半導体レジン封止体のクラック(図3に
示す10)などの故障を引き起こすなどの問題点があっ
た。
Since the conventional semiconductor device is constructed as described above, particularly in the surface mount type semiconductor device, the temperature of the entire device is raised during mounting, and the water vapor absorbed by the resin during storage is abrupt. As a result, interface peeling between the back surface of the die pad and the resin encapsulant (9 in FIG. 3) occurs, the characteristics of the semiconductor chip change, the strength of the bonding wire part deteriorates, or the semiconductor resin encapsulant cracks (see FIG. 3). There is a problem such as causing a failure such as 10) shown below.

【0005】この発明は上記の様な問題点を解消するた
めになされたもので、ダイパッドとレジン封止体との界
面剥離に起因する半導体チップ特性劣化やレジン封止体
自身の材料破壊を防止できる半導体装置を得ることを目
的としている。
The present invention has been made to solve the above problems, and prevents deterioration of semiconductor chip characteristics and material destruction of the resin sealing body itself due to interfacial peeling between the die pad and the resin sealing body. The purpose is to obtain a semiconductor device that can be manufactured.

【0006】[0006]

【課題を解決するための手段】この発明に係る半導体装
置は、半導体チップと、一端側が半導体チップと接続線
で結線された複数のリード片と、一面側に半導体チップ
の載置接着面と凹凸表面とを有するダイパッドと、ダイ
パッドの他方面を露出させて半導体チップ及びリード片
の一端側をダイパッドと封止固定するレジン封止体とで
構成したものである。
A semiconductor device according to the present invention includes a semiconductor chip, a plurality of lead pieces whose one end side is connected to the semiconductor chip by a connecting wire, and a semiconductor chip mounting adhesive surface and an uneven surface on one surface side. A die pad having a surface and a resin sealing body that seals and fixes one end side of the semiconductor chip and the lead piece to the die pad by exposing the other surface of the die pad.

【0007】[0007]

【作用】この発明における半導体装置のダイパッドは、
裏面側を露出したことにより裏面側でのレジン封止体に
対する作用応力がなくなる。また、凹凸状の面がレジン
封止体との接合力を向上させ界面剥離を防止する。
The die pad of the semiconductor device according to the present invention is
By exposing the back surface side, the stress acting on the resin sealing body on the back surface side is eliminated. Further, the uneven surface improves the bonding force with the resin sealing body and prevents interfacial peeling.

【0008】[0008]

【実施例】実施例1.以下、この発明の実施例1を図に
ついて説明する。図1はこの発明の実施例1における半
導体装置を示す断面図である。図において、1,3ない
し5は従来と同様であるためその説明は省略する。7は
一面側に半導体チップ1の載置接着面7aと凹凸表面7
cを有し他面側7bが露出面となるダイパッド、8はダ
イパッド7の他面側7bを露出させて半導体チップ1及
びリード片4の一端側をダイパッド7と封止固定するレ
ジン封止体である。
EXAMPLES Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention. In the figure, the reference numerals 1, 3 and 5 are the same as the conventional ones, and therefore their explanations are omitted. 7 is a mounting adhesive surface 7a of the semiconductor chip 1 and an uneven surface 7 on one surface side.
A die pad 8 having c and the other surface side 7b being an exposed surface, and 8 is a resin sealing body for exposing the other surface side 7b of the die pad 7 and sealingly fixing one end side of the semiconductor chip 1 and the lead piece 4 to the die pad 7. Is.

【0009】次に動作について説明する。ダイパッド7
の他面側7bを全面露出することによりレジン封止体8
とダイパッド7の他面側7bとの界面がなくなり、レジ
ン封止体8の硬化収縮,熱収縮及び温度サイクル,高温
保存等により発生する種々の応力で起きるレジン封止体
8とダイパッドの裏面側における界面剥離を解消するこ
とができ同時にレジン封止体8のクラック発生も防止で
きる。また、ダイパッド7に設けられた凹凸表面7cに
よって当部位とレジン封止体8との接着面積が増加し発
生応力に充分対応してダイパッド7とレジン封止体8間
の界面剥離を防止することができる。
Next, the operation will be described. Die pad 7
The resin sealing body 8 is formed by exposing the entire other surface side 7b.
And the other surface side 7b of the die pad 7 disappears, and the resin sealing body 8 and the back surface side of the die pad 8 which are caused by various stresses caused by curing shrinkage, thermal shrinkage of the resin sealing body 8 and temperature cycle, high temperature storage, etc. It is possible to eliminate the interfacial peeling at the same time, and at the same time prevent the occurrence of cracks in the resin sealing body 8. In addition, the uneven surface 7c provided on the die pad 7 increases the adhesion area between the site and the resin sealing body 8 and sufficiently copes with the generated stress to prevent the interface peeling between the die pad 7 and the resin sealing body 8. You can

【0010】[0010]

【発明の効果】以上のように、この発明における半導体
装置は、半導体チップと、一端側が半導体チップと接続
線で結線された複数のリード片と、一面側に半導体チッ
プの載置接着面と凹凸表面とを有するダイパッドと、ダ
イパッドの他面側を露出させて半導体チップ及びリード
片の一端側をダイパッドと封止固定するレジン封止体と
で構成したので、ダイパッドとレジン封止体との界面剥
離に起因する半導体チップ特性劣化やレジン封止体自身
の材料破壊を防止できる半導体装置が得られる効果があ
る。
As described above, the semiconductor device according to the present invention includes a semiconductor chip, a plurality of lead pieces whose one end side is connected to the semiconductor chip by a connecting wire, and a semiconductor chip mounting adhesive surface and unevenness on one surface side. Since the die pad having a surface and the resin sealing body that exposes the other surface side of the die pad and seals and fixes one end side of the semiconductor chip and the lead piece with the die pad, the interface between the die pad and the resin sealing body is formed. There is an effect that a semiconductor device capable of preventing deterioration of semiconductor chip characteristics due to peeling and material destruction of the resin sealing body itself can be obtained.

【図面の簡単な説明】[Brief description of drawings]

【図1】この発明の実施例1における半導体装置を示す
断面図である。
FIG. 1 is a sectional view showing a semiconductor device according to a first embodiment of the present invention.

【図2】従来の半導体装置を示す断面図である。FIG. 2 is a cross-sectional view showing a conventional semiconductor device.

【図3】従来の半導体装置における不良状態を示す断面
図である。
FIG. 3 is a cross-sectional view showing a defective state of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 半導体チップ 4 リード片 5 接続線 7 ダイパッド 7a 載置接着面 7b 露出面(他面側) 7c 凹凸表面 8 レジン封止体 DESCRIPTION OF SYMBOLS 1 Semiconductor chip 4 Lead piece 5 Connection wire 7 Die pad 7a Mounting adhesive surface 7b Exposed surface (other surface side) 7c Uneven surface 8 Resin sealing body

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体チップと、一端側が上記半導体チ
ップと接続線で結線された複数のリード片と、一面側に
上記半導体チップの載置接着面と凹凸表面とを有するダ
イパッドと、該ダイパッドの他面側を露出させて上記半
導体チップ及び上記リード片の一端側を上記ダイパッド
と封止固定するレジン封止体とを備えたことを特徴とす
る半導体装置。
1. A semiconductor chip, a plurality of lead pieces, one end of which is connected to the semiconductor chip by a connecting wire, a die pad having a mounting adhesive surface of the semiconductor chip and an uneven surface on one surface side, and a die pad of the die pad. A semiconductor device comprising: a resin sealing body that exposes the other surface side and seals and fixes one end side of the semiconductor chip and the lead piece to the die pad.
JP23831492A 1992-09-07 1992-09-07 Semiconductor device Pending JPH0685132A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP23831492A JPH0685132A (en) 1992-09-07 1992-09-07 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23831492A JPH0685132A (en) 1992-09-07 1992-09-07 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH0685132A true JPH0685132A (en) 1994-03-25

Family

ID=17028369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23831492A Pending JPH0685132A (en) 1992-09-07 1992-09-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0685132A (en)

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0964243A (en) * 1995-08-30 1997-03-07 Nec Corp Semiconductor device and manufacture thereof
US5910681A (en) * 1996-05-15 1999-06-08 Kabushiki Kaisha Toshiba Resin sealed semiconductor device
KR100298692B1 (en) * 1998-09-15 2001-10-27 마이클 디. 오브라이언 Lead frame structure for semiconductor package manufacturing
JP2001345414A (en) * 2000-06-01 2001-12-14 Seiko Epson Corp Lead frame, semiconductor device and its manufacturing method, circuit board, and electronic equipment
US6713849B2 (en) * 2000-12-28 2004-03-30 Hitachi, Ltd. Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
KR100477176B1 (en) * 1994-12-29 2005-07-28 닛토덴코 가부시키가이샤 Semiconductor device and manufacturing method thereof
KR100526837B1 (en) * 2000-04-27 2005-11-08 앰코 테크놀로지 코리아 주식회사 Semiconductor package
KR100522620B1 (en) * 1997-12-22 2006-01-12 오끼 덴끼 고오교 가부시끼가이샤 Semiconductor device
WO2009126367A1 (en) * 2008-04-08 2009-10-15 Freescale Semiconductor Inc. Leadframe for packaged electronic device with enhanced mold locking capability
US7906859B2 (en) 2007-08-22 2011-03-15 Denso Corporation Semiconductor device
JP2011114190A (en) * 2009-11-27 2011-06-09 Shindengen Electric Mfg Co Ltd Semiconductor package
DE102014202651A1 (en) 2013-04-02 2014-10-02 Mitsubishi Electric Corporation Semiconductor device and semiconductor module
US20150092379A1 (en) * 2013-09-30 2015-04-02 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same

Cited By (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100477176B1 (en) * 1994-12-29 2005-07-28 닛토덴코 가부시키가이샤 Semiconductor device and manufacturing method thereof
JPH0964243A (en) * 1995-08-30 1997-03-07 Nec Corp Semiconductor device and manufacture thereof
US5910681A (en) * 1996-05-15 1999-06-08 Kabushiki Kaisha Toshiba Resin sealed semiconductor device
US7538416B2 (en) 1997-06-27 2009-05-26 Panasonic Corporation Resin molded type semiconductor device and a method of manufacturing the same
US6861735B2 (en) 1997-06-27 2005-03-01 Matsushita Electric Industrial Co., Ltd. Resin molded type semiconductor device and a method of manufacturing the same
US6900524B1 (en) 1997-06-27 2005-05-31 Matsushita Electric Industrial Co., Ltd. Resin molded semiconductor device on a lead frame and method of manufacturing the same
KR100522620B1 (en) * 1997-12-22 2006-01-12 오끼 덴끼 고오교 가부시끼가이샤 Semiconductor device
KR100298692B1 (en) * 1998-09-15 2001-10-27 마이클 디. 오브라이언 Lead frame structure for semiconductor package manufacturing
US6437427B1 (en) 1998-09-15 2002-08-20 Amkor Technology, Inc. Lead frame used for the fabrication of semiconductor packages and semiconductor package fabricated using the same
KR100526837B1 (en) * 2000-04-27 2005-11-08 앰코 테크놀로지 코리아 주식회사 Semiconductor package
JP2001345414A (en) * 2000-06-01 2001-12-14 Seiko Epson Corp Lead frame, semiconductor device and its manufacturing method, circuit board, and electronic equipment
US8618642B2 (en) 2000-12-28 2013-12-31 Renesas Electronics Corporation Semiconductor device
US8581396B2 (en) 2000-12-28 2013-11-12 Renesas Electronics Corporation Semiconductor device
US10490486B2 (en) 2000-12-28 2019-11-26 Renesas Electronics Corporation Semiconductor device
US10115658B2 (en) 2000-12-28 2018-10-30 Renesas Electronics Corporation Semiconductor device
US7911054B2 (en) 2000-12-28 2011-03-22 Renesas Electronics Corporation Semiconductor device
US9496204B2 (en) 2000-12-28 2016-11-15 Renesas Electronics Corporation Semiconductor device
US8044509B2 (en) 2000-12-28 2011-10-25 Renesas Electronics Corporation Semiconductor device
US7518156B2 (en) 2000-12-28 2009-04-14 Renesas Technology Corp. Semiconductor device
US6713849B2 (en) * 2000-12-28 2004-03-30 Hitachi, Ltd. Semiconductor utilizing grooves in lead and tab portions of lead frame to prevent peel off between the lead frame and the resin
US7906859B2 (en) 2007-08-22 2011-03-15 Denso Corporation Semiconductor device
WO2009126367A1 (en) * 2008-04-08 2009-10-15 Freescale Semiconductor Inc. Leadframe for packaged electronic device with enhanced mold locking capability
JP2011114190A (en) * 2009-11-27 2011-06-09 Shindengen Electric Mfg Co Ltd Semiconductor package
DE102014202651A1 (en) 2013-04-02 2014-10-02 Mitsubishi Electric Corporation Semiconductor device and semiconductor module
US9613888B2 (en) 2013-04-02 2017-04-04 Mitsubishi Electric Corporation Semiconductor device and semiconductor module
US20150092379A1 (en) * 2013-09-30 2015-04-02 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same
US10104775B2 (en) * 2013-09-30 2018-10-16 Mitsubishi Electric Corporation Semiconductor device and method for manufacturing the same

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