JPS6037754A - Flat package - Google Patents

Flat package

Info

Publication number
JPS6037754A
JPS6037754A JP58147012A JP14701283A JPS6037754A JP S6037754 A JPS6037754 A JP S6037754A JP 58147012 A JP58147012 A JP 58147012A JP 14701283 A JP14701283 A JP 14701283A JP S6037754 A JPS6037754 A JP S6037754A
Authority
JP
Japan
Prior art keywords
rubber
plastic
lead frame
chip
brass
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58147012A
Other languages
Japanese (ja)
Inventor
Makio Goto
後藤　万亀雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Suwa Seikosha KK
Original Assignee
Seiko Epson Corp
Suwa Seikosha KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, Suwa Seikosha KK filed Critical Seiko Epson Corp
Priority to JP58147012A priority Critical patent/JPS6037754A/en
Publication of JPS6037754A publication Critical patent/JPS6037754A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

PURPOSE:To obtain plastic flat packages of excellent water proof by improvement of adhesionproperty with plastic by the use of a rubber chip. CONSTITUTION:When an Ni lead frame 202 is partly plated with Cu-Zn alloy (brass) and then thermally vulcanized with the rubber chip 206, Cu-S band takes place between the Cu in brass and the S in rubber, and the brass is adhered to the rubber. This lead frame with built-in rubber is joined to the plastic 205 by rubber fusion during molding. Such a construction produces excellent adhesion property because of the direct chemical bond of the lead frame with the rubber chip and the chip with the plastic part, accordingly water proof is improved, and then the plastic flat package of high reliability can be obtained.

Description

【発明の詳細な説明】 〔技術分野〕 本発明はフラットパッケージモールド品の信頼性、特に
耐水性を向上させる構造に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a structure that improves the reliability, particularly water resistance, of a flat package molded product.

〔従来技術〕[Prior art]

従来、半入り体素子Ｃ以下ＩＣチップと略記）を実装す
るパソク−−ジには、セヲミツクバソケージ及びプラス
チックパッケージが利用されてきたが、セラミックは高
価であるため、ブヲスチツクが材料として一般に用いら
れてきた。Traditionally, semiconductor cages and plastic packages have been used to mount semi-contained elements (hereinafter referred to as IC chips), but since ceramics are expensive, wood chips are generally used as materials. I've been exposed to it.

従来第１図に示す如くフラットパッケージはブラスチッ
クパッケージ措造を有していた。同し１において、１０
１はＩＣチップ、Ｊ０２はリードフレーム１，１０３け
金線、１０４はパッド、　１　（１５はブヲスチツクで
ある。Conventionally, flat packages have had a plastic package structure as shown in FIG. In the same 1, 10
1 is an IC chip, J02 is a lead frame 1, 103 is a metal wire, 104 is a pad, 1 (15 is a book stick).

しかしながらこのようなプラスチックパッケージは、信
頼性、特に耐水性が悪いという欠点があった。However, such plastic packages have the drawback of poor reliability, particularly poor water resistance.

ところで、工Ｃチップ中央部には水分の影響による腐食
がなく、パッド部に腐食がみられるため水分の侵入経路
は第１図の矢印方向であると考えられる。By the way, since there is no corrosion due to the influence of moisture in the center of the C chip, and corrosion is observed in the pad portion, it is thought that the path of moisture intrusion is in the direction of the arrow in FIG.

ここでプラスチックパッケージの耐水イてＵの悪さの原
因は、リードフレームとプラスチック部の密着性の恕さ
に起因している。The reason why the plastic package has poor water resistance is due to poor adhesion between the lead frame and the plastic part.

〔発明の目的〕[Purpose of the invention]

本発明はこの欠点を除去するもので、その目的はプラス
チツクフヲットパッケージの信頼性、特に耐水性を向上
させることに°ある。The present invention aims to eliminate this drawback and its purpose is to improve the reliability, especially the water resistance, of plastic foot packages.

本発明によるブヲスチツクフヲットパッケージは、ゴム
片を使うことによシプヲスチックとの密着性を向上させ
てあるとｈう特徴を持つ。The physical packaging according to the present invention is characterized by the use of rubber pieces to improve adhesion to the physical packaging.

〔実施例〕〔Example〕

以下図面により説明する。 This will be explained below with reference to the drawings.

第２図は本発明によるセラミックフラットパッケージで
ある。FIG. 2 shows a ceramic flat package according to the present invention.

同図において、２０１け工Ｃチップ、２０２はリードフ
レーム、２０３は金線、２０４はパッド、２０５はプラ
スチック、２０６はゴム片である。In the figure, 201 is a C-chip, 202 is a lead frame, 203 is a gold wire, 204 is a pad, 205 is a plastic, and 206 is a rubber piece.

ニッケルからなるリードフレーム２０２　Ｕ、ｔｉ１ｍ
ゴム片２０６と熱加硫することにより、真中の銅とゴム
中の％ｆｔ黄の間に０％−８の結合が生じ、真鈴とゴム
は接着される。Lead frame made of nickel 202 U, ti1m
By heat vulcanizing with the rubber piece 206, a 0%-8 bond is created between the copper in the middle and the %ft yellow in the rubber, and the marin and the rubber are bonded.

このようにして形成されたゴム付リードフレームは、成
型時にゴムが溶融しプラスチックと接合される。In the thus formed lead frame with rubber, the rubber is melted and bonded to the plastic during molding.

以上説明したように、リードフレームとゴム片及びゴム
片とプラスチック部は直接化学結合されているため、そ
の密着性はかなシ良いという利点がある。As explained above, since the lead frame and the rubber piece and the rubber piece and the plastic part are directly chemically bonded, there is an advantage that their adhesion is short and good.

このように、リードフレームとプラスチック部の密着性
を向上させることによってリードフレームとプラスチッ
クの密Ｘｉ件を向上することができ、従ってブヲスチツ
クフヲツドパッケージの欠点である耐水性の悪さが解決
され、信頼性が向上する効果を有する。In this way, by improving the adhesion between the lead frame and the plastic part, it is possible to improve the adhesiveness between the lead frame and the plastic, thus solving the problem of poor water resistance, which is a disadvantage of the book stick package. , which has the effect of improving reliability.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のフラットパッケージの断面図、第２図は
本発明のフラットパッケージの断面図である。 １０１・・工Ｃチップ　１０２・−リードフレーム　１
０３・・金線　１０４・・パッド　１０５１プヲスチツ
ク　２０１１工Ｃチツプ　２０２・・リードフレーム　
２０３１１１Ｉ−ｆ：線　２０４ｅ・パッド　２０５・
・プラスチック　２０６・・ゴム片。 以」二FIG. 1 is a sectional view of a conventional flat package, and FIG. 2 is a sectional view of a flat package of the present invention. 101...C chip 102...Lead frame 1
03...Gold wire 104...Pad 1051 Push stick 2011 C chip 202...Lead frame
203111I-f: Line 204e・Pad 205・
・Plastic 206...Rubber piece. I"2

Claims (1)

【特許請求の範囲】[Claims] 半導体素子を実装するフラットパッケージにおいて、一
部を真輸メッキされたリードフレームされ、該メッキ部
はゴム片と接着され、該ゴム片は、プラスチック部き接
合されていることを特徴とするフラットパッケージ。A flat package for mounting a semiconductor element, characterized in that a part of the lead frame is directly plated, the plated part is bonded to a rubber piece, and the rubber piece is bonded to a plastic part. .
JP58147012A 1983-08-10 1983-08-10 Flat package Pending JPS6037754A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58147012A JPS6037754A (en) 1983-08-10 1983-08-10 Flat package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58147012A JPS6037754A (en) 1983-08-10 1983-08-10 Flat package

Publications (1)

Publication Number Publication Date
JPS6037754A true JPS6037754A (en) 1985-02-27

Family

ID=15420549

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58147012A Pending JPS6037754A (en) 1983-08-10 1983-08-10 Flat package

Country Status (1)

Country Link
JP (1) JPS6037754A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265845A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor device
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips
US5289033A (en) * 1990-04-25 1994-02-22 Sony Corporation Packaging of semiconductor chips with resin

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61265845A (en) * 1985-05-20 1986-11-25 Fujitsu Ltd Semiconductor device
US5289033A (en) * 1990-04-25 1994-02-22 Sony Corporation Packaging of semiconductor chips with resin
US5214846A (en) * 1991-04-24 1993-06-01 Sony Corporation Packaging of semiconductor chips

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