JP2005268487A - Manufacturing method of semiconductor device, and manufacturing equipment thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the activation rate of an impurity layer formed in an Si substrate. <P>SOLUTION: At the time of forming a p<SP>+</SP>collector layer of NPT type IGBT using an FZ-N substrate, boron is implanted into the rear face while heating the FZ-N substrate at 400°C-500°C. The ion implantation boron at room temperature is enriched from a shallow domain to a deep domain in accordance with the rise of ion implantation temperature. The activation rate becomes about 2% at the ion implantation temperature of 400°C and becomes about 5% at 500°C, so that a higher activation rate can be obtained than the activation rate of about 1.8% when performing electric furnace annealing of one hour at 400°C after the ion implantation at room temperature. Consequently, the p layer can be activated by the effect of substrate heating, and the excellent p<SP>+</SP>collector layer can be formed. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus, and more particularly, to an IC (Integrated Circuit), a MOS (Metal Oxide Semiconductor), an insulated gate bipolar transistor (hereinafter referred to as “IGBT”), a free hood. The present invention relates to a method for manufacturing a semiconductor element such as a ring diode (hereinafter referred to as “FWD”) and a semiconductor element manufacturing apparatus.

  In recent years, an integrated circuit (IC) in which a large number of transistors, resistors, and the like are connected to form an electric circuit and integrated on one chip is frequently used in important parts of computers and communication devices. Among such ICs, those including power semiconductor elements are called power ICs.

  The IGBT is a power element having high-speed switching of a MOSFET, voltage drive characteristics, and low on-voltage characteristics of a bipolar transistor. IGBTs have been increasingly applied to industrial fields such as general-purpose inverters, AC servos, uninterruptible power supplies (UPS), and switching power supplies, as well as consumer devices such as microwave ovens, rice cookers, and strobes. Development for the next generation is also progressing, and the development of lower on-voltage IGBTs using a new chip structure has led to lower loss and higher efficiency of application devices.

  The structure of the IGBT mainly includes a punch through (PT) type, a non punch through (NPT) type, a field stop (FS) type, and the like. Most IGBTs currently mass-produced have an n-channel vertical double diffusion structure except for a p-channel type for some audio power amplifiers. In the following, unless otherwise indicated, the IGBT is an n-type IGBT.

PT-type IGBT has a structure in which an n ⁺ layer (n buffer layer) is provided between a p ⁺ epitaxial substrate and an n ⁻ layer (n type active layer), and a depletion layer in the n type active layer reaches the n buffer layer It is the mainstream basic structure of IGBT. However, for example, a thickness of about 70 μm is sufficient for an IGBT having a withstand voltage of 600 V, but the total thickness is about 200 μm to 300 μm when the p ⁺ epitaxial substrate portion is included. Therefore, an NPT type IGBT in which a shallow p ⁺ collector layer having a low dose is formed by using an FZ substrate formed by an FZ (Floating Zone) method without using an epitaxial substrate to achieve a reduction in thickness and cost. FS type IGBT has been developed.

FIG. 25 is an example of a cross-sectional structure of an NPT type IGBT.
An NPT type IGBT 100 shown in FIG. 25 has a gate electrode 103 such as polysilicon formed on the surface side of an n ⁻ type FZ substrate (FZ-N substrate) 101 via a gate oxide film 102 such as SiO _2. A surface electrode 105 such as an aluminum / silicon film is formed thereon via an interlayer insulating film 104 such as BPSG (Boro-Phospho Silicate Glass). A p ⁺ base layer 106 and an n ⁺ emitter layer 107 are formed in the p ⁺ base layer 106 on the front side of the FZ-N substrate 101, and a p ⁺ collector layer on the back side of the FZ-N substrate 101. 108 is formed, and several kinds of metal films are laminated thereon to form a back electrode 109.

In the NPT type IGBT 100 having such a configuration, a shallow low implantation p ⁺ collector with a low dose is used for the p ⁺ collector layer 108. In this NPT type IGBT 100, since a p ⁺ epitaxial substrate is not used, the total thickness is significantly thinner than that of the PT type IGBT.

In the NPT structure, since the hole injection rate can be controlled, high-speed switching is possible without performing lifetime control. On the other hand, the ON voltage depends on the thickness and specific resistance of the n-type active layer. Become. Since the FZ substrate is used instead of the p ⁺ epitaxial substrate, the cost of the chip can be reduced.

FIG. 26 shows an example of a cross-sectional structure of an FS type IGBT. However, in FIG. 26, the same elements as those shown in FIG. 25 are denoted by the same reference numerals, and detailed description thereof is omitted.
In the FS type IGBT 200 shown in FIG. 26, like the NPT type IGBT 100, an FZ-N substrate 101 is used instead of the p ⁺ epitaxial substrate, and the total thickness is about 100 μm to 200 μm. As with the PT-type IGBT, the n-type active layer is depleted by setting it to about 70 μm according to the 600V breakdown voltage. Therefore, in the FS type IGBT 200, an n ⁺ layer (n buffer layer) 201 is formed on the back surface of the FZ-N substrate 101, and a p ⁺ collector layer 108 and a back electrode 109 are formed on the n buffer layer 201. . In the FS type IGBT 200, as in the case of the NPT type IGBT 100, lifetime control is unnecessary.

  For the purpose of reducing the on-voltage, there is also a combination of a trench structure IGBT in which a narrow and deep groove is formed on the IGBT surface and a MOS gate is formed on the side surface of the IGBT with the FS structure. Recently, the total thickness has been reduced by optimizing the design.

  Here, an example of an IGBT forming method will be described with reference to FIGS. 27 to 31 by taking the FS type IGBT 200 shown in FIG. 26 as an example. 27 is a cross-sectional view after completion of the surface side process, FIG. 28 is a cross-sectional view of the substrate grinding process, FIG. 29 is a cross-sectional view of the back surface ion implantation process, FIG. 30 is a cross-sectional view of the back surface annealing process, and FIG. It is sectional drawing of a process. However, in FIGS. 27 to 31, the same elements as those shown in FIGS. 25 and 26 are denoted by the same reference numerals, and detailed description thereof will be omitted.

The formation of the FS type IGBT 200 is roughly divided into a front side process and a back side process. First, the surface side process will be described with reference to FIG.
In the surface side process, first, SiO ₂ and polysilicon are deposited on the surface side of the FZ-N substrate 101, and a window process is performed to form the gate oxide film 102 and the gate electrode 103, respectively. Subsequently, BPSG is deposited on the surface, and window processing is performed to form an interlayer insulating film 104. Thereby, an insulated gate structure is formed on the surface side of the FZ-N substrate 101.

Next, a p ⁺ base layer 106 is formed on the surface side of the FZ-N substrate 101, and an n ⁺ emitter layer 107 is formed in the p ⁺ base layer 106. Further, an aluminum / silicon film is deposited so as to be in contact with the n ⁺ emitter layer 107 to form a surface electrode 105 serving as an emitter electrode. The aluminum / silicon film is then heat-treated at a low temperature of about 400 ° C. to 500 ° C. in order to realize stable matching and low resistance wiring.

Although not shown in FIGS. 26 and 27, an insulating protective film is formed on the surface electrode 105 using polyimide or the like so as to cover the surface.
Next, the back side process will be described with reference to FIGS. In the back surface side process, first, as shown in FIG. 28, the FZ-N substrate 101 is ground from the back surface side to a desired thickness by grinding such as back grinding or etching to reduce the thickness of the wafer.

Next, as shown in FIG. 29, after phosphorus (P ⁺ ) and boron (B ⁺ ) are respectively implanted in this order on the back side of the FZ-N substrate 101, an n ⁺ layer 201a and a p ⁺ layer 108a are formed. Then, heat treatment (annealing) is performed at a low temperature of 350 ° C. to 500 ° C. using an electric furnace. As a result, the n ⁺ layer 201a implanted with phosphorus and the p ⁺ layer 108a implanted with boron are activated, and the n buffer layer 201 and the p ⁺ collector are formed on the back surface side of the FZ-N substrate 101 as shown in FIG. Each layer 108 is formed.

Thereafter, as shown in FIG. 31, a back electrode 109 is formed on the surface of the p ⁺ collector layer 108 by combining metal films such as an aluminum layer, a titanium layer, a nickel layer, and a gold layer.
Finally, after dicing into chips, an aluminum wire electrode is fixed to the surface of the front electrode 105 by an ultrasonic wire bonding apparatus, and the back electrode 109 is connected to a predetermined fixing member via a solder layer.

Note that here, a case where phosphorus and boron are sequentially ion-implanted to form the n buffer layer 201 and the p ⁺ collector layer 108 on the back surface side of the FZ-N substrate 101 is shown. In order to secure ohmic contact, boron fluoride (BF ₂ ⁺ ) may be further implanted as a surface contact layer after boron implantation.

  By the way, in recent years, matrix converters that perform direct AC-AC conversion without using direct current are in the spotlight. Unlike the conventional inverter, there is an advantage that a capacitor is unnecessary and power supply harmonics are reduced. However, since the input is AC, the semiconductor switch is required to have a reverse breakdown voltage. When the conventional IGBT is used, it is necessary to connect reverse blocking diodes in series.

FIG. 32 is an example of a cross-sectional structure of the reverse blocking IGBT. However, in FIG. 32, the same elements as those shown in FIG. 25 are denoted by the same reference numerals, and detailed description thereof will be omitted.
As shown in FIG. 32, the reverse blocking IGBT 300 is an IGBT that has the basic performance of the conventional IGBT and further has a p ⁺ isolation layer 301 to have a reverse breakdown voltage. Since the reverse blocking IGBT 300 having such a structure does not require a series diode, the conduction loss can be reduced by half, which greatly contributes to the improvement of the conversion efficiency of the matrix converter. A high-performance reverse-blocking IGBT can be manufactured by combining a technology for forming a deep junction of 100 μm or more and a technology for producing an ultra-thin wafer having a thickness of 100 μm or less.

The flow of manufacturing the reverse blocking IGBT 300 and the NPT type IGBT 100 is the same as that described above except that the n buffer layer is not formed on the back side of the FZ-N substrate 101 and only the p ⁺ collector layer 108 is formed. This is the same as in the case of the FS type IGBT 200. Further, the FWD has no n buffer layer, and the outermost layer on the back side of the substrate is an n ⁺ layer.

  However, when manufacturing IGBTs and FWDs, in order to realize a thin element of about 70 μm, backside back grinding, ion implantation from the backside, backside heat treatment, etc. are required. There are also many technical issues in the process.

  As one of such manufacturing process technologies, activation of a p-type impurity layer (p layer) and an n-type impurity layer (n layer) necessary for forming various semiconductor elements such as IGBTs and FWDs exemplified here. Various techniques have been studied so far, and in addition to those using the electric furnace as described above, there are those that activate the impurity layer by annealing using a laser.

  For example, a wafer is reinforced with an adhesive sheet for preventing cracking, and this is fixed to a support substrate, and an XeCl laser or YAG (Yttrium Aluminum Garnet) laser is irradiated to activate the impurity layer, or YAG is used for activation. A method using a third harmonic of a laser (YAG3ω laser) has been studied (for example, see Patent Document 1).

As another method for activating the impurity layer, a method is proposed in which a predetermined heat treatment is performed after ion implantation is performed while the substrate is cooled or heated (see Non-Patent Document 1). Furthermore, a method of irradiating a low energy beam such as an excimer laser while heating the substrate after ion implantation of the active silicon layer or gate silicon into the semiconductor thin film has been proposed (see, for example, Patent Document 2). ). Furthermore, a method of performing ion implantation while adjusting the substrate temperature and irradiating a laser, and a semiconductor manufacturing apparatus provided with respective mechanisms for substrate heating, laser irradiation, and ion implantation for that purpose have been proposed (for example, Patent Documents). 3, non-patent documents 2 to 4).
Japanese Patent Laid-Open No. 2003-59856 (paragraph numbers [0015] to [0016], FIGS. 6 and 7) Japanese Patent Laid-Open No. 7-222103 (paragraph numbers [0008] to [0009], FIG. 1) JP 2001-196320 A (paragraph numbers [0011] to [0013], FIG. 4) S. M.M. Sze, “VLSI TECHNOLOGY”, McGraw Hill Book Company, p. 246, FIG. 50th Applied Physics Related Conference, Proceedings, March 2003, p. 448, 29a-ZB-6 Hiroshi Sugimoto, 5 others, "Activation annealing of 4H-SiC with high energy Al ion implantation", Society of Applied Physics, SiC and related wide gap semiconductors, November 1998, SiC and related wide gap semiconductors 7th Lecture Program, P15 Masanori Watanabe, 2 others, “Laser simultaneous irradiation ion implantation technology and its application”, Ion Engineering Center / Ion Engineering Laboratory, October 2002, Ion Engineering Center News No. 51, p. 7-9

However, the conventional method has the following problems regarding the activation of the impurity layer in the manufacturing process of various semiconductor elements.
First, when performing furnace annealing or laser annealing after ion implantation at normal room temperature, it is necessary to transport the wafer when shifting from the ion implantation process to the annealing process. Wafer cracks are likely to occur. The possibility that the wafers come into contact with each other and become scratched increases as the number of transports increases, and there may also occur a problem that particles adhere to the wafers during transport. These all cause a reduction in the yield rate of semiconductor elements.

  In order to prevent occurrence of wafer cracking, it is possible to reinforce the wafer with an adhesive sheet. However, since the heat-resistant temperature of the adhesive sheet is usually 200 ° C. or lower, it is difficult to use it particularly for electric furnace annealing, and it cannot be used for electric furnace annealing exceeding the heat-resistant temperature of the adhesive sheet.

  Further, in electric furnace annealing performed after normal ion implantation in a room temperature environment, there is a problem that it is difficult to sufficiently activate the p layer when the p layer or the pn continuous layer is activated. In order to increase the activation of the p layer by electric furnace annealing, a method has been proposed in which ion implantation is performed by adjusting the substrate temperature during ion implantation, and electric furnace annealing is performed at an appropriate temperature after the ion implantation. . However, in the case of this method, depending on the substrate temperature, the adhesive sheet cannot be used, and it may be impossible to prevent wafer cracking. Furthermore, under the activation conditions proposed in the past, a sufficient activation rate has not been obtained because the temperature during ion implantation is low and the heat treatment time after ion implantation is short.

In addition, a method of performing ion implantation while irradiating a laser to a silicon carbide (SiC) substrate or the like whose temperature is adjusted has been proposed, but conventionally, energy is low in order to avoid damage to the substrate by the laser as much as possible, An excimer laser having a small pulse width (half width) is used. For example, an example in which the irradiation energy density on the laser irradiation surface is about 0.46 J / cm ² and the pulse width is about 17 ns has been reported. However, such a low-energy excimer laser alone is difficult to sufficiently activate an impurity layer from a shallow region to a deep region of a silicon (Si) substrate such as an FZ substrate or an epitaxial substrate, and seems to be proposed. A simple SiC substrate process cannot be directly applied to a Si substrate process.

  The present invention has been made in view of these points, and optimizes the substrate temperature conditions, ion implantation conditions, and annealing conditions necessary for forming and activating the impurity layer, and suppressing damage to the substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device capable of effectively activating an impurity layer.

  Another object of the present invention is to provide a semiconductor device manufacturing apparatus that can perform substrate temperature adjustment, ion implantation, and laser irradiation, and can effectively activate an impurity layer.

  In the present invention, in order to solve the above problem, in a method of manufacturing a semiconductor device including a step of activating an impurity layer formed on a Si substrate, the Si substrate is heated to a temperature of 400 ° C. to 500 ° C. There is provided a method for manufacturing a semiconductor device, wherein the impurity layer is activated by ion-implanting impurities into a substrate.

  According to such a method for manufacturing a semiconductor element, since the ion implantation is performed in a state where the Si substrate is set to 400 ° C. to 500 ° C., the impurity layer formed on the Si substrate is activated during the ion implantation due to the substrate heating effect. Become so.

  Furthermore, according to the present invention, in the method for manufacturing a semiconductor device having a step of activating an impurity layer formed on the Si substrate, the wavelength of the Si substrate is set at a temperature of 400 ° C. to 500 ° C. There is provided a method for manufacturing a semiconductor device, wherein the impurity layer is activated by ion implantation of impurities while irradiating a laser pulse of 300 nm to 600 nm.

  According to such a method of manufacturing a semiconductor element, since ion implantation is performed while irradiating a laser pulse having a wavelength of 300 nm to 600 nm with the Si substrate being set to 400 ° C. to 500 ° C., the substrate heating effect and the laser irradiation heating effect are achieved. Thus, the impurity layer formed on the Si substrate is activated at the time of ion implantation.

Furthermore, in the present invention, in a method for manufacturing a semiconductor device having a step of activating an impurity layer formed on a Si substrate, the Si substrate has a wavelength of 300 nm to 600 nm and an irradiation energy density of 0.4 J / cm ² to 1. A method of manufacturing a semiconductor device is provided, wherein the impurity layer is activated by ion-implanting impurities into the Si substrate while irradiating a laser pulse of .4 J / cm ² .

According to the manufacturing method of the semiconductor device, since the ion implantation while irradiating the laser pulse irradiation energy density 0.4J / cm ² ~1.4J / cm ² at a wavelength 300nm~600nm the Si substrate, a laser Due to the irradiation heating effect, the impurity layer formed on the Si substrate is activated during ion implantation.

  Furthermore, in the present invention, in a method of manufacturing a semiconductor element having a step of activating an n-type impurity layer formed on a Si substrate, the temperature of the Si substrate is set to a liquid nitrogen temperature or 200 ° C. to 500 ° C. An n-type impurity is ion-implanted into a Si substrate, and after the n-type impurity is ion-implanted, an electric furnace annealing or laser annealing is performed at a temperature of 350 ° C. to 500 ° C. for a time of 5 hours to 10 hours. A method for manufacturing a semiconductor device is provided, wherein the impurity layer is activated.

  According to such a method of manufacturing a semiconductor element, n-type impurities are ion-implanted with the Si substrate at a liquid nitrogen temperature or 200 ° C. to 500 ° C., and then at 350 ° C. to 500 ° C. for 5 hours to 10 hours. Perform electric furnace annealing or laser annealing. As a result, the Si substrate is given sufficient thermal energy for activating the n-type impurity layer after ion implantation.

According to the present invention, in a semiconductor device manufacturing apparatus that activates an impurity layer formed on a Si substrate, a substrate heating apparatus that heats the Si substrate, and an ion implantation apparatus that ion-implants impurities into the Si substrate; , production of a semiconductor device characterized by having a laser irradiation apparatus having a wavelength irradiation energy density 300nm~600nm irradiating a laser pulse of 0.4J / cm ² ~1.4J / cm ² on the Si substrate An apparatus is provided.

According to such a semiconductor element manufacturing apparatus, the substrate heating apparatus heats the Si substrate, the ion implantation apparatus ion-implants impurities into the Si substrate, the laser irradiation apparatus has a wavelength of 300 nm to 600 nm and an irradiation energy density of 0. irradiating a laser pulse of ^{4J / cm 2 ~1.4J / cm 2} . Since it is possible to laser irradiation apparatus irradiates the laser pulse irradiation energy density ^{0.4J / cm 2 ~1.4J / cm 2} , while suppressing damage to the Si substrate during laser irradiation, the Si substrate Sufficient thermal energy can be applied. Furthermore, according to such a semiconductor element manufacturing apparatus, substrate temperature adjustment, ion implantation, and laser irradiation can be performed with one apparatus.

  In the method for manufacturing a semiconductor device of the present invention, the substrate temperature adjustment, ion implantation and laser irradiation are performed simultaneously or in combination, and by optimizing each processing condition at that time, a p layer formed on the Si substrate, Impurity layers such as an n layer and a pn continuous layer can be effectively activated. As a result, a semiconductor element having good device characteristics can be manufactured.

  In the semiconductor device manufacturing apparatus of the present invention, substrate temperature adjustment, ion implantation, and laser irradiation can be performed with a single device, and the laser irradiation conditions are optimized, so that a semiconductor device with good device characteristics can be efficiently used. Will be able to be manufactured.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, taking as an example the case of application to the manufacture of various semiconductor elements.
First, a first embodiment will be described.

  The semiconductor device manufacturing method according to the first embodiment forms and activates an impurity layer such as a p layer, an n layer, or a pn continuous layer on an Si substrate (including an epitaxial substrate in addition to an FZ substrate). When performing, Si substrate temperature is adjusted to 400 to 500 degreeC, and ion implantation is performed in this state.

The method for manufacturing the semiconductor device of the first embodiment will be specifically described with the following three examples.
First, as a first example, a case where the first embodiment is applied to manufacture of an NPT type IGBT using an FZ-N substrate will be described.

In this case, as is conventional first to form a FZ-N surface insulated gate structure of the substrate, the p ⁺ base layer and the n ⁺ emitter layer was formed on the FZ-N substrate, p ⁺ base layer and n ⁺ A surface electrode in contact with the emitter layer is formed (surface side process). That is, a gate electrode is formed on the surface side of the FZ-N substrate via a gate oxide film, a p ⁺ base layer and an n ⁺ emitter layer are formed in the FZ-N substrate, and the gate electrode is covered. An interlayer insulating film and a surface electrode in contact with the p ⁺ base layer and the n ⁺ emitter layer through the interlayer insulating film are formed. The surface electrode is formed by, for example, forming an aluminum / silicon film and then heat-treating the film at 400 ° C. to 500 ° C.

Next, after the back surface of the FZ-N substrate is ground by back grinding or the like, ion implantation and activation are performed on the back surface of the FZ-N substrate to form a p ⁺ collector layer, and a back electrode is formed thereon as an emitter electrode. (Back side process).

Here, when the p ⁺ collector layer is formed by the back side process, boron is implanted into the back side while the FZ-N substrate is heated to 400 ° C. to 500 ° C. For example, an FZ-N substrate is placed on a sample stage equipped with a substrate heating mechanism such as a heater, with its surface side (side on which the surface electrode is formed) facing down, and heated at a predetermined temperature. Then, boron ions are implanted from the back side of the FZ-N substrate (side where the p ⁺ collector layer is formed).

FIG. 1 shows a concentration profile when boron ion implantation is performed while heating the FZ-N substrate.
In FIG. 1, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the boron concentration (cm ⁻³ ) in the FZ-N substrate. FIG. 1 shows the results when boron is implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² and acceleration energy of 50 keV while the FZ-N substrate is heated at 350 ° C., 400 ° C., and 500 ° C. . For comparison, FIG. 1 also shows the results when only ion implantation is performed at room temperature (27 ° C.). The concentration profile in FIG. 1 is measured by the spreading resistance method (SR method).

  As shown in FIG. 1, the p layer that was not activated only by ion implantation at room temperature was activated as the ion implantation temperature increased to 350 ° C., 400 ° C., and 500 ° C., and the boron concentration in the shallow region was high. Will become more advanced. Furthermore, as the ion implantation temperature rises, boron diffuses into a deep region. Such diffusion of boron in the depth direction is effective because it acts in the direction of lowering the on-voltage of the NPT type IGBT.

  When the p layer is ion-implanted at room temperature and then subjected to electric furnace annealing at 400 ° C. for 1 hour, the activation rate is about 1.8%. On the other hand, when the ion implantation is performed while heating the FZ-N substrate, the activation rate of the p layer is about 2% when the ion implantation temperature by the substrate heating is 400 ° C., and about 5% when the ion implantation temperature is 500 ° C. Thus, a higher activation rate can be obtained as compared with the case where the electric furnace annealing is performed after ion implantation at room temperature.

However, when the ion implantation temperature is lower than 400 ° C., the substrate back surface concentration of the p layer is low, and it becomes difficult to ensure ohmic contact with the back electrode to be formed later. In consideration of ohmic contact with the back electrode, the concentration of the impurity layer (p layer, n layer) on the back surface of the FZ-N substrate is preferably 1 × 10 ¹⁶ cm ⁻³ or more. Further, when the ion implantation temperature exceeds 500 ° C., the surface electrode such as aluminum or silicon is dissolved, and as a result, there is a possibility that necessary insulation cannot be secured in the NPT type IGBT. Absent. The surface electrode may dissolve at 520 ° C.

As in this example, in the backside process of NPT type IGBT manufacturing, boron is ion-implanted while the FZ-N substrate is heated to 400 ° C. to 500 ° C., thereby activating the p layer by the effect of substrate heating. And a good p ⁺ collector layer can be formed.

In addition, in order to secure ohmic contact with the back surface electrode, when forming a p layer by ion implantation of boron fluoride in addition to boron on the back surface of the FZ-N substrate, the FZ-N substrate is heated to 400 ° C. to 500 ° C. In a heated state, boron and boron fluoride are sequentially ion-implanted. In this case as well, a good activation rate can be obtained for the p ⁺ collector layer, and a good ohmic contact can be obtained.

Next, as a second example, a case where the first embodiment is applied to manufacture of an FWD using an FZ-N substrate will be described.
In this case, first, an insulated gate structure is formed on the surface side of the FZ-N substrate, a p ⁺ base layer and an n ⁺ emitter layer are formed in the FZ-N substrate, and is in contact with the p ⁺ base layer and the n ⁺ emitter layer. A surface electrode is formed. Then, after the back surface of the FZ-N substrate is ground by back grinding or the like, ion implantation and activation are performed on the back surface of the FZ-N substrate to form an n layer, and a back electrode is formed thereon. Here, when the n layer is formed by this backside process, phosphorus is implanted into the backside while the FZ-N substrate is heated to 400 ° C to 500 ° C.

FIG. 2 shows a concentration profile when phosphorus ions are implanted while heating the FZ-N substrate.
In FIG. 2, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the phosphorus concentration (cm ⁻³ ) in the FZ-N substrate. FIG. 2 shows the results when phosphorus is implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² and acceleration energy of 50 keV while the FZ-N substrate is heated at 350 ° C., 400 ° C., and 500 ° C. . For comparison, FIG. 2 also shows the results when only ion implantation is performed at room temperature. The concentration profile is measured by the SR method.

  From FIG. 2, the n layer that was not activated only by ion implantation at room temperature was activated as the ion implantation temperature increased to 350 ° C., 400 ° C., and 500 ° C., and phosphorous on the back surface of the FZ-N substrate was activated. The concentration increases.

  However, when the ion implantation temperature is lower than 400 ° C., the surface concentration of the n layer is low, and it becomes difficult to ensure ohmic contact with the back electrode. Further, when the ion implantation temperature exceeds 500 ° C., the surface electrode is dissolved, and there may be a problem that necessary insulation cannot be secured in the FWD.

  As in this example, in FWD manufacturing, by implanting phosphorus ions in a state where the FZ-N substrate is heated to 400 ° C. to 500 ° C., the n layer can be activated by the effect of substrate heating. An n layer can be formed.

Subsequently, as a third example, a case where the first embodiment is applied to manufacture of an FS type IGBT using an FZ-N substrate will be described.
In this case, first, an insulated gate structure is formed on the surface side of the FZ-N substrate, a p ⁺ base layer and an n ⁺ emitter layer are formed in the FZ-N substrate, and is in contact with the p ⁺ base layer and the n ⁺ emitter layer. A surface electrode is formed. Then, after grinding the back surface of the FZ-N substrate by back grinding or the like, ion implantation and activation are performed on the back surface of the FZ-N substrate to form a continuous layer of p layer and n layer, and a back electrode is formed thereon. . Here, when the pn continuous layer is formed by this backside process, phosphorus and boron are sequentially injected into the backside while the FZ-N substrate is heated to 400 ° C to 500 ° C.

FIG. 3 shows a concentration profile when phosphorus and boron ions are implanted while heating the FZ-N substrate.
In FIG. 3, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the concentration (cm ⁻³ ) of phosphorus and boron in the FZ-N substrate. In FIG. 3, the FZ-N substrate is heated at 350 ° C., 400 ° C., and 500 ° C., and phosphorus is first implanted at a dose of 1 × 10 ¹³ cm ⁻² and an acceleration energy of 240 keV. The results are shown when boron is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. For comparison, FIG. 3 also shows the results when only phosphorus and boron ions are implanted at room temperature. The concentration profile is measured by the SR method.

  From FIG. 3, the n layer and the p layer, which were not activated only by ion implantation at room temperature, were activated as the ion implantation temperature increased to 350 ° C., 400 ° C., and 500 ° C., and the FZ-N substrate The concentration of boron in a shallow region and phosphorus in a deep region are increased.

  When the pn continuous layer is subjected to electric furnace annealing at 400 ° C. for 1 hour after ion implantation at room temperature, the activation rate of the p layer at that time is about 0.5%. On the other hand, when the ion implantation is performed while heating the FZ-N substrate, the activation rate of the p layer is about 1% when the ion implantation temperature is 400 ° C. and about 5% when the ion implantation temperature is 500 ° C. As described above, a higher activation rate can be obtained as compared with the case where the electric furnace annealing is performed after ion implantation at room temperature. Similarly, for the activation rate of the n layer, by performing ion implantation while heating the FZ-N substrate, a higher activation rate can be obtained than when performing electric furnace annealing after ion implantation.

  However, when the ion implantation temperature is lower than 400 ° C., the n layer and the p layer cannot be sufficiently activated. When the ion implantation temperature is higher than 500 ° C., the surface electrode is dissolved and the FS is dissolved. There may be a problem that necessary insulation cannot be secured in the type IGBT.

  As in this example, in the manufacture of FS type IGBT, both the n layer and the p layer are activated by the effect of substrate heating by ion implantation of phosphorus and boron while the FZ-N substrate is heated to 400 ° C. to 500 ° C. And a good pn continuous layer can be formed.

  In the first to third examples in the first embodiment, the case where the FZ-N substrate is used has been described. However, the same result can be obtained when the epitaxial substrate is used. In that case, the manufacturing process of each semiconductor element is appropriately changed accordingly.

  As described above, in the first embodiment, by heating the Si substrate at a predetermined temperature at the time of ion implantation, the impurity layer can be activated while performing the ion implantation, and p formed in various semiconductor elements. The layer, the n layer, and the pn continuous layer can be effectively activated. This also eliminates the need for an electric furnace annealing step and a laser annealing step after ion implantation. If annealing after ion implantation is no longer necessary, there is no need to shift to the annealing process, for example, transfer the wafer to an electric furnace annealing cassette or transfer the wafer to the processing chamber. -It becomes possible to reduce the occurrence of scratches and particle adhesion.

  Further, the semiconductor element manufacturing method of the first embodiment is a substrate heating apparatus provided with an appropriate heating mechanism in which an existing ion implantation apparatus is heated with a heater from the side opposite to the ion irradiation surface thereof. And can be easily introduced into a conventional ion implantation process.

Next, a second embodiment will be described.
In the method of manufacturing a semiconductor device according to the second embodiment, when forming and activating a p layer, an n layer, or a pn continuous layer on a Si substrate, the temperature of the Si substrate is adjusted to 400 ° C. to 500 ° C. In this state, ion implantation is performed while irradiating a laser. As a laser to irradiate, a laser with a wavelength of 300 nm to 600 nm that is well absorbed by the Si substrate can be used. If the wavelength is shorter than 300 nm, the deep region of the Si substrate (for example, the thickness of the FZ-N substrate is about 630 μm) may not be activated. If the wavelength is longer than 600 nm, the laser penetrates the Si substrate and is active. This is because there is a case where the conversion does not occur.

The method for manufacturing the semiconductor device of the second embodiment will be specifically described with the following three examples.
First, as a first example, a case where the second embodiment is applied to manufacture of an NPT type IGBT using an FZ-N substrate will be described.

In this case, when forming the p ⁺ collector layer on the back surface of the FZ-N substrate in the back surface side process, boron is irradiated while irradiating a laser of a predetermined wavelength on the back surface while the FZ-N substrate is heated to 400 ° C. to 500 ° C. Inject. For example, the FZ-N substrate is placed on a sample stage equipped with a heating mechanism, and the front side of the FZ-N substrate is heated at a predetermined temperature. Ion implantation is performed.

FIG. 4 shows a concentration profile when boron ion implantation is performed while irradiating a laser while heating the FZ-N substrate.
In FIG. 4, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the boron concentration (cm ⁻³ ) in the FZ-N substrate. In FIG. 4, a pulse of a XeCl laser (wavelength 308 nm, half width 50 ns) is irradiated at an irradiation energy density of 0.6 J / cm ² on the back surface while the FZ-N substrate is heated at 350 ° C., 400 ° C., and 500 ° C. However, the results are shown when boron is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. For comparison, FIG. 4 also shows the results when only ion implantation is performed at room temperature. The concentration profile is measured by the SR method.

  From FIG. 4, the p layer that was not activated only by ion implantation at room temperature was also obtained by performing ion implantation while heating the FZ-N substrate at 350 ° C., 400 ° C., and 500 ° C. and irradiating the XeCl laser. As the ion implantation temperature rises, it is activated and the concentration of boron in a shallow region is increased. In addition, activation proceeds to a deeper region as compared to the case where the XeCl laser is not irradiated as in the first embodiment (first example) (see FIG. 1).

However, when the ion implantation temperature is lower than 400 ° C., the surface concentration of the p layer is low, and when it is higher than 500 ° C., the surface electrode may be dissolved.
As in this example, in the NPT type IGBT manufacturing, boron is ion-implanted while irradiating the XeCl laser while the FZ-N substrate is heated to 400 ° C. to 500 ° C., thereby adding the effect of heating the substrate by laser irradiation. , The p layer can be effectively activated.

  In addition, when forming a p layer by ion-implanting boron fluoride in addition to boron on the back surface of the FZ-N substrate, boron is irradiated while irradiating the XeCl laser with the FZ-N substrate heated to 400 ° C. to 500 ° C. And boron fluoride are sequentially implanted.

Subsequently, as a second example, a case where the second embodiment is applied to manufacture of an FWD using an FZ-N substrate will be described.
In this case, when forming the n layer on the back surface of the FZ-N substrate by the back surface side process, phosphorus is injected while irradiating the back surface with a laser having a predetermined wavelength while the FZ-N substrate is heated to 400 ° C. to 500 ° C. To do.

FIG. 5 is a concentration profile when the ion implantation of phosphorus is performed while irradiating a laser while heating the FZ-N substrate.
In FIG. 5, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the phosphorus concentration (cm ⁻³ ) in the FZ-N substrate. In FIG. 5, a pulse of a XeCl laser (wavelength: 308 nm, half width: 50 ns) is irradiated at an irradiation energy density of 0.6 J / cm ² on the back surface with the FZ-N substrate heated at 350 ° C., 400 ° C., and 500 ° C. However, the results are shown when phosphorus is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. For comparison, FIG. 5 also shows the results when only ion implantation is performed at room temperature. The concentration profile is measured by the SR method.

  As shown in FIG. 5, the n-layer that was not activated only by room-temperature ion implantation is ion-implanted by heating the FZ-N substrate at 350 ° C., 400 ° C., and 500 ° C. and irradiating the XeCl laser. As the implantation temperature rises, it is activated and the concentration of phosphorus in a shallow region is increased. Further, the diffusion proceeds to a deeper region as compared with the case where the XeCl laser is not irradiated as in the first embodiment (second example) (see FIG. 2).

  However, when the ion implantation temperature is lower than 400 ° C., the surface concentration of the n layer is low and the diffusion in the depth direction is small. Further, when the ion implantation temperature exceeds 500 ° C., the surface electrode may be dissolved.

  As in this example, in the FWD manufacturing, phosphorus is ion-implanted while irradiating the XeCl laser while the FZ-N substrate is heated to 400 ° C. to 500 ° C., thereby adding the effect of heating the substrate by laser irradiation. The layer can be activated effectively.

Subsequently, as a third example, a case where the second embodiment is applied to the manufacture of an FS type IGBT using an FZ-N substrate will be described.
In this case, when the pn continuous layer is formed on the back surface of the FZ-N substrate by the back surface side process, the FZ-N substrate is heated to 400 ° C. to 500 ° C. while irradiating the back surface with a laser having a predetermined wavelength. Inject boron in order.

FIG. 6 shows a concentration profile when phosphorus and boron ions are implanted while the FZ-N substrate is heated and irradiated with laser.
In FIG. 6, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the phosphorus and boron concentrations (cm ⁻³ ) in the FZ-N substrate. In FIG. 6, the FZ-N substrate was heated at 350 ° C., 400 ° C., and 500 ° C., and the back surface was irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. However, first, phosphorus is implanted at a dose of 1 × 10 ¹³ cm ⁻² and an acceleration energy of 240 keV, and then boron is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. Yes. For comparison, FIG. 6 also shows the results when only phosphorus and boron ions are implanted at room temperature. The concentration profile is measured by the SR method.

  As shown in FIG. 6, the n layer and the p layer, which were not activated only by ion implantation at room temperature, are also implanted by irradiating the XeCl laser while heating the FZ-N substrate at 350 ° C., 400 ° C., and 500 ° C. As the ion implantation temperature is increased, the activation is performed, and the concentration of boron in the shallow region and phosphorus in the deep region of the FZ-N substrate are increased. As in the first embodiment (third example), diffusion proceeds to a deeper region as compared with the case where the XeCl laser is not irradiated (see FIG. 3).

  However, when the ion implantation temperature is lower than 400 ° C., the n layer and the p layer cannot be sufficiently activated, and when the ion implantation temperature is higher than 500 ° C., the surface electrode is dissolved. There is.

  As in this example, in the production of FS type IGBT, the effect of heating the substrate by laser irradiation can be obtained by injecting phosphorus and boron while irradiating the XeCl laser while the FZ-N substrate is heated to 400 ° C. to 500 ° C. In addition, the pn continuous layer can be effectively activated.

  In the first to third examples of the second embodiment, the case where the FZ-N substrate is used has been described. However, the same result can be obtained when the epitaxial substrate is used. In the second embodiment, a YAG laser can be used instead of the XeCl laser.

  Thus, in the second embodiment, the impurity layer can be activated while performing ion implantation by heating the Si substrate at a predetermined temperature and irradiating a predetermined laser during ion implantation. Thus, the p layer, the n layer, and the pn continuous layer formed in various semiconductor elements can be effectively activated. This is particularly effective for activating deep regions. This also eliminates the need for an electric furnace annealing step and a laser annealing step after ion implantation, thereby reducing the occurrence of wafer cracks and scratches and particle adhesion.

Next, a third embodiment will be described.
In the method of manufacturing a semiconductor device according to the third embodiment, when forming and activating a p layer, an n layer, or a pn continuous layer on a Si substrate, the wavelength is 300 nm to 600 nm, and the irradiation energy density is 1.4 J /. Ion implantation is performed while irradiating a laser pulse of cm ² or less.

The method for manufacturing the semiconductor device of the third embodiment will be specifically described with the following three examples.
First, as a first example, a case where the third embodiment is applied to manufacture of an NPT type IGBT using an FZ-N substrate will be described.

In this case, when forming the p ⁺ collector layer on the back surface of the FZ-N substrate in the back surface side process, boron is implanted while irradiating the FZ-N substrate back surface with a laser having a predetermined wavelength and irradiation energy density.

FIG. 7 is a concentration profile when boron ion implantation is performed while irradiating a laser.
In FIG. 7, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the boron concentration (cm ⁻³ ) in the FZ-N substrate. In FIG. 7, while irradiating the back of the FZ-N substrate with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 1.35 J / cm ² , the dose of boron is 1 × 10 ¹⁵ cm ⁻² , The result is shown when implantation is performed at an acceleration energy of 50 keV. For comparison, FIG. 7 also shows the results when only ion implantation is performed at room temperature and the results when electric furnace annealing is performed at 400 ° C. for 5 hours (hr) after the ion implantation. The concentration profile is measured by the SR method.

From FIG. 7, the activation of the p layer that has not been activated only by ion implantation at room temperature is also advanced by electric furnace annealing. The activation rate of the p layer at this time is about 3%. On the other hand, when ion implantation is performed while irradiating a XeCl laser at an irradiation energy density of 1.35 J / cm ² , the p-layer can be made higher in concentration, and the activation rate at this time is about 50 %become.

Above in the example described in the second embodiment has been irradiated with XeCl laser with irradiation energy density ^{0.6J / cm 2, 1.35J / cm} 2 irradiation energy density as in the third embodiment As a result, the p layer can be sufficiently activated without performing substrate heating during ion implantation and annealing after ion implantation.

As in this example, in NPT type IGBT manufacturing, by injecting boron while irradiating the back surface of the FZ-N substrate with XeCl laser having a wavelength of 308 nm and an irradiation energy density of 1.35 J / cm ² , The p-layer can be effectively activated by the effect.

However, when the irradiation energy density of the XeCl laser at the time of ion implantation exceeds 1.4 J / cm ² , the XeCl laser processing trace remains on the back surface of the FZ-N substrate and is removed before forming the back electrode. Since another processing may be required, the irradiation energy density of the XeCl laser is preferably 1.4 J / cm ² or less.

Note that when boron fluoride is also ion-implanted, boron and boron fluoride may be sequentially ion-implanted while irradiating a laser.
Subsequently, as a second example, a case where the third embodiment is applied to manufacture of an FWD using an FZ-N substrate will be described.

In this case, when the n layer is formed on the back surface of the FZ-N substrate in the back surface side process, phosphorus is implanted while irradiating the FZ-N substrate back surface with laser pulses having a predetermined wavelength and irradiation energy density.
FIG. 8 shows a concentration profile when phosphorus ions are implanted while irradiating a laser.

In FIG. 8, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the phosphorus concentration (cm ⁻³ ) in the FZ-N substrate. In FIG. 8, while the pulse of the XeCl laser (wavelength 308 nm, half width 50 ns) is irradiated on the back surface of the FZ-N substrate at an irradiation energy density of 1.35 J / cm ² , phosphorus is dosed at 1 × 10 ¹⁵ cm ⁻² , The result is shown when implantation is performed at an acceleration energy of 50 keV. For comparison, FIG. 8 also shows the results when only ion implantation is performed at room temperature and the results when electric furnace annealing is performed at 400 ° C. for 5 hours after the ion implantation. The concentration profile is measured by the SR method.

From FIG. 8, the n layer that was not activated only by ion implantation at room temperature is activated by the electric furnace annealing. At this time, the activation rate of the n layer is about 1%. On the other hand, when the ion implantation is performed while irradiating the XeCl laser at the irradiation energy density of 1.35 J / cm ² , the n layer can be further concentrated, and the activation rate at this time is about 40 %become.

Thus, by setting the irradiation energy density to 1.35 J / cm ² , the n layer can be sufficiently activated without performing substrate heating during ion implantation and annealing after ion implantation.

As in this example, in FWD manufacturing, by injecting phosphorus while irradiating the back of the FZ-N substrate with XeCl laser having a wavelength of 308 nm and an irradiation energy density of 1.35 J / cm ² , the effect of substrate heating by laser irradiation The n layer can be activated effectively.

Although not shown here, as a third example, similarly to the activation of the pn continuous layer, phosphorus and boron are sequentially injected while irradiating a XeCl laser having an irradiation energy density of 1.35 J / cm ^2. Thus, both the n layer and the p layer can be effectively activated by the effect of heating the substrate by laser irradiation.

  In the first to third examples of the third embodiment, the case where the FZ-N substrate is used is described. However, the same result is obtained when the epitaxial substrate is used. By the method described in the embodiment, the p layer, the n layer, and the pn continuous layer can be effectively activated. In the third embodiment, a YAG laser can be used instead of the XeCl laser.

In addition, if the irradiation energy density of the laser pulse at the time of ion implantation is 0.4 J / cm ² or more, a suitable laser irradiation method, for example, a plurality of laser irradiation apparatuses can be used to continuously irradiate a plurality of pulses or laser It is possible to activate the p layer, the n layer, and the pn continuous layer by increasing the overlap ratio of the area irradiated with.

  Thus, by irradiating laser pulses with a predetermined wavelength and irradiation energy density during ion implantation into the Si substrate, the impurity layer can be activated while performing ion implantation, heating the Si substrate during ion implantation, and ion implantation. A subsequent annealing step is not necessary.

Next, a fourth embodiment will be described.
The semiconductor device manufacturing method of the fourth embodiment is the same as that of the first, second, and third embodiments when forming and activating the p layer, the n layer, or the pn continuous layer on the Si substrate. After the ion implantation described above, low temperature electric furnace annealing at 350 ° C. to 500 ° C. is further performed.

Next, a method for manufacturing the semiconductor device of the fourth embodiment will be specifically described.
FIG. 9 shows a concentration profile when an electric furnace annealing is performed after boron ion implantation is performed while the FZ-N substrate is heated, and FIG. 10 shows electricity after phosphorous ion implantation is performed while the FZ-N substrate is heated. FIG. 11 shows a concentration profile when furnace annealing is performed, and FIG. 11 shows a concentration profile when electric furnace annealing is performed after ion implantation of phosphorus and boron while heating the FZ-N substrate.

9 to 11, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the concentration of boron or / and phosphorus (cm ⁻³ ) in the FZ-N substrate. . All concentration profiles are measured by the SR method.

In FIG. 9, after the FZ-N substrate is heated at 400 ° C. and 500 ° C., boron is implanted on the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, and then the electricity is further applied at 400 ° C. for 5 hours. The result when furnace annealing is performed is shown. FIG. 9 also shows the result when only ion implantation is performed at room temperature and the result when this electric furnace annealing is not performed (FIG. 1).

In FIG. 10, after the FZ-N substrate is heated at 400 ° C. and 500 ° C., phosphorus is implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, and then at 400 ° C. for 5 hours. The result when furnace annealing is performed is shown. FIG. 10 also shows the result when only ion implantation is performed at room temperature and the result when this electric furnace annealing is not performed (FIG. 2).

In FIG. 11, the FZ-N substrate is heated at 400 ° C. and 500 ° C., phosphorus is first implanted at a dose of 1 × 10 ¹³ cm ⁻² and acceleration energy of 240 keV, and then boron is dosed at 1 ×. The results are shown when electric furnace annealing is further performed at 400 ° C. for 5 hours after implantation at 10 ¹⁵ cm ⁻² and acceleration energy of 50 keV. FIG. 11 also shows the result when only ion implantation is performed at room temperature and the result when this electric furnace annealing is not performed (FIG. 3).

  9 to 11, as described in the first embodiment, the ion implantation is performed while heating the FZ-N substrate, and then the electric furnace annealing is performed to further p layer, n layer, and pn continuous layer. Can be activated more.

  FIG. 12 shows the concentration profile when annealing the electric furnace after performing ion implantation of boron while heating the FZ-N substrate and irradiating the laser. FIG. 13 shows the concentration profile when the FZ-N substrate is heated. FIG. 14 shows the concentration profile when the electric furnace annealing is performed after the phosphorus ion implantation is performed. FIG. 14 shows the electric furnace after the phosphorus and boron ions are implanted while the FZ-N substrate is heated and irradiated with the laser. It is a density | concentration profile when annealing is performed.

12 to 14, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the concentration of boron or / and phosphorus (cm ⁻³ ) in the FZ-N substrate. . All concentration profiles are measured by the SR method.

FIG. 12 shows that while the FZ-N substrate is heated at 400 ° C. and 500 ° C., the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. The results are shown in the case where an electric furnace annealing is further carried out at 400 ° C. for 5 hours after implantation at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. FIG. 12 also shows the results when only ion implantation is performed at room temperature and the results when this electric furnace annealing is not performed (FIG. 4).

In FIG. 13, while the FZ-N substrate is heated at 400 ° C. and 500 ° C., the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. The results are shown in the case where an electric furnace annealing is further carried out at 400 ° C. for 5 hours after implantation at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV. FIG. 13 also shows the results when only ion implantation is performed at room temperature and the results when this electric furnace annealing is not performed (FIG. 5).

In FIG. 14, while the FZ-N substrate is heated at 400 ° C. and 500 ° C., the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. Phosphorus is implanted at a dose of 1 × 10 ¹³ cm ⁻² and an acceleration energy of 240 keV, then boron is implanted at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, followed by further electric furnace annealing at 400 ° C. for 5 hours. Shows the results when FIG. 14 also shows the result when only ion implantation is performed at room temperature and the result when this electric furnace annealing is not performed (FIG. 6).

  From FIG. 12 to FIG. 14, as described in the second embodiment, after performing ion implantation while irradiating a laser in a state where the FZ-N substrate is heated, electric furnace annealing is further performed to form a p layer, The n layer and the pn continuous layer can be further activated.

Further, same applies to the case where a third ion implantation while irradiating the laser pulse irradiation at a wavelength 300nm~600nm as described in the embodiments the energy density of ^{0.4J / cm 2 ~1.4J / cm 2} , By performing electric furnace annealing after the ion implantation, the p layer, the n layer, and the pn continuous layer can be further activated.

  Further, the temperature of the electric furnace annealing is not limited to 400 ° C. exemplified here, and the same result is obtained if it is in the range of 350 ° C. to 500 ° C., which is effective for activating the impurity layer. When the temperature of the electric furnace annealing is lower than 350 ° C., the temperature is too low to sufficiently activate, and when it exceeds 500 ° C., the surface electrode may be dissolved.

In the fourth embodiment, similar results can be obtained when an epitaxial substrate is used, and a YAG laser can be used instead of the XeCl laser.
As described above, in the method for manufacturing a semiconductor device according to the fourth embodiment, although the operation and the annealing time for the electric furnace annealing process are added to the manufacturing method according to the first to third embodiments, each embodiment is described. As compared with the case of using this manufacturing method, the impurity layer can be more activated.

Next, a fifth embodiment will be described.
In the method of manufacturing a semiconductor device of the fifth embodiment, when the p layer, the n layer or the pn continuous layer is formed and activated on the Si substrate, the ions described in the first to third embodiments are used. Laser annealing is performed by further irradiating a laser after the implantation. For this laser annealing, for example, a YAG2ω laser (wavelength: 532 nm, half-value width: 100 ns) can be used, and one or two or more laser irradiation apparatuses are used, and an appropriate irradiation energy density (when two or more laser irradiation apparatuses are used). In this case, the Si substrate is irradiated with a laser pulse at a total irradiation energy density of pulses irradiated by each apparatus and an appropriate delay time between the pulses.

Next, a method for manufacturing the semiconductor device of the fifth embodiment will be specifically described.
FIG. 15 shows a concentration profile when laser annealing is performed after boron ion implantation is performed while the FZ-N substrate is heated, and FIG. 16 shows laser annealing after phosphorous ion implantation is performed while the FZ-N substrate is heated. FIG. 17 is a concentration profile when laser annealing is performed after ion implantation of phosphorus and boron while heating the FZ-N substrate.

15 to 17, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the concentration of boron or / and phosphorus (cm ⁻³ ) in the FZ-N substrate. . All concentration profiles are measured by the SR method.

In FIG. 15, after the FZ-N substrate is heated at 400 ° C., boron is implanted at the back surface with a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, and then a YAG 2ω laser (wavelength 532 nm, half width 100 ns). These results are shown when laser annealing is performed by irradiating the above pulses with a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns. FIG. 15 also shows the results when only ion implantation is performed at room temperature and the results when this laser annealing is not performed (FIG. 1).

In FIG. 16, after the FZ-N substrate is heated at 400 ° C., phosphorus is implanted into the back surface at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, and then a YAG 2ω laser (wavelength 532 nm, half width 100 ns). These results are shown when laser annealing is performed by irradiating the above pulses with a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns. FIG. 16 also shows the result when only ion implantation is performed at room temperature and the result when this laser annealing is not performed (FIG. 2).

In FIG. 17, phosphorus is first implanted at a dose of 1 × 10 ¹³ cm ⁻² and an acceleration energy of 240 keV on the back surface of the FZ-N substrate heated at 400 ° C., and then boron is dosed at 1 × 10 ¹⁵ cm. ^-2 , when laser annealing was performed by irradiating a pulse of YAG2ω laser (wavelength of 532 nm, half-value width of 100 ns) with a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns after implantation at an acceleration energy of 50 keV Shows the results. FIG. 17 also shows the result when only ion implantation is performed at room temperature and the result when this laser annealing is not performed (FIG. 3).

  As shown in FIGS. 15 to 17, as described in the first embodiment, after performing ion implantation while heating the FZ-N substrate, laser annealing is performed to obtain a p layer, an n layer, and a pn continuous layer. For example, the activation rate is 56% in the p layer and 51% in the n layer, and the activation rate exceeds 50%.

  FIG. 18 shows a concentration profile when laser annealing is performed after boron ion implantation is performed while the FZ-N substrate is heated and irradiated with a laser, and FIG. 19 shows that the FZ-N substrate is heated and irradiated with a laser. FIG. 20 shows the concentration profile when laser annealing is performed after phosphorus ion implantation while FIG. 20 shows laser annealing after ion implantation of phosphorus and boron while irradiating the laser while heating the FZ-N substrate. It is a density profile at the time.

18 to 20, the horizontal axis represents the depth (μm) from the back surface of the FZ-N substrate, and the vertical axis represents the concentration of boron or / and phosphorus (cm ⁻³ ) in the FZ-N substrate. . All concentration profiles are measured by the SR method.

In FIG. 18, while the FZ-N substrate is heated at 400 ° C., the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ² , and the dose of boron is shown. After injection at 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, the laser is further irradiated with a YAG2ω laser (wavelength 532 nm, half width 100 ns) pulse at a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns. The result when annealing is performed is shown. FIG. 18 also shows the results when only ion implantation is performed at room temperature and the results when this laser annealing is not performed (FIG. 4).

In FIG. 19, the FZ-N substrate is heated at 400 ° C., and the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. After injection at 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, the laser is further irradiated with a YAG2ω laser (wavelength 532 nm, half width 100 ns) pulse at a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns. The result when annealing is performed is shown. FIG. 19 also shows the results when only ion implantation is performed at room temperature and the results when this laser annealing is not performed (FIG. 5).

In FIG. 20, while the FZ-N substrate is heated at 400 ° C., the back surface is irradiated with a pulse of XeCl laser (wavelength 308 nm, half width 50 ns) at an irradiation energy density of 0.6 J / cm ^2. Implanted at a dose of 1 × 10 ¹³ cm ⁻² and an acceleration energy of 240 keV, then boron was injected at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 50 keV, and then a YAG2ω laser (wavelength 532 nm, half width 100 ns) pulse. Shows the results when laser annealing is performed by irradiation with a total irradiation energy density of 2.8 J / cm ² and a delay time of 300 ns. FIG. 20 also shows the results when only ion implantation is performed at room temperature and the results when this laser annealing is not performed (FIG. 6).

  18 to 20, as described in the second embodiment, after performing ion implantation while irradiating a laser while the FZ-N substrate is heated, laser annealing is further performed to form a p layer, n The layer and the pn continuous layer can be further activated, for example, 78% for the p layer and 90% for the n layer, and the activation rate exceeds 70%.

Further, same applies to the case where a third ion implantation while irradiating the laser pulse irradiation at a wavelength 300nm~600nm as described in the embodiments the energy density of ^{0.4J / cm 2 ~1.4J / cm 2} , By performing electric furnace annealing after the ion implantation, the p layer, the n layer, and the pn continuous layer can be further activated.

When laser annealing is performed using a YAG2ω laser as in the fifth embodiment, it is preferable to use a plurality of laser irradiation devices with a lower irradiation energy density per laser irradiation device. . For example, a pulse with an irradiation energy density of 1.4 J / cm ² is continuously irradiated using two laser irradiation apparatuses, thereby ensuring a total irradiation energy density of 2.8 J / cm ² (double pulse irradiation). . At that time, irradiation is performed with a delay time between two pulses of 300 ns as described above, for example. According to such a laser irradiation method, the irradiation energy density required for annealing can be ensured and the irradiation energy density per pulse can be kept low to prevent the formation of processing marks on the FZ-N substrate. It becomes possible.

  In the fifth embodiment, the case of the p layer, the n layer, and the pn continuous layer is illustrated. However, the pp continuous layer in which the p layer is continuously formed and the nn continuous layer in which the n layer is continuously formed. The present invention can also be applied to a case where activation is required up to a deep region, such as an Ar layer in which Ar and Si are ion-implanted, or a continuous layer of an Si layer and a p layer or an n layer. Although the case where ion implantation is performed in a state where the FZ-N substrate is heated at 400 ° C. is shown here, the same result can be obtained when the ion implantation is performed at 500 ° C.

  Further, in the fifth embodiment, the same result is obtained when an epitaxial substrate is used, and a YAG laser can be used instead of a XeCl laser, or a XeCl laser can be used instead of a YAG laser. Is possible.

Next, a sixth embodiment will be described.
In the method of manufacturing a semiconductor device according to the sixth embodiment, when forming and activating an n layer on a Si substrate, the Si substrate is maintained at a liquid nitrogen temperature (−196 ° C.) or 200 ° C. to 500 ° C. After the implantation, low temperature electric furnace annealing or laser annealing at 350 ° C. to 500 ° C. is performed.

The semiconductor element manufacturing method of the sixth embodiment will be specifically described by taking as an example a case where it is applied to manufacture of an FWD using an FZ-N substrate.
In this case, when forming the n layer on the back surface of the FZ-N substrate by the back surface side process, phosphorus is kept in a state where the FZ-N substrate is maintained at a predetermined temperature of liquid nitrogen temperature, room temperature, 200 ° C., 400 ° C. or 500 ° C. After implantation at a dose of 1 × 10 ¹⁵ cm ⁻² and an acceleration energy of 45 keV, electric furnace annealing or laser annealing is performed. The electric furnace annealing is performed at a temperature of 400 ° C. for 1, 5, or 10 hours. Laser annealing is performed by using a YAG2ω laser (wavelength: 532 nm, half-value width: 100 ns) using two laser irradiation devices with a total irradiation energy density of 2.8 J / cm ² and pulses irradiated from each laser irradiation device. Irradiation is performed so that the delay time is 300 ns. The concentration profile at this time is measured by the SR method.

FIG. 21 is a diagram showing the ion implantation temperature dependence of the peak concentration of the concentration profile.
In FIG. 21, the horizontal axis represents the ion implantation temperature (° C.), and the vertical axis represents the peak concentration (cm ⁻³ ) of the phosphorus concentration profile.

  FIG. 21 shows that when electric furnace annealing at 400 ° C. is performed after phosphorus implantation at each ion implantation temperature, the peak concentration is obtained when the ion implantation temperature is room temperature regardless of the annealing time (1, 5, 10 hours). The peak concentration is higher at other ion implantation temperatures than at room temperature. Further, as the annealing time becomes longer, the peak concentration at each ion implantation temperature increases.

In FWD, in order to ensure ohmic contact with the back electrode, it is desirable that the peak concentration of the n layer is ideally 1 × 10 ¹⁹ cm ⁻³ . In order to obtain this peak concentration, electric furnace annealing at 400 ° C. for 1 hour is not sufficient regardless of the ion implantation temperature, the ion implantation temperature is liquid nitrogen temperature or 200 ° C. to 500 ° C., and 5 at 400 ° C. It can be seen that an hour or 10 hour electric furnace anneal is required.

  In addition, when laser annealing with a YAG2ω laser is performed after phosphorus implantation at each ion implantation temperature, a high peak concentration can be obtained regardless of the ion implantation temperature. Use of a YAG2ω laser has an advantage that a peak concentration equal to or higher than that of electric furnace annealing at 400 ° C. for 5 hours can be obtained within a few ns order.

  The annealing temperature of the electric furnace annealing is exemplified here at 400 ° C. However, if the temperature is in the range of 350 ° C. to 500 ° C., the same result is obtained, which is effective for activating the impurity layer. When the electric furnace annealing temperature is lower than 350 ° C., sufficient activation cannot be achieved, and when it exceeds 500 ° C., the surface electrode may be dissolved. Further, if the annealing time is 5 hours or more, a desirable peak concentration can be obtained. However, if the annealing time exceeds 10 hours, the peak concentration and the activation rate are saturated, so the annealing time is 5 hours to 10 hours. Time is appropriate.

Furthermore, in the sixth embodiment, similar results are obtained when an epitaxial substrate is used, and a XeCl laser can be used in place of the YAG laser.
In the above description, IGBT and FWD have been described as examples. However, the present invention is not limited to these, and the entire IC, the p layer, the n layer, the pn continuous layer, and the pp continuous, regardless of the front side or the back side. It can be widely applied to the activation of the layer and the nn continuous layer.

Next, a semiconductor device manufacturing apparatus that can be used in the manufacturing methods described in the first to sixth embodiments will be described.
The semiconductor device manufacturing apparatus (semiconductor manufacturing apparatus) for realizing the manufacturing method described in the first to sixth embodiments can adjust the temperature of the substrate simultaneously with ion implantation, and irradiates the substrate with laser. It is desirable that it can be performed.

FIG. 22 shows a configuration example of a semiconductor manufacturing apparatus.
The semiconductor manufacturing apparatus 1 shown in FIG. 22 irradiates the substrate heating apparatus 2 having a sample stage on which the substrate 20 is placed and the substrate 20 placed on the substrate heating apparatus 2 with an ion beam. The ion implantation apparatus 3 and the laser irradiation apparatus 4 for irradiating the substrate 20 with a laser beam.

  The substrate heating device 2 is disposed in the ion implantation / laser irradiation chamber 5 and is configured to be able to place, for example, a wafer having a size of 125 mm to 300 mm. A temperature controller 6 provided outside the ion implantation / laser irradiation chamber 5 is connected to the substrate heating apparatus 2, and a heater or the like built in the substrate heating apparatus 2 is heated by this temperature controller 6, so that the substrate 20 is predetermined. The temperature can be adjusted. Further, the ion implantation / laser irradiation chamber 5 is provided with a gas introduction mechanism and a gas exhaust mechanism (both not shown) so that the atmosphere and pressure in the room can be controlled.

  An existing ion implantation apparatus 3 can be used. In this semiconductor manufacturing apparatus 1, the deflection electromagnet 7 is disposed in front of the substrate 20, and the ion beam emitted from the ion implantation apparatus 3 is deflected here. Then, the substrate 20 is irradiated.

  As the laser irradiation device 4, an existing device that emits a high-energy laser can be used. In this semiconductor manufacturing device 1, five mirrors 8a, 8b, 8c, 8d, and 8e, a telescope 9 and a homogenizer 10 are provided. The substrate 20 is irradiated with a laser beam.

The laser pulse emitted from the laser irradiation device 4 may be either an XeCl laser or a YAG laser. Here, if the irradiation energy density of the emitted laser beam is XeCl laser, 0.4 J / cm ^{2 to} 1.4 J / cm ^2, and preferably a possible output configurations in a range of 0.4J / cm ² ~2.0J / cm ² if YAG2ω laser. If the irradiation energy density exceeds the upper limit of this range at the time of laser pulse irradiation, there is a high possibility that processing marks will be generated on the substrate 20. As a YAG laser, a YAG3ω laser (wavelength 355 nm) may be used for the purpose of activation up to a deep position.

FIG. 23 shows another configuration example of the semiconductor manufacturing apparatus. However, in FIG. 23, the same elements as those shown in FIG. 22 are denoted by the same reference numerals, and detailed description thereof is omitted.
The semiconductor manufacturing apparatus 1a shown in FIG. 23 includes two laser irradiation apparatuses 4a and 4b, and further includes five mirrors 8f, 8g, 8h, 8i, and 8j and a PBS (polarizing beam splitter) 11. It has a configuration. The laser emitted from the laser irradiation devices 4a and 4b may be either a XeCl laser or a YAG laser, but the same kind of laser can be emitted during processing.

  Since the two laser irradiation devices 4a and 4b are provided in this way, it becomes possible to continuously irradiate the substrate 20 with a plurality of pulses of the same type of laser with an appropriate delay time. It becomes possible to apply sufficient irradiation energy to the region. Thereby, activation to a deeper region can be performed in a short time.

For example, in the case of laser annealing, ideally two YAG2ω laser irradiation apparatuses are provided, and pulses with an irradiation energy density of 1.4 J / cm ² are continuously irradiated with a delay time of 300 ns to 500 ns. In this case, the total irradiation energy density is 2.8 J / cm ² . In this way, when the YAG2ω laser is irradiated with double pulses, the irradiation energy density per pulse can be kept low, so that generation of processing marks can be prevented, and heating by the substrate heating device 2 is not performed. A high irradiation energy density can be sufficiently secured. In this case, activation can be performed in a short time without generating a processing mark at the time of ion implantation. For example, the overlap rate on the substrate 20 at the time of laser irradiation is about 50%, or the laser is uniformly applied to the substrate 20 once. Sufficient activation can be achieved by scanning irradiation.

  By using the semiconductor manufacturing apparatuses 1 and 1a configured as shown in FIGS. 22 and 23, temperature adjustment of the substrate 20, ion implantation at an appropriate timing, and laser irradiation can be performed by batch processing. The manufacturing method described in the sixth embodiment can be easily realized. In addition, since batch processing can be performed, annealing in a vacuum can be performed, and the impurity layer can be activated while suppressing the influence of oxygen and contamination, whereby a film formed on the substrate 20 after activation. The contact property of is improved.

  Furthermore, in such semiconductor manufacturing apparatuses 1 and 1a, the irradiation energy density of the laser pulse can be set higher than in the past. A conventional semiconductor manufacturing apparatus uses an XeCl excimer laser, but the output of the excimer laser is small, and it is difficult to sufficiently activate impurities implanted into the Si substrate only by conventional level laser irradiation. On the other hand, the semiconductor manufacturing apparatuses 1 and 1a can irradiate a laser pulse with an irradiation energy density in a range that does not cause processing marks on the substrate 20, and are ion-implanted into the Si substrate as described in the above embodiments. Sufficient activation of impurities can be realized.

  Further, when ion implantation is performed on the substrate 20 while irradiating a laser, the laser pulse may be irradiated at an irradiation energy density necessary for activating the impurity layer, but in order to make the most of the laser effect. It is preferable to irradiate the substrate 20 with the same scan frequency of the ion beam and the oscillation frequency of the laser beam.

FIG. 24 is a block diagram of the main part of the semiconductor manufacturing apparatus. However, in FIG. 24, the same elements as those shown in FIG. 22 are denoted by the same reference numerals, and detailed description thereof will be omitted.
For example, when the ion beam scan frequency of the ion implantation apparatus 3 is 100 Hz in both the horizontal direction and the vertical direction, the laser beam oscillation frequency of the laser irradiation apparatus 4 is also set to 100 Hz. Then, the ion beam and laser beam having the same frequency are irradiated onto the substrate 20 from the same direction. As a result, the substrate 20 is irradiated with an ion beam and a laser beam at a timing of 1/100 second, and activation can be promoted and in-plane variation can be suppressed.

  If the ion beam scan frequency of the ion implantation device 3 is different, such as 100 Hz in the horizontal direction and 500 Hz in the vertical direction, the oscillation frequency of the laser beam of the laser irradiation device 4 should be between 100 Hz and 500 Hz. In this case, the irradiation timings of both the substrates 20 do not deviate greatly. This promotes activation and suppresses in-plane variation.

It is a concentration profile when boron ion implantation is performed while heating the FZ-N substrate. It is a concentration profile when phosphorus ion implantation is performed while heating the FZ-N substrate. This is a concentration profile when phosphorus and boron ions are implanted while heating the FZ-N substrate. This is a concentration profile when boron ion implantation is performed while irradiating a laser while heating the FZ-N substrate. It is a density | concentration profile when performing ion implantation of phosphorus, heating a FZ-N board | substrate and irradiating a laser. It is a density | concentration profile when ion implantation of phosphorus and boron is performed while heating an FZ-N substrate and irradiating a laser. It is a concentration profile when boron ion implantation is performed while irradiating a laser. It is a concentration profile when ion implantation of phosphorus is performed while irradiating a laser. It is a concentration profile when electric furnace annealing is performed after boron ion implantation is performed while heating the FZ-N substrate. It is a concentration profile when electric furnace annealing is performed after ion implantation of phosphorus while heating the FZ-N substrate. It is a concentration profile when electric furnace annealing is performed after ion implantation of phosphorus and boron while heating the FZ-N substrate. It is a concentration profile when electric furnace annealing is performed after boron ion implantation is performed while heating the FZ-N substrate and irradiating a laser. It is a concentration profile when electric furnace annealing is performed after ion implantation of phosphorus is performed while heating the FZ-N substrate and irradiating a laser. It is a concentration profile when electric furnace annealing is performed after ion implantation of phosphorus and boron is performed while heating the FZ-N substrate and irradiating a laser. It is a concentration profile when laser annealing is performed after boron ion implantation is performed while heating the FZ-N substrate. It is a concentration profile when laser annealing is performed after ion implantation of phosphorus while heating the FZ-N substrate. It is a concentration profile when laser annealing is performed after ion implantation of phosphorus and boron while heating the FZ-N substrate. It is a concentration profile when laser annealing is performed after boron ion implantation is performed while the FZ-N substrate is heated and irradiated with laser. It is a concentration profile when laser annealing is performed after ion implantation of phosphorus is performed while heating the FZ-N substrate and irradiating a laser. It is a concentration profile when laser annealing is performed after ion implantation of phosphorus and boron is performed while irradiating a laser while heating the FZ-N substrate. It is a figure which shows the ion implantation temperature dependence of the peak density | concentration of a density | concentration profile. It is a structural example of a semiconductor manufacturing apparatus. It is another structural example of a semiconductor manufacturing apparatus. It is a principal part block diagram of a semiconductor manufacturing apparatus. It is an example of the cross-sectional structure of NPT type IGBT. It is an example of the cross-sectional structure of FS type IGBT. It is sectional drawing after the surface side process completion | finish. It is sectional drawing of a substrate grinding process. It is sectional drawing of a back surface ion implantation process. It is sectional drawing of a back surface annealing process. It is sectional drawing of a back surface electrode film formation process. It is an example of the cross-sectional structure of reverse blocking IGBT.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,1a Semiconductor manufacturing apparatus 2 Substrate heating apparatus 3 Ion implantation apparatus 4, 4a, 4b Laser irradiation apparatus 5 Ion implantation / laser irradiation chamber 6 Temperature controller 7 Bending magnet 8a, 8b, 8c, 8d, 8e, 8f, 8g, 8h , 8i, 8j Mirror 9 Telescope 10 Homogenizer 11 PBS
20 substrates

Claims (8)

In a method for manufacturing a semiconductor device having a step of activating an impurity layer formed on a silicon substrate,
A method of manufacturing a semiconductor element, wherein the impurity layer is activated by ion-implanting impurities into the silicon substrate in a state where the temperature of the silicon substrate is set to 400 ° C. to 500 ° C. In a method for manufacturing a semiconductor device having a step of activating an impurity layer formed on a silicon substrate,
The impurity layer is activated by ion-implanting impurities while irradiating the silicon substrate with a laser pulse having a wavelength of 300 nm to 600 nm while the temperature of the silicon substrate is set to 400 ° C. to 500 ° C. A method for manufacturing a semiconductor device.   3. The method of manufacturing a semiconductor device according to claim 2, wherein the scan frequency of the ion beam at the time of ion implantation is substantially the same as the oscillation frequency of the laser beam at the time of laser irradiation. In a method for manufacturing a semiconductor device having a step of activating an impurity layer formed on a silicon substrate,
By ion-implanting an impurity into the silicon substrate while wavelengths in the silicon substrate is irradiated energy density 300nm~600nm irradiated with a laser pulse of ^{0.4J / cm 2 ~1.4J / cm 2} , the impurity layer A method of manufacturing a semiconductor device, wherein the semiconductor device is activated.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the scan frequency of the ion beam at the time of ion implantation is substantially the same as the oscillation frequency of the laser beam at the time of laser irradiation. In a method for manufacturing a semiconductor device, comprising a step of activating an n-type impurity layer formed on a silicon substrate.
An n-type impurity is ion-implanted into the silicon substrate in a state where the temperature of the silicon substrate is a liquid nitrogen temperature or 200 ° C. to 500 ° C., and after the ion implantation of the n-type impurity, the temperature is 350 ° C. to 500 ° C. A method of manufacturing a semiconductor device, wherein the n-type impurity layer is activated by performing electric furnace annealing or laser annealing for 5 hours to 10 hours. In a semiconductor device manufacturing apparatus that activates an impurity layer formed on a silicon substrate,
A substrate heating apparatus for heating the silicon substrate;
An ion implantation apparatus for ion-implanting impurities into the silicon substrate;
A laser irradiation apparatus wavelength irradiation energy density 300nm~600nm irradiating a laser pulse of 0.4J / cm ² ~1.4J / cm ² on the silicon substrate,
A device for manufacturing a semiconductor element, comprising:   8. The semiconductor device manufacturing apparatus according to claim 7, wherein a plurality of the laser irradiation devices are provided, and the silicon substrate is continuously irradiated with laser pulses respectively emitted from the plurality of laser irradiation devices. .

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