JP5557848B2 - Manufacturing method of semiconductor device - Google Patents
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- JP5557848B2 JP5557848B2 JP2011539356A JP2011539356A JP5557848B2 JP 5557848 B2 JP5557848 B2 JP 5557848B2 JP 2011539356 A JP2011539356 A JP 2011539356A JP 2011539356 A JP2011539356 A JP 2011539356A JP 5557848 B2 JP5557848 B2 JP 5557848B2
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- 239000004065 semiconductor Substances 0.000 title claims description 76
- 238000004519 manufacturing process Methods 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 70
- 239000012535 impurity Substances 0.000 claims description 37
- 238000000034 method Methods 0.000 claims description 16
- 238000010438 heat treatment Methods 0.000 claims description 10
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- 238000002844 melting Methods 0.000 claims description 6
- 230000008018 melting Effects 0.000 claims description 6
- 230000003213 activating effect Effects 0.000 claims description 5
- 238000005468 ion implantation Methods 0.000 claims description 5
- 230000001678 irradiating effect Effects 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 35
- 238000005224 laser annealing Methods 0.000 description 18
- -1 phosphorus ions Chemical class 0.000 description 18
- 238000009826 distribution Methods 0.000 description 14
- 229910052796 boron Inorganic materials 0.000 description 10
- 239000011574 phosphorus Substances 0.000 description 10
- 229910052698 phosphorus Inorganic materials 0.000 description 10
- 239000010408 film Substances 0.000 description 7
- 238000001994 activation Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 6
- 239000013078 crystal Substances 0.000 description 6
- 230000004913 activation Effects 0.000 description 5
- 230000007547 defect Effects 0.000 description 5
- 239000004642 Polyimide Substances 0.000 description 4
- 238000002513 implantation Methods 0.000 description 4
- 230000007246 mechanism Effects 0.000 description 4
- 229920001721 polyimide Polymers 0.000 description 4
- 238000010521 absorption reaction Methods 0.000 description 3
- 150000001638 boron Chemical class 0.000 description 3
- 150000003017 phosphorus Chemical class 0.000 description 3
- 239000000853 adhesive Substances 0.000 description 2
- 230000001070 adhesive effect Effects 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000003574 free electron Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 238000001004 secondary ion mass spectrometry Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000002679 ablation Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005284 excitation Effects 0.000 description 1
- 238000011049 filling Methods 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
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- 238000000859 sublimation Methods 0.000 description 1
- 230000008022 sublimation Effects 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/268—Bombardment with radiation with high-energy radiation using electromagnetic radiation, e.g. laser radiation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6831—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using electrostatic chucks
Description
本発明は、半導体基板内に導入された不純物を活性化させる際に用いられるレーザーアニール技術に係り、その不純物活性化方法を用いた半導体装置の製造方法に関する。 The present invention relates to a laser annealing technique used when activating impurities introduced into a semiconductor substrate, and more particularly to a method of manufacturing a semiconductor device using the impurity activation method.
Ｓｉの厚みを１００μｍ程度にまで薄くした極薄ＩＧＢＴ（Insulated Gate Bipolar Transistor）が知られている。極薄ＩＧＢＴは、ｎ＋型のフィールドストップ層及びｐ＋型のコレクタ層を半導体基板の裏面部分に備えている。一般的には、フィールドストップ層及びコレクタ層は積層して形成されている。フィールドストップ層とコレクタ層は、半導体基板の裏面からｎ型不純物であるリンイオンを深い位置に導入し、ｐ型不純物であるボロンイオンを浅い位置に導入した後に、活性化のための熱処理を実施することによって得られる。An ultra-thin IGBT (Insulated Gate Bipolar Transistor) in which the thickness of Si is reduced to about 100 μm is known. The ultra-thin IGBT includes an n + -type field stop layer and a p + -type collector layer on the back surface portion of the semiconductor substrate. In general, the field stop layer and the collector layer are laminated. In the field stop layer and the collector layer, phosphorus ions that are n-type impurities are introduced into deep positions from the back surface of the semiconductor substrate, and boron ions that are p-type impurities are introduced into shallow positions, and then heat treatment for activation is performed. Can be obtained.
この熱処理方法としてレーザーアニールが利用されている。レーザーアニールには、エキシマレーザー、ＹＡＧ第２高調波レーザー、又はＹＬＦ第２高調波レーザー等が利用されている。これらのパルスレーザーは、Ｓｉ半導体基板における吸収係数も大きいことから、半導体基板の裏面部分のみを選択的に加熱することができる。このため、半導体基板の表面に形成されているアルミ電極及びポリイミド層が損傷してしまうことを回避できる。この種のレーザーアニールを利用する方法は、下記の特許文献１〜４に開示されている。
Laser annealing is used as this heat treatment method. For laser annealing, an excimer laser, a YAG second harmonic laser, a YLF second harmonic laser, or the like is used. Since these pulse lasers also have a large absorption coefficient in the Si semiconductor substrate, only the back surface portion of the semiconductor substrate can be selectively heated. For this reason, it can avoid that the aluminum electrode and polyimide layer which are formed in the surface of a semiconductor substrate will be damaged. Methods using this type of laser annealing are disclosed in the following
極薄ＩＧＢＴのｎ＋型のフィールドストップ層は、半導体基板の裏面から１μｍほどの深い位置に不純物濃度のピークが形成され、その形成範囲が半導体基板の裏面から２μｍほどの深い位置にまで至ることが多い。このため、ｎ型不純物であるリンイオンも半導体基板の裏面から深い位置に導入されている。このリンイオンを高活性化させるためには、深い位置まで９５０℃以上にまで加熱しなければならない。しかしながら、特許文献１〜４に示されたレーザーアニールでは、半導体基板の裏面から深い位置に導入された不純物を高活性化させることが難しい。エキシマレーザー、ＹＡＧ第２高調波レーザ、又はＹＬＦ第２高調波レーザ等のパルスレーザは、波長が短いレーザーである。このため、これらのパルスレーザは半導体基板の裏面から浅い位置（深さ数10〜100ｎｍ）で吸収され、深い位置を加熱することができないためである。The n + type field stop layer of the ultra-thin IGBT has an impurity concentration peak formed at a depth of about 1 μm from the back surface of the semiconductor substrate, and its formation range reaches a deep position of about 2 μm from the back surface of the semiconductor substrate There are many. For this reason, phosphorus ions, which are n-type impurities, are also introduced deep from the back surface of the semiconductor substrate. In order to activate this phosphorus ion highly, it is necessary to heat to a deep position up to 950 ° C. or higher. However, in the laser annealing disclosed in
下記の特許文献５には、ＹＡＧ第２高調波レーザと回転円盤式レーザーアニール装置を用いているが、この方式でも半導体基板の裏面から深い位置に導入された不純物を高活性化させることが難しい。
In
上述の特許文献１〜４に示される短波長のレーザーを利用する場合は、バンド間キャリア励起吸収をその加熱起源とするためレーザーアニールがアニール温度をコントロールできず、必ずＳｉ基板を融点以上の温度に上昇させ溶解再結晶化させてしまう。このため結晶欠陥が多く電流リークパスが起こり易く、不純物プロファイルの形を制御できない（ｐｎ接合を裏面に作っても全部混合してしまう）という欠点がある。極薄ＩＧＢＴのフィールドストップ層を効率的に活性化させるために、深い領域の不純物活性化を結晶欠陥数を減少させながら実現するレーザーアニールの技術が望まれている。
When using the short-wavelength lasers disclosed in the above-mentioned
半導体基板の裏面から１μｍよりも深い位置に形成されているフィールドストップ領域を備えている場合、特許文献１〜４に示されるレーザーアニールでは十分に活性化させることができなかった。また、これらのレーザーアニール技術によって深い位置のフィールドストップ領域を活性化させようとすると、レーザーの強度が強くなりすぎ浅い位置のコレクタ領域において昇華（アブレーション）が発生し、コレクタ領域が欠落するという事態が発生していた。
In the case where the field stop region formed at a position deeper than 1 μm from the back surface of the semiconductor substrate is provided, the laser annealing disclosed in
上述の特許文献５に示される回転円盤式レーザーアニール装置を利用しても、深さ１μｍの領域の活性化は十分できない。
Even if the rotating disk type laser annealing apparatus shown in
本発明は、半導体基板内に導入された不純物を、その深さに依存せずレーザーアニールで活性化させる方法を見出したことに基づくものである。半導体基板の主材料にＳｉ（シリコン）が用いられる場合、本発明の不純物の活性化工程では、長波長の光がＳｉに吸収される様にＳｉ基板を２５０℃以上の温度にあげた後に、従来用いられたエキシマ、ＹＡＧレーザー等とは異なり自由電子吸収をその加熱起源とする長波長のレーザーを用いて、レーザーパワーを制御することで半導体基板の表面の温度がシリコンの溶融温度以下となる条件でレーザーを照射する。これにより、半導体基板の表面部分を結晶欠陥の少ない状態にすることができる。 The present invention is based on the discovery of a method for activating an impurity introduced into a semiconductor substrate by laser annealing without depending on its depth. When Si (silicon) is used as the main material of the semiconductor substrate, in the impurity activation process of the present invention, after raising the Si substrate to a temperature of 250 ° C. or higher so that long wavelength light is absorbed by Si, Unlike the conventional excimer, YAG laser, etc., the surface temperature of the semiconductor substrate becomes lower than the melting temperature of silicon by controlling the laser power using a long wavelength laser whose free electron absorption is the heating origin. Irradiate the laser under conditions. Thereby, the surface part of a semiconductor substrate can be made into a state with few crystal defects.
具体的には、レーザーアニールの実施前に静電チャック機構で吸着する支持基板に、デバイス表面側が対向するように、ウエハ裏面が外側に出るように極薄デバイスウエハ（半導体基板）を吸着させる。１００μｍ程度の厚みの極薄Ｓｉ基板の場合、その基板自体を例えば本発明のように２５０℃以上に加熱すると下側（表面側）に凸にそりあがってしまうためである。この加熱のために、接着剤や固定テープ等で固定することはできず、本発明のような静電チャック機構で吸着する支持基板が必要となる。 Specifically, an ultrathin device wafer (semiconductor substrate) is adsorbed so that the back surface of the wafer is exposed to the outside so that the device front side faces the support substrate adsorbed by the electrostatic chuck mechanism before laser annealing. This is because, in the case of an ultrathin Si substrate having a thickness of about 100 μm, if the substrate itself is heated to 250 ° C. or more as in the present invention, for example, it is warped convexly downward (surface side). For this heating, it cannot be fixed with an adhesive or a fixing tape, and a support substrate that is attracted by an electrostatic chuck mechanism as in the present invention is required.
本発明の第１の特徴は、（１）半導体基板の表面から不純物を導入して半導体領域を形成する工程、静電チャック方式を用いて前記半導体基板を支持基板に固定して前記半導体基板全体を２５０℃以上に加熱する工程、３μｍ以上の波長のレーザーを１０００マイクロ秒以下の照射時間で照射して前記半導体基板の表面を加熱して前記半導体基板内に導入された前記不純物を活性化する工程とを有する半導体装置の製造方法にある。 The first feature of the present invention is that: (1) a step of forming a semiconductor region by introducing impurities from the surface of the semiconductor substrate, and fixing the semiconductor substrate to a support substrate by using an electrostatic chuck method. And heating the surface of the semiconductor substrate to irradiate the impurities introduced into the semiconductor substrate by irradiating a laser having a wavelength of 3 μm or more with an irradiation time of 1000 microseconds or less. A method of manufacturing a semiconductor device having a process.
（２）（１）において、前記レーザーは波長１０．６μｍを有するＣＯ２レーザーであることが好ましい。自由電子をより励起しやすくする長波長のレーザーであり、かつ機械工作等で既に産業界で広く用いられている、安定稼動可能なレーザーであるためである。(2) In (1), the laser is preferably a CO 2 laser having a wavelength of 10.6 μm. This is because it is a laser with a long wavelength that makes it easier to excite free electrons, and is a laser that can be stably operated and is already widely used in the industry for machining.
（３）（１）において、前記半導体領域を形成する工程が前記半導体基板の裏面から１μｍよりも深い位置に第１導電型の不純物を導入してフィールドストップ領域を形成する工程と、前記半導体基板の裏面から１μｍよりも浅い位置に第２導電型の不純物を導入してコレクタ領域を形成する工程とを有することが好ましい。 (3) In (1), in the step of forming the semiconductor region, a step of forming a field stop region by introducing a first conductivity type impurity at a position deeper than 1 μm from the back surface of the semiconductor substrate; And a step of forming a collector region by introducing a second conductivity type impurity at a position shallower than 1 μm from the back surface of the substrate.
（４）（１）において、前記半導体基板は３００μｍ以下に薄膜化した半導体Ｓｉ基板を用いることが好ましい。表裏面間に流れるキャリアの流動距離を短くし、極薄ＩＧＢＴの性能をより向上させるためである。 (4) In (1), it is preferable to use a semiconductor Si substrate thinned to 300 μm or less as the semiconductor substrate. This is for shortening the flow distance of the carrier flowing between the front and back surfaces and further improving the performance of the ultra-thin IGBT.
（５）（１）において、前記不純物を活性化する工程では、前記半導体Ｓｉ基板の裏面から前記半導体基板の裏面から１μｍよりも深い位置の温度が９５０℃以上シリコンの溶融温度１４１２℃以下となる条件で前記レーザーを照射することが好ましい。フィールドストップ領域を十分活性化させるためである。 (5) In (1), in the step of activating the impurities, the temperature deeper than 1 μm from the back surface of the semiconductor Si substrate to the back surface of the semiconductor substrate is 950 ° C. or higher and the silicon melting temperature is 1412 ° C. or lower. It is preferable to irradiate the laser under conditions. This is to sufficiently activate the field stop region.
（６）（３）において、前記コレクタ領域は、前記半導体基板の裏面から１μｍよりも浅い位置に向けて前記不純物の濃度がイオン注入時のままの形状を維持した領域を備えていることが好ましい。裏面側最表面の活性な不純物濃度をより濃くし、金属電極との接触抵抗をさげ極薄ＩＧＢＴの性能を向上させるためである。 (6) In (3), it is preferable that the collector region includes a region in which the impurity concentration is maintained as it is at the time of ion implantation toward a position shallower than 1 μm from the back surface of the semiconductor substrate. . This is because the active impurity concentration on the outermost surface on the back surface side is made higher, the contact resistance with the metal electrode is reduced, and the performance of the ultra-thin IGBT is improved.
本発明によれば、深さの異なるフィールドストップ領域とコレクタ領域の不純物を共に充分活性化することが可能であり、フィールドストップ領域の活性化時にコレクタ領域を溶融させることもなく、結晶欠陥の少ない半導体装置を得ることができる。 According to the present invention, it is possible to sufficiently activate both impurities in the field stop region and the collector region having different depths, and there is little crystal defect without melting the collector region when the field stop region is activated. A semiconductor device can be obtained.
以下、図面を参照して実施例１を詳細に説明する。 Hereinafter, Example 1 will be described in detail with reference to the drawings.
（ＩＧＢＴの製造方法）
図１〜図１０を参照して、ＩＧＢＴの製造方法を説明する。とりわけ、フィールドストップ層及びコレクタ層を形成する方法を中心に説明する。(Manufacturing method of IGBT)
With reference to FIGS. 1-10, the manufacturing method of IGBT is demonstrated. In particular, the method for forming the field stop layer and the collector layer will be mainly described.
図１に、ＩＧＢＴ１００の製造過程の要部断面図を模式的に示す。ＩＧＢＴ１００は、ｎ型のシリコン単結晶のウェハ（ＣＺ、ＭＣＺ、ＦＺ）を利用して形成されている。ＩＧＢＴ１００は、ｎ−型のドリフト層１上に形成されているｐ型のボディ層２と、そのボディ層２の表面部分に形成されているｎ＋型のソース領域３を備えている。ボディ層２及びソース領域３は、ドリフト層１の表面部分にイオン注入技術を利用して形成することができる。In FIG. 1, the principal part sectional drawing of the manufacturing process of IGBT100 is shown typically. The
次に、図２に示すように、ＩＧＢＴ１００には、トレンチゲート電極４が形成される。トレンチゲート電極４は、ソース領域３とドリフト層１を隔てているボディ層２にゲート絶縁膜５を介して対向している。ゲート絶縁膜５は、ボディ層２の表面からトレンチを形成した後に、そのトレンチの内壁を熱酸化することによって形成することができる。トレンチゲート電極４は、ゲート絶縁膜５によって被覆されたトレンチ内にポリシリコンを充填することによって形成することができる。トレンチゲート電極４のポリシリコンには不純物が高濃度に導入されており、実質的に導体である。
Next, as shown in FIG. 2, the
半導体基板の表面には、ソース領域３に電気的に接続するソース電極６が形成されている。ソース電極６とトレンチゲート電極４は、層間絶縁膜７によって電気的に分離されている。ボディ層２の表面にはさらに、ポリイミド層８が形成されている。ポリイミド層８はソース電極６を覆っており、ソース電極６等のパッシベーション（保護膜）用に設けられている。
A
次に、図３に示すように、ＩＧＢＴ１００のドリフト層１は裏面側から研磨され、半導体基板は１００μｍ程度の厚みに調整される。
Next, as shown in FIG. 3, the
次に、ドリフト層１の裏面から、フィールドストッパ層として寄与するｎ型不純物であるリンイオン９ａを深い位置に導入し、さらにコレクタ層として寄与するｐ型不純物であるボロンイオン９ｂを浅い位置に導入する。リンイオン９ａの注入条件は、注入エネルギーが５００〜７００KeVであり、ドーズ量が１×１０１３cm−２である。ボロンイオン９ｂの注入条件は、注入エネルギーが１０〜２０KeVであり、ドーズ量が５×１０１３〜１×１０１４cm−２である。図４に示すように、リンイオンの導入濃度分布は、半導体基板の裏面から１μｍほどの深い位置に不純物濃度のピークが形成され、その形成範囲が半導体基板の裏面から２μｍほどの深い位置にまで至っている。Next, from the back surface of the
次に、図５に示すように、静電チャック機構で吸着する支持基板に、デバイス表面側が対向するように、ウエハ裏面が外側に出るように吸着させる。１００μｍ程度の厚みの極薄Ｓｉ基板（極薄サンプル、極薄膜サンプル、Thin Wafer）の場合、その基板自体を例えば本発明のように２５０℃以上に加熱すると図６のように下側（表面側）に凸にそりあがってしまうためである。この加熱のために、接着剤や固定テープ等で固定することはできず、本発明のような静電チャック機構で吸着する支持基板が必要となる。 Next, as shown in FIG. 5, the wafer is sucked so that the back surface of the wafer comes out to the outside so that the device front side faces the support substrate sucked by the electrostatic chuck mechanism. In the case of an ultrathin Si substrate (ultrathin sample, ultrathin sample, thin wafer) having a thickness of about 100 μm, when the substrate itself is heated to, for example, 250 ° C. or more as in the present invention, the lower side (surface side) as shown in FIG. This is because it will bend upward. For this heating, it cannot be fixed with an adhesive or a fixing tape, and a support substrate that is attracted by an electrostatic chuck mechanism as in the present invention is required.
次に、半導体基板（極薄サンプル、極薄膜サンプル、Thin Wafer）の裏面に向けてレーザーアニールを実施する。レーザーアニール条件は、例えば裏面温度１２００℃、アニール時間６００マイクロ秒、基板加熱温度は２５０℃である。図７にボロンイオンを同一レーザー照射強度でＣＯ２レーザーアニールしたサンプルのシート抵抗、到達アニール温度の基板加熱温度依存性を示す。イオン注入層を十分活性化するためには（すなわち１１００℃以上に活性化するためには）、基板自体を２５０℃以上に加熱する必要があることが分かる。Next, laser annealing is performed on the back surface of the semiconductor substrate (ultra thin sample, ultra thin film sample, thin wafer). The laser annealing conditions are, for example, a back surface temperature of 1200 ° C., an annealing time of 600 microseconds, and a substrate heating temperature of 250 ° C. FIG. 7 shows the substrate resistance dependence of the sheet resistance and ultimate annealing temperature of a sample obtained by subjecting boron ions to CO 2 laser annealing at the same laser irradiation intensity. It can be seen that the substrate itself needs to be heated to 250 ° C. or higher in order to sufficiently activate the ion-implanted layer (that is, to activate it at 1100 ° C. or higher).
図８に、リン、ボロンイオンの導入濃度分布と活性化された濃度分布を示す。導入濃度分布は二次イオン質量分析システム（ＳＩＭＳ）を用いて算出した。活性化されたリンの濃度分布は拡がり抵抗（ＳＲ）を用いて算出した。 本実施例の活性化されたリンの濃度分布は、リンイオンの導入濃度分布に沿って深い位置までほぼ１００％活性化されていることが分かる。 本実施例では、半導体基板の浅い位置に導入されたボロンイオンの活性化においても従来技術で形成されたものとは異なる特徴を有している。図９に、半導体基板の裏面から深さ方向に沿った活性化ボロンの不純物濃度分布を示す。本実施例では、半導体基板の裏面部分がシリコンの溶融温度である１４１２℃以下の範囲で加熱されている。溶融再結晶化の現象は起きておらず、裏面部分の結晶欠陥の少ない状態であり、ほぼ１００％活性化されている。 FIG. 8 shows the introduction concentration distribution and activated concentration distribution of phosphorus and boron ions. The introduced concentration distribution was calculated using a secondary ion mass spectrometry system (SIMS). The concentration distribution of activated phosphorus was calculated using the spread resistance (SR). It can be seen that the activated phosphorus concentration distribution of this example is almost 100% activated to a deep position along the phosphorus ion introduction concentration distribution. In this embodiment, the activation of boron ions introduced at a shallow position of the semiconductor substrate also has a feature different from that formed by the prior art. FIG. 9 shows the impurity concentration distribution of activated boron along the depth direction from the back surface of the semiconductor substrate. In the present embodiment, the back surface portion of the semiconductor substrate is heated within a range of 1412 ° C. or less, which is the melting temperature of silicon. The phenomenon of melt recrystallization does not occur, there are few crystal defects in the back surface portion, and it is almost 100% activated.
本実施例のレーザーアニールによると、コレクタ層の不純物濃度が、アニール後もほぼイオン注入時の濃度分布のまま形成されるという利点も有している。図１０に示すように、ＹＡＧレーザー等の従来技術を用いると、コレクタ層の不純物濃度の分布は、溶解したシリコンの深さまで一様濃度分布している。半導体基板の表面部分の不純物濃度が低下している。この表面部分の低下は、ピークの値に対して１／１０ほどに低下する。一方、本実施例のコレクタ層は、イオン注入条件を制御することによりコレクタ層最表面の濃度を従来技術によるものよりも濃くすることができる。これにより、コレクタ電極に対するコンタクト性の向上、及び正孔の注入効率の向上が得られ、オン電圧の小さいＩＧＢＴを得ることができる。 According to the laser annealing of this embodiment, there is also an advantage that the impurity concentration of the collector layer is formed with the concentration distribution at the time of ion implantation substantially after the annealing. As shown in FIG. 10, when a conventional technique such as a YAG laser is used, the distribution of impurity concentration in the collector layer is uniformly distributed up to the depth of dissolved silicon. The impurity concentration of the surface portion of the semiconductor substrate is reduced. The reduction of the surface portion is reduced to about 1/10 of the peak value. On the other hand, in the collector layer of this embodiment, the concentration of the outermost surface of the collector layer can be made higher than that of the prior art by controlling the ion implantation conditions. Thereby, the contact property with respect to the collector electrode and the hole injection efficiency are improved, and an IGBT having a low on-voltage can be obtained.
次に、図１１に示すように、コレクタ層の裏面にアルミニウムを蒸着してコレクタ電極１０を形成して、ＩＧＢＴ１００を得ることができる。
Next, as shown in FIG. 11, the
以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、請求の範囲を限定するものではない。請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。 Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.
１…ドリフト層、２…ｐ型のボディ層、３…ソース領域、４…トレンチゲート電極、５…ゲート絶縁膜、６…ソース電極、７…層間絶縁膜、８…ポリイミド層、９ａ…リンイオン、９ｂ…ボロンイオン、１０…コレクタ電極。
DESCRIPTION OF
Claims (11)
前記半導体領域を形成する工程により、前記フィールドストッパ層を形成することを特徴とする請求項１記載の半導体装置の製造方法。2. The method of manufacturing a semiconductor device according to claim 1, wherein the field stopper layer is formed by the step of forming the semiconductor region.
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