JP2005302883A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance performance of a semiconductor device by shallow jointing of an impurity diffused layer and reducing the resistance. <P>SOLUTION: An element isolation region 2, a p-type well 3, a gate insulating film 4, and a gate electrode 5 are sequentially formed in a semiconductor substrate 1. Then, since an n<SP>-</SP>-type semiconductor region 7 as the extension diffused layer of the source/drain is formed, ion implantation 7a is carried out in an aslant direction, with respect to the main face of the semiconductor substrate 1. Thus, impurities are also introduced into the p-type well 3 at both ends of the gate electrode 5, and the n<SP>-</SP>-type semiconductor area 7 and the gate electrode 5 are overlapped. A sidewall 8 is formed on the sidewall of the gate electrode 5, and for forming an n<SP>+</SP>-type semiconductor area 9 as the source/drain, ion implantation 9a is carried out. Thereafter, in order to activate the impurities introduced into the n<SP>-</SP>-type semiconductor region 7 and the n<SP>+</SP>-type semiconductor region 9, a long wavelength laser annealing process is performed. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a technology that is effective when applied to a technology for manufacturing a semiconductor device having a MISFET having source and drain regions formed by ion implantation.

  A well region is formed on a semiconductor substrate, a gate insulating film is formed on the surface of the well region, a gate electrode is formed on the gate insulating film, and impurities are introduced into the well region on both sides of the gate electrode by ion implantation to form a source By forming an impurity diffusion layer as a drain, a MISFET is formed. After ion implantation, an annealing process is performed to activate the introduced impurities. As this annealing treatment, generally, RTA (Rapid Thermal Annealing) such as lamp annealing is performed.

  In Japanese Patent Laid-Open No. 10-261792, a shallow source / drain diffusion layer aligned with the gate electrode is formed by injecting ions at an angle of 30 ° from the vertical incidence toward the gate electrode side. After performing time annealing (RTA) to form a gate sidewall spacer, a deep source / drain diffusion layer aligned with the gate sidewall spacer is formed by ion implantation, and again annealed at 950 ° C. for 5 seconds for a short time (RTA). The technique which performs is described (refer patent document 1).

Japanese Patent Application Laid-Open No. 2000-77541 describes a technique for performing RTA treatment at about 1000 ° C. for 10 seconds in a nitrogen atmosphere after ion implantation (see Patent Document 2).
Japanese Patent Laid-Open No. 10-261792 JP 2000-77541 A

  According to the study of the present inventor, it has been found that there are the following problems.

  In order to achieve high integration of LSI, it is required to make the source and drain of MISFET and the extension diffusion layer thin with low resistance. For example, a transistor having a gate length of 65 nm or less is required to have a junction depth of about 20 nm and a resistance value of about 300 to 400 Ω / sq.

  When the annealing process after ion implantation is performed by RTA such as lamp annealing, the introduced impurities are diffused during the annealing. When the impurities diffuse, the junction depth of the formed impurity diffusion layer becomes deep. This is disadvantageous for miniaturization and high integration of the semiconductor device (semiconductor integrated circuit device). For this reason, in consideration of impurity diffusion, it is necessary to reduce the dose during ion implantation in order to reduce the junction depth of the formed impurity diffusion layer (source, drain and its extension diffusion layer). This increases the resistance of the impurity diffusion layer to be formed and may reduce the performance of the semiconductor device.

  An object of the present invention is to provide a technique capable of improving the performance of a semiconductor device.

  Another object of the present invention is to provide a technique that enables a semiconductor device to be miniaturized and highly integrated.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  In the present invention, ion implantation is performed obliquely with respect to the main surface of a semiconductor substrate to form a semiconductor region partially located below the gate electrode, and a sidewall insulating film is formed on the sidewall of the gate electrode. Then, ion implantation is performed to form a semiconductor region whose end is separated from the lower portion of the side wall of the gate electrode, and a step of performing long-wavelength laser annealing with a wavelength of 3 μm or more to activate the introduced impurity It has.

  In the present invention, ion implantation is performed obliquely with respect to the main surface of the semiconductor substrate to form a source / drain extension diffusion layer, and after forming a sidewall insulating film on the sidewall of the gate electrode, the ion implantation is performed. In order to form source / drain regions and activate the introduced impurities, long-wavelength laser annealing with a wavelength of 3 μm or more is performed.

  In the present invention, a sidewall insulating film is formed on the sidewall of the gate electrode, and then ion implantation is performed to form a source / drain region, and the sidewall insulating film is removed and then oblique to the main surface of the semiconductor substrate. Ion implantation is performed in the direction to form source / drain extension diffusion layers, and in order to activate the introduced impurities, long wavelength laser annealing with a wavelength of 3 μm or more is performed.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  It is possible to achieve both shallow junction and low resistance of the impurity diffusion layer.

  In addition, the performance of the semiconductor device can be improved.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiments, and the repetitive description thereof will be omitted. In the following embodiments, the description of the same or similar parts will not be repeated in principle unless particularly necessary.

  In the drawings used in the embodiments, hatching may be omitted even in a cross-sectional view so as to make the drawings easy to see. Further, even a plan view may be hatched to make the drawing easy to see.

(Embodiment 1)
A manufacturing process of the semiconductor device (semiconductor integrated circuit device) of the present embodiment will be described with reference to the drawings. FIG. 1 is a process flow diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor). 2 to 5 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment.

  As shown in FIG. 2, a semiconductor substrate (semiconductor wafer) 1 made of, for example, p-type single crystal silicon having a specific resistance of about 1 to 10 Ωcm is prepared (step S1), and an element is formed on the main surface of the semiconductor substrate 1. An isolation region 2 is formed (step S2). The element isolation region 2 is made of silicon oxide or the like, and is formed by, for example, an STI (Shallow Trench Isolation) method or a LOCOS (Local Oxidization of Silicon) method.

  Next, the p-type well 3 is formed in the region where the n-channel MISFET is to be formed on the semiconductor substrate 1 (step S3). The p-type well 3 is formed by ion implantation of a p-type impurity such as boron (B). Thereafter, if necessary, the surface layer portion of the p-type well 3 can be subjected to ion implantation for adjusting the threshold voltage of a MISFET to be formed later and heat treatment for activating the introduced impurity.

  Next, the gate insulating film 4 is formed on the surface of the p-type well 3 (step S4). The gate insulating film 4 is made of, for example, a thin silicon oxide film, and can be formed by, for example, a thermal oxidation method. Further, the surface of the thermal oxide film can be nitrided using NO gas or the like, and the gate insulating film 4 can be formed by a laminated film of a silicon oxide film and a silicon nitride film thereon. Alternatively, the gate insulating film 4 can be formed using a silicon oxynitride film.

  Next, the gate electrode 5 is formed on the gate insulating film 4 of the p-type well 3 (step S5). For example, a polycrystalline silicon film and an insulating film 6 (for example, a silicon oxide film) are sequentially formed on the semiconductor substrate 1 by using a CVD (Chemical Vapor Deposition) method or the like, and phosphorus ( An n-type impurity such as P) is introduced, and the insulating film 6 and the polycrystalline silicon film are patterned by dry etching, thereby forming the gate electrode 5 made of the polycrystalline silicon film into which the n-type impurity is introduced. it can. An insulating film 6 is formed on the gate electrode 5, and the insulating film 6 can function as a protective film for the gate electrode 5.

Next, as shown in FIG. 3, n-type impurities such as arsenic (As) are ion-implanted (ion-implanted) into regions on both sides of the gate electrode 5 of the p-type well 3, thereby (a pair of) n ^A -type semiconductor region (impurity diffusion layer, source / drain extension diffusion layer) 7 is formed (step S6).

  As schematically illustrated in FIG. 3, the ion implantation 7 a in step S <b> 6 uses an oblique ion implantation method in which impurities are ion-implanted from an oblique direction with respect to the main surface of the semiconductor substrate 1. That is, the ion implantation 7a in step S6 is performed on both sides of the gate electrode 5 of the p-type well 3 from a direction inclined by a predetermined angle from a direction perpendicular to the main surface of the semiconductor substrate 1 (normal direction of the main surface of the semiconductor substrate 1). Impurities are ion-implanted into the region. Thus, impurity ions are incident on the main surface of the semiconductor substrate 1 from a direction inclined by a predetermined angle from the direction perpendicular to the main surface of the semiconductor substrate 1 and are introduced into the p-type well 3.

In step S6, the direction of ion implantation 7a (advancing direction, acceleration direction, and incident direction of impurity ions to be introduced) is inclined by 1 degree (1 °) or more from the direction perpendicular to the main surface of the semiconductor substrate 1 (that is, the semiconductor substrate). The incident angle of impurity ions on the main surface of 1 is preferably 89 degrees (89 °) or less, and is preferably inclined by 4 degrees (4 °) or more (that is, impurity ions on the main surface of the semiconductor substrate 1). More preferably, the incident angle is 86 degrees (86 °) or less. In the ion implantation in step S6, the gate electrode 5 and the insulating film 6 can function as an implantation blocking mask. The condition of the ion implantation 7a in step S6 is that acceleration energy is about 3 keV, for example, and the implantation amount (dose amount) can be about 1 × 10 ¹⁵ / cm ^2, for example.

  Further, in the ion implantation process of step S6, the semiconductor substrate 1 is arranged so that the normal direction of the main surface of the semiconductor substrate 1 is inclined with respect to the direction of ion implantation, and the semiconductor substrate is rotated after the ion implantation. The operation is repeated a plurality of times (for example, the operation of rotating the semiconductor substrate 90 degrees by ion implantation is repeated four times). Alternatively, the semiconductor substrate 1 is arranged so that the normal direction of the main surface of the semiconductor substrate 1 is inclined with respect to the direction of the ion implantation 7a, and ion implantation is performed while rotating the semiconductor substrate 1. As a result, impurities are also introduced into the p-type well 3 below both ends of the gate electrode 5.

In the present embodiment, by performing the ion implantation 7a in step S6 from an oblique direction with respect to the main surface of the semiconductor substrate 1, the region into which the impurity is implanted (n ⁻ type semiconductor region 7) and the gate electrode 5 are over. Impurities are also introduced into the p-type well 3 under the edge of the gate electrode 5. Therefore, the n ⁻ type semiconductor region 7 also extends below the end of the gate electrode 5. That is, part of the n ⁻ type semiconductor region 7 formed on both sides of the gate electrode 5 overlaps with the gate electrode 5 and is located below the gate electrode 5. The overlap length between the impurity-implanted region (n ⁻ type semiconductor region 7) and the gate electrode 5 can be controlled by adjusting the angle of the ion implantation 7a and the like.

Further, in the ion implantation process of step S6, since the gate electrode 5 and the insulating film 6 can function as an implantation blocking mask, the n ⁻ type semiconductor region 7 is formed in a self-aligned manner with respect to the gate electrode 5. . For this reason, the n ⁻ type semiconductor region 7 is formed on both sides of the gate electrode so as to be in contact with the channel region of the MISFET, and a part of the n ⁻ type semiconductor region 7 overlaps with the gate electrode 5 to be below the gate electrode 5. Will be located.

In addition, after the ion implantation in step S6, an annealing process in the order of seconds is performed at a relatively low temperature to activate the overlap region between the impurity-implanted region (n ⁻ type semiconductor region 7) and the gate electrode 5. The overlap length can be adjusted or the impurity concentration can be made uniform. When this annealing treatment is performed, the annealing temperature is set to 800 ° C. or lower. If the annealing temperature is too high, impurities may diffuse too much. In this embodiment, as described later, it is preferable to reduce the diffusion of impurities as much as possible. Therefore, the annealing temperature at this stage is set to 800 ° C. or lower to suppress the diffusion of impurities. Further, this annealing treatment can be omitted.

  Next, as shown in FIG. 4, a sidewall (sidewall spacer, sidewall insulating film) 8 made of an insulating film such as silicon oxide, silicon nitride, or a laminated film thereof is formed on the sidewall of the gate electrode 5. (Step S7). The sidewall 8 can be formed, for example, by depositing an insulating film (a silicon oxide film or a silicon nitride film or a laminated film thereof) on the semiconductor substrate 1 and anisotropically etching the insulating film.

Next, as shown in FIG. 5, n-type impurities such as arsenic (As) are ion-implanted (ion-implanted) into regions on both sides of the gate electrode 5 and the sidewall 8 of the p-type well 3 ( A pair of n ⁺ type semiconductor regions 9 (source, drain) are formed (step S8). As schematically shown in FIG. 5, the ion implantation 9 a in step S <b> 8 is performed on the gate electrode 5 of the p-type well 3 and the regions on both sides of the sidewall 8 from the direction perpendicular to the main surface of the semiconductor substrate 1. Impurities can be ion-implanted.

The n ⁺ type semiconductor region 9 has a higher impurity concentration than the n ⁻ type semiconductor region 7. The junction depth (depth or thickness in the direction perpendicular to the main surface of the semiconductor substrate 1) of the n ⁺ type semiconductor region 9 is equal to the junction depth of the n ⁻ type semiconductor region 7 (perpendicular to the main surface of the semiconductor substrate 1). Deeper than (thickness or thickness in any direction). That is, the n ⁻ type semiconductor region 7 has a lower impurity concentration and is shallower than the n ⁺ type semiconductor region 9. For example, by making the acceleration energy of the ion implantation 7a in step S6 lower than the acceleration energy of the ion implantation 9a in step S8, the junction depth of the n ⁻ type semiconductor region 7 is made larger than the junction depth of the n ⁺ type semiconductor region 9. Can also be shallow.

In the ion implantation process of step S8, since the gate electrode 5, the insulating film 6 and the sidewall 8 can function as an implantation blocking mask, the n ⁺ type semiconductor region 9 is self-aligned with respect to the sidewall 8. It is formed. Therefore, the end portion of the n ⁺ -type semiconductor region 9 is separated from the lower side wall of the gate electrode 5, the channel region of the MISFET n ^- to be separated through a type semiconductor region 7, n ^- linked to type semiconductor region 7 An n ⁺ type semiconductor region 9 to be formed is formed on both sides of the gate electrode 5.

Next, in order to activate the impurities introduced into the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 by the ion implantation in step S6 and step S8, a long wavelength laser annealing process is performed (step S9).

The long wavelength laser annealing process in step S9 is an annealing process (heat treatment) using a long wavelength laser (laser), and the wavelength of the laser (laser light) used is preferably 3 μm or more, preferably 5 μm or more. More preferably, it is more preferably 8 μm or more. For example, the annealing process in step S9 can be performed using a CO ₂ gas laser (wavelength 10.6 μm). By irradiating the main surface (predetermined region) of the semiconductor substrate 1 with a long wavelength laser, the annealing target region can be heated to a desired annealing temperature. In this embodiment, by using long-wavelength laser annealing for the annealing process for activating impurities, the temperature can be raised and lowered in a shorter time at a higher temperature than RTA such as lamp annealing. High-temperature and short-time annealing is possible. As a result, the resistance of the activated impurity diffusion layer (n ⁻ type semiconductor region 7 and n ⁺ type semiconductor region 9) can be reduced, and the diffusion of the introduced impurity can be suppressed, and the impurity diffusion layer (n It is possible to reduce the junction depth of the ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9, particularly the n ⁻ type semiconductor region 7), that is, to form a shallow junction. This is advantageous for downsizing and high integration of the semiconductor device (semiconductor integrated circuit device).

The annealing temperature in step S9 is preferably 1000 ° C. or higher, more preferably 1100 ° C. or higher, and even more preferably 1200 ° C. or higher. The annealing time in step S9 is preferably 100 msec (100 milliseconds) or less, more preferably 10 msec (10 milliseconds) or less, and even more preferably 1 msec (1 milliseconds) or less. The annealing process in step S9 can be performed, for example, in a nitrogen (N ₂ ) atmosphere, but other gas species (for example, an inert gas) can also be used.

In this way, an n-type semiconductor region (impurity diffusion layer) functioning as a source or drain of the n-channel MISFET is formed by the n ⁺ -type semiconductor region 9 and the n ⁻ -type semiconductor region 7, and is formed in the p-type well 3. An n-channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) 11 is formed. The n ⁺ type semiconductor region 9 (or the n ⁺ type semiconductor region 9 and the n ⁻ type semiconductor region 7) can function as a source or a drain of the n-channel type MISFET 11. The n ⁻ type semiconductor region 7 can function as a source or drain extension diffusion layer (extension region).

  In the present embodiment, the case where the n-channel type MISFET 11 is formed has been described. However, the n-type and p-type conductivity types may be reversed to form the p-channel type MISFET. Further, an n-channel MISFET and a p-channel MISFET can be formed to form a CMISFET (Complementary Metal Insulator Semiconductor Field Effect Transistor).

  A process after the n-channel MISFET 11 is formed (process after step S9) will be described. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG.

As shown in FIG. 6, to expose the surface of the gate electrode 5 and the n ⁺ -type semiconductor region 9, for example, by heat treatment by depositing a cobalt (Co) film, a gate electrode 5 and the n ⁺ -type semiconductor region 9 A silicide film (cobalt silicide film, for example, CoSi ₂ film) 12a and a silicide film (cobalt silicide film, for example, CoSi ₂ film) 12b are respectively formed on the surfaces of the films. Thereby, the diffusion resistance and contact resistance of the n ⁺ type semiconductor region 9 can be reduced. Thereafter, the unreacted cobalt film is removed.

  Next, an insulating film (interlayer insulating film) 13 is formed on the semiconductor substrate 1 so as to cover the gate electrode 5. The insulating film 13 is made of, for example, a laminated film of a relatively thin silicon nitride film and a relatively thick silicon oxide film thereon.

Next, the contact hole (opening) 14 is formed in the upper part of the n ⁺ type semiconductor region (source, drain) 9 by dry etching the insulating film 13 using a photolithography technique. At the bottom of the contact hole 14, a part of the main surface of the semiconductor substrate 1, for example, a part of the n ⁺ -type semiconductor region 9 (silicide film 12b on the surface thereof) or the gate electrode 5 (silicide film 12a on the surface thereof). A part of is exposed.

Next, a plug 15 made of tungsten (W) or the like is formed in the contact hole 14. The plug 15 is formed, for example, by forming a barrier film 15a such as a titanium nitride film on the insulating film 13 including the inside of the contact hole 14, and then filling the contact hole 14 on the barrier film 15a by a CVD method. It is formed by removing an unnecessary tungsten film and barrier film 15a on the insulating film 13 by a CMP (Chemical Mechanical Polishing) method or an etch back method. Plug 15 is electrically connected to n ⁺ type semiconductor region 9 or gate electrode 5.

Next, a wiring 16 is formed as a first layer wiring on the insulating film 13 in which the plug 15 is embedded. For example, a titanium film 16a, a titanium nitride film 16b, an aluminum film (aluminum alloy film) 16c, a titanium film 16d, and a titanium nitride film 16e are sequentially formed by a sputtering method or the like, and patterned using a photolithography method, a dry etching method, or the like. As a result, the wiring 16 can be formed. The wiring 16 is electrically connected to the n ⁺ -type semiconductor region 9 for the source or drain of the n-channel type MISFET 11, the gate electrode 5, and the like through the plug 15. The wiring 16 is not limited to aluminum wiring and can be variously changed. For example, the wiring 16 may be formed of tungsten wiring.

  Next, an insulating film (interlayer insulating film) 17 is formed on the insulating film 13 so as to cover the wiring 16. Thereafter, a second layer wiring and the like electrically connected to the wiring 16 are formed, but the description thereof is omitted here. The buried copper wiring formed by the damascene method can be used after the second layer wiring.

As described above, in the present embodiment, after performing the ion implantation in step S6 and step S8, a long wavelength laser annealing process (heat treatment) is performed in step S9 in order to activate the introduced impurities. As a result, the impurities introduced into the semiconductor substrate 1 (the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9) are activated, and the n ⁻ type semiconductor region that functions as the source or drain of the n-channel type MISFET 11 is activated. 7 and n ⁺ type semiconductor region 9 are formed.

  Unlike this embodiment, it is also conceivable to use lamp heating (lamp annealing) for the annealing treatment after ion implantation (annealing treatment in step S9). However, in the case of lamp heating using a wavelength such that absorption into Si (silicon) is poor (absorption coefficient is low), it takes time to raise the temperature of the semiconductor substrate to a predetermined annealing temperature. Irradiation time) becomes longer. In addition, even in the case of flash lamp annealing using a wavelength such that absorption into Si (silicon) is good (absorption coefficient is high), in the lamp heating method, it takes time to start up the lamp when emitting lamp light. Therefore, the annealing time (lamp light irradiation time) is longer than that of the laser method. Further, it is not easy to control the short-time irradiation of the lamp light, and if the irradiation time of the lamp light is shortened, there is a possibility that the variation in the annealing temperature becomes large. Further, in the case of the lamp heating method, the wavelength of the lamp light is wider than that of the laser method, and there is a possibility that uneven annealing temperature (nonuniform temperature distribution) occurs in the surface of the semiconductor wafer. There is also a limit to the annealing temperature that can raise the temperature.

  When the annealing time becomes long, the introduced impurities diffuse during the annealing. When the impurities diffuse, the junction depth of the formed impurity diffusion layer becomes deep. This is disadvantageous for high integration of the semiconductor device (semiconductor integrated circuit device). For this reason, in consideration of impurity diffusion, it is necessary to reduce the dose during ion implantation in order to reduce the junction depth of the formed impurity diffusion layers (source, drain and its extension diffusion layer). This increases the resistance of the impurity diffusion layer to be formed, and may result in a high sheet resistance value such as 2000 to 3000 Ω / sq (2000 to 3000 Ω / □).

  In contrast, in this embodiment, a long wavelength laser annealing process is used for the annealing process in step S9 after ion implantation. Laser annealing, which is a laser-type annealing process, can raise the temperature locally by irradiating laser light, and uses the focusing property of the laser light. Can be warmed. For this reason, laser annealing can shorten the annealing time (heating time, laser light irradiation time) as compared with a lamp heating method or the like. Since the annealing time can be shortened, it is possible to suppress or prevent the introduced impurities from diffusing during the annealing. For this reason, the junction depth of the formed impurity diffusion layer can be reduced. Further, since the laser method is used, it is easy to control the short-time irradiation of the laser light, and even if the irradiation time of the laser light is short, the variation in the annealing temperature can be made relatively small.

Further, unlike the present embodiment, it is conceivable to use a short wavelength laser such as an excimer laser (for example, wavelength 308 nm) for the annealing process in step S9. In this case, since the light having the wavelength of the excimer laser is transparent to the oxide film, (1) the silicon region under the element isolation region 2 is dissolved, and (2) the semiconductor material is made of a semiconductor material such as polycrystalline silicon. The gate electrode 5 is also dissolved. (3) The dependence on the density difference of the pattern (pattern of the gate electrode 5) and the underlying material (on the silicon (active region) or on the oxide film (element isolation region)) May occur. Because of these problems, it is not easy to activate the impurities introduced into the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 with a short wavelength laser such as an excimer laser.

FIG. 7 is a graph showing the wavelength dependence of the absorption coefficient of silicon (Si). FIG. 8 is an explanatory diagram of intrinsic absorption, and FIG. 9 is an explanatory diagram of free carrier absorption. The horizontal axis of the graph of FIG. 7 corresponds to the wavelength of incident light, and the vertical axis of the graph of FIG. 7 corresponds to the absorption coefficient (Absorption coefficients) of silicon (Si). Further, in the graph of FIG. 7, when the impurity concentration in silicon is changed, here, for the ^three cases where the impurity concentration p is 10 ¹⁷ / cm ³ , 10 ¹⁸ / cm ³ and 10 ¹⁹ / cm ³ , silicon ( The dependence of the absorption coefficient of silicon (in which impurities are introduced) on the incident light wavelength is shown.

  As can be seen from the graph of FIG. 7, in the region where the wavelength of the incident light is relatively short, intrinsic absorption as shown in FIG. 8 occurs, and the shorter the wavelength of the incident light, the higher the absorption coefficient and the silicon is heated. As the incident light becomes longer, the absorption coefficient becomes lower and the silicon tends not to be heated. On the other hand, in the region where the wavelength of the incident light is relatively long, free electron absorption occurs as shown in FIG. 9, and the shorter the wavelength of the incident light, the lower the absorption coefficient is, making it difficult for the silicon to be heated. The coefficient tends to be high and silicon tends to be easily heated. Further, as can be seen from the graph of FIG. 7, the absorption coefficient due to intrinsic absorption (corresponding to the absorption coefficient in the region where the incident light wavelength is relatively short) does not depend on the impurity concentration in silicon, but the absorption coefficient due to free electron absorption. (Corresponding to the absorption coefficient in a region where the incident light wavelength is relatively long) depends on the impurity concentration in silicon, and the absorption coefficient tends to increase as the impurity concentration increases.

In this embodiment, a laser having a wavelength in a region where the absorption coefficient is relatively high due to free electron absorption, that is, a long wavelength laser is used for the annealing process in step S9 after ion implantation. The wavelength of the laser used is preferably 3 μm or more, more preferably 5 μm or more, and even more preferably 8 μm or more. For example, the annealing process in step S9 can be performed using a CO ₂ gas laser (wavelength 10.6 μm). By using a long wavelength laser, the above-mentioned problems (above (1) to (3)) that may occur when a short wavelength laser such as an excimer laser is used can be eliminated. Further, by setting the wavelength of the laser beam to preferably 3 μm or more, more preferably 5 μm or more, and even more preferably 8 μm or more, free electron absorption can easily occur and the absorption coefficient can be made relatively high, and the annealing time ( Laser light irradiation time) can be shortened. Also, the annealing temperature can be increased.

  Thus, by using the long wavelength laser annealing for the annealing process in step S9 after the ion implantation, the temperature can be raised and lowered in a shorter time at a higher temperature than in the lamp heating method or the like. Since the annealing time can be shortened, it is possible to suppress or prevent the introduced impurities from diffusing during the annealing. Therefore, the junction depth of the formed impurity diffusion layer can be reduced, which is advantageous for downsizing and high integration of the semiconductor device (semiconductor integrated circuit device). The annealing time by the long wavelength laser annealing in step S9 is preferably 100 msec (100 milliseconds) or less, more preferably 10 msec (10 milliseconds) or less, and even more preferably 1 msec (1 milliseconds) or less. Thereby, it is possible to more accurately suppress or prevent the introduced impurities from diffusing during annealing. In addition, since the annealing temperature can be increased, the solid solubility (solid solubility limit) of the impurities introduced into the silicon can be increased, and the resistance of the impurity diffusion layer after the annealing treatment (impurity activation) ( Resistivity) can be reduced. The annealing temperature of the long wavelength laser annealing in step S9 is preferably 1000 ° C. or higher, more preferably 1100 ° C. or higher, and further preferably 1200 ° C. or higher, thereby annealing treatment (impurity activation). The resistance (resistivity) of the subsequent impurity diffusion layer can be reduced more accurately.

The impurity concentration in the region (n ⁻ type semiconductor region 7 and / or n ⁺ type semiconductor region 9) activated by the long-wavelength laser annealing in step S9 is preferably 10 ¹⁸ / cm ³ or more, and preferably 10 ¹⁹ / More preferably, it is more preferably cm ³ or more, and even more preferably 10 ²⁰ / cm ³ or more. As can be seen from the graph of FIG. 7, the absorption coefficient due to free electron absorption (corresponding to the absorption coefficient in the region where the incident light wavelength is relatively long) depends on the impurity concentration in silicon, and the absorption coefficient increases as the impurity concentration increases. Tend to be. Free electron absorption is achieved by setting the impurity concentration in the region heated by irradiation with the long wavelength laser to preferably 10 ¹⁸ / cm ³ or more, more preferably 10 ¹⁹ / cm ³ or more, and even more preferably 10 ²⁰ / cm ³ or more. The absorption coefficient can be further increased and the annealing time (laser light irradiation time) can be shortened and the annealing temperature can be increased easily.

  FIG. 10 is a graph showing the impurity concentration distribution before and after annealing. The horizontal axis of the graph of FIG. 10 corresponds to the depth from the surface of the semiconductor substrate, and the vertical axis of the graph of FIG. 10 corresponds to the impurity concentration. The graph of FIG. 10 shows a state after ion implantation and before annealing (corresponding to “as-impla” in the graph of FIG. 10), and a state after ion implantation and long wavelength laser annealing treatment (graph of FIG. 10). Corresponds to “Long wavelength laser annealing (low irradiation intensity)” and “Long wavelength laser annealing (high irradiation intensity)”, and the size in parentheses corresponds to laser irradiation intensity), followed by ion annealing and lamp annealing treatment. The state of being performed (corresponding to “RTA (lamp annealing)” in the graph of FIG. 10) is shown.

  As can be seen from the graph of FIG. 10, when lamp annealing is performed after ion implantation, the annealing time (lamp light irradiation time) is relatively long, so that impurities diffuse during the annealing, and the impurity concentration distribution at the time of ion implantation. (Corresponding to “as-impla” in the graph of FIG. 10) cannot be maintained, and the impurity concentration distribution after lamp annealing is considerably different from the impurity concentration distribution during ion implantation. On the other hand, if long-wavelength laser annealing is performed after ion implantation, the annealing time can be shortened and the annealing temperature can be increased, impurities are hardly diffused, and the impurity concentration distribution during ion implantation can be maintained. That is, the impurity concentration distribution after the long wavelength laser annealing can be made almost the same as the impurity concentration distribution at the time of ion implantation.

FIG. 11 is a graph showing the correlation between the junction depth of the impurity diffusion layer formed by ion implantation and subsequent various annealings and the sheet resistance. FIG. 12 is a graph showing the sheet resistance of the impurity diffusion layer formed by ion implantation and subsequent annealing. The horizontal axis of the graph of FIG. 11 corresponds to the junction depth of the formed impurity diffusion layer (here, the junction depth at an impurity concentration of 10 ¹⁸ / cm ³ ), and the vertical axis of the graph of FIG. This corresponds to the sheet resistance of the impurity diffusion layer. The horizontal axis of the graph of FIG. 12 corresponds to the laser output (arbitrary unit: arbitrary unit) of the long wavelength laser annealing, and the vertical axis of the graph of FIG. 12 corresponds to the sheet resistance of the formed impurity diffusion layer. . In the graph of FIG. 11, unlike the case of the present embodiment, when the long wavelength laser annealing is performed after the ion implantation as in the present embodiment (corresponding to “long wavelength laser annealing” in the graph of FIG. 11), the ion implantation is different. Comparative example (corresponding to “RTA (ramp annealing)” in the graph of FIG. 11) in which RTA (Rapid Thermal Annealing) was performed later by lamp annealing and comparison in which flash lamp annealing was performed after ion implantation unlike this embodiment An example (corresponding to “flash lamp annealing” in the graph of FIG. 11) is shown. Further, in the graph of FIG. 12, the sheet resistance value dependency of the laser output when long-wavelength laser annealing is performed after ion implantation (corresponding to “long-wavelength laser annealing” in the graph of FIG. 12) as in the present embodiment. As a comparative example, the sheet resistance when RTA by lamp annealing is performed after ion implantation (corresponding to “RTA (ramp annealing)” in the graph of FIG. 12) is also plotted in the graph of FIG. It is.

  As can be seen from the graphs of FIGS. 11 and 12, the sheet resistance of the impurity diffusion layer to be formed can be reduced by performing the long wavelength laser annealing after the ion implantation. In addition, as can be seen from the graph of FIG. 11, by performing long wavelength laser annealing after ion implantation, it is possible to achieve both shallow junction of the impurity diffusion layer to be formed and reduction of sheet resistance (low resistance). Become. Therefore, the performance of the semiconductor device can be improved, and the semiconductor device can be miniaturized and highly integrated.

  In this embodiment, since the long wavelength laser annealing process is used for the annealing process in step S9 after the ion implantation, the diffusion of impurities during the annealing is suppressed. For this reason, the impurity concentration distribution at the time of ion implantation can be maintained even after the annealing process of step S9, and the impurity concentration distribution in the depth direction (direction perpendicular to the main surface of the semiconductor substrate 1) is the ideal impurity concentration distribution. It is possible to However, the introduced impurities are not diffused in the lateral direction of the semiconductor substrate 1 (the direction parallel to the main surface of the semiconductor substrate 1, the channel length direction of the MISFET 11) in the annealing process in step S9.

Therefore, unlike the present embodiment, the ion implantation process for forming the n ⁻ type semiconductor region (source / drain extension diffusion layer) 7 in step S6 is perpendicular to the main surface of the semiconductor substrate 1. When ion implantation is performed in the direction, the region into which the impurity is implanted (n ⁻ type semiconductor region 7) and the gate electrode 5 do not overlap, and impurities are present in the p-type well 3 below the end of the gate electrode 5. Not introduced. Since impurities in the long-wavelength laser annealing process subsequent step S9 hardly diffused, after the long-wavelength laser annealing process in the step S9, n ^- not overlap type semiconductor region 7 and the gate electrode 5, n ^- -type semiconductor region 7 does not extend below the end of the gate electrode 5. This degrades the characteristics of the n-channel type MISFET 11 to be formed, for example, lowers the drain current.

On the other hand, in the present embodiment, in the ion implantation step for forming the n ⁻ type semiconductor region (source / drain extension diffusion layer) 7 in step S 6, an oblique direction with respect to the main surface of the semiconductor substrate 1 ( Ions are implanted in a direction inclined at a predetermined angle from a direction perpendicular to the main surface of the semiconductor substrate 1. By performing ion implantation from an oblique direction with respect to the main surface of the semiconductor substrate 1, the region into which the impurity has been implanted (n ⁻ type semiconductor region 7) and the gate electrode 5 overlap, and the end of the gate electrode 5 is overlapped. Impurities are also introduced into the lower p-type well 3. The impurities are hardly diffused by the long-wavelength laser annealing process in the subsequent step S9. However, the p-type well 3 under the end of the gate electrode 5 has already been formed in the ion implantation process for forming the n ⁻ type semiconductor region 7 in the step S6. Since the impurity is also introduced into the n ⁻ type semiconductor region 7 and the gate electrode 5 after the long-wavelength laser annealing in step S 9, the n ⁻ type semiconductor region 7 is formed at the end of the gate electrode 5. It will also extend downward. Thereby, the characteristics of the n-channel type MISFET 11 to be formed can be improved, and for example, the drain current can be increased. The length in the channel length direction of the overlap region between the n ⁻ -type semiconductor region 7 and the gate electrode 5 is preferably 1 nm or more, whereby the characteristics of the n-channel MISFET 11 can be improved more accurately. Therefore, the performance of the semiconductor device can be improved.

FIG. 13 is a graph showing I _off -I _on characteristics of an n-channel MISFET. The horizontal axis of the graph of FIG. 13 corresponds to the current I _on between the source and the drain when the MISFET is turned _on , and the vertical axis of the graph of FIG. 13 is between the source and the drain when the MISFET is turned off. Current I _off (leakage current). Further, in the graph of FIG. 13, in the ion implantation process for forming the n ⁻ type semiconductor region 7 in step S 6, the ion implantation is performed obliquely with respect to the main surface of the semiconductor substrate 1 as in the present embodiment. When this is performed (corresponding to “oblique ion implantation” in the graph of FIG. 13), and in the case of a comparative example in which ion implantation is performed in a direction perpendicular to the main surface of the semiconductor substrate 1 (FIG. 13). 13 corresponds to “vertical ion implantation”), and in both cases, the MISFET is formed by substantially the same manufacturing process except for the ion implantation process of step S6.

As shown in the graph of FIG. 13, compared to the comparative example in which the ion implantation for forming the n ⁻ type semiconductor region 7 in step S 6 is performed in the direction perpendicular to the main surface of the semiconductor substrate 1. The value of I _{on at} the same I _off becomes larger when the operation is performed obliquely with respect to the main surface of the semiconductor substrate 1 as in the present embodiment. The ion implantation for forming the n ⁻ type semiconductor region 7 in step S 6 is performed in an oblique direction with respect to the main surface of the semiconductor substrate 1, thereby overlapping the n ⁻ type semiconductor region 7 and the gate electrode 5. The leakage current (I _off ) of the MISFET can be reduced, and the source / drain current (I _on ) of the MISFET can be increased.

In this manner, ion implantation for forming the n ⁻ type semiconductor region 7 in step S6 is performed obliquely with respect to the main surface of the semiconductor substrate 1, and the n ⁻ type semiconductor region 7 and n ^{+ in} step 9 are performed. It is important to combine the annealing process for activating the impurities in the type semiconductor region 9 with long-wavelength laser annealing. In the present embodiment, ion implantation for forming the n ⁻ type semiconductor region 7 in step S 6 is performed in an oblique direction with respect to the main surface of the semiconductor substrate 1, so that the p under the end of the gate electrode 5 is formed. Impurities are also introduced into the type well 3 to overlap the n ⁻ type semiconductor region 7 and the gate electrode 5 to activate the impurities in the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 in step 9. In the annealing process, the introduced impurities are suppressed or prevented from diffusing during annealing by performing long-wavelength laser annealing. Since the impurity concentration distribution during the ion implantation in step S6 and step S8 can be maintained even after the annealing process in step S9, the n ⁻ type semiconductor region 7 can be obtained by adjusting the ion implantation conditions in step S6 and step S8. In addition, the impurity concentration distribution of the n ⁺ type semiconductor region 9 can be controlled, and a desired impurity concentration distribution can be obtained easily and accurately. Further, by adjusting the conditions of the ion implantation 7a for forming the n ⁻ type semiconductor region 7 in step S6 (for example, the angle of the ion implantation 7a), the gate electrode 5 and the source / drain extension diffusion layers (n ⁻ type) are formed. The overlap length with the semiconductor region 7) can be controlled with high accuracy.

When ion implantation is performed using any mask (here, the gate electrode 5 and the insulating film 6) like the source / drain extension diffusion layer (n ⁻ type semiconductor region 7), the direction perpendicular to the main surface of the semiconductor substrate 1 When ion implantation is performed, one-dimensional (direction perpendicular to the main surface of the semiconductor substrate 1, depth direction, device vertical direction) has a low resistance and shallow junction (impurity diffusion) due to the impurity concentration distribution caused by the ion implantation itself. In the long-wavelength laser annealing process, the annealing time (laser irradiation time) is short, so that it is two-dimensional (direction parallel to the main surface of the semiconductor substrate 1, lateral direction, device lateral direction). Impurities are not sufficiently diffused, an overlap region between the gate electrode 5 and the source / drain extension diffusion layer (n ⁻ type semiconductor region 7) is not formed, and the drain current (Source / drain current) is reduced. As in the present embodiment, ion implantation for forming the source / drain extension diffusion layer (n ⁻ type semiconductor region 7) (ion implantation in step S6) is performed obliquely with respect to the main surface of the semiconductor substrate 1. By doing so, a necessary overlap region between the gate electrode 5 and the source / drain extension diffusion layer (n ⁻ type semiconductor region 7) can be secured, the diffusion layer resistance in this region is reduced, and the drain current (source / drain) is reduced. Current) can be prevented, and hot carrier deterioration can be prevented.

As described above, in the present embodiment, the overlap length between the gate electrode 5 and the source / drain extension diffusion layer (n ⁻ type semiconductor region 7) is controlled with high accuracy, and the activation of the junction itself, ie, low It is possible to achieve both resistance and steep (shallow junction) impurity distribution in the vertical and horizontal directions. Therefore, the performance of the semiconductor device can be improved, and the semiconductor device (semiconductor integrated circuit device) can be downsized and highly integrated.

(Embodiment 2)
FIG. 14 is a process flow diagram showing manufacturing steps of a semiconductor device according to another embodiment of the present invention. 15 and 16 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process. Since the manufacturing process up to (step S5 in FIG. 2) is the same as that in the first embodiment, the description thereof is omitted here, and the subsequent manufacturing process will be described.

  After the steps S1 to S5 are performed in the same manner as in the first embodiment to form the structure shown in FIG. 2, as shown in FIG. 15, on the side wall of the gate electrode 5, for example, silicon oxide or A sidewall (offset spacer, sidewall spacer, sidewall insulating film) 20 made of a thin insulating film such as silicon nitride is formed (step S21). Similar to the sidewall 8, the sidewall 20 can be formed by depositing an insulating film such as a silicon oxide film on the semiconductor substrate 1 and anisotropically etching the insulating film. The thickness of the sidewall 20 is made thinner than the thickness of the sidewall 8.

The subsequent steps are the same as those in the first embodiment. That is, as shown in FIG. 16, (a pair of) n ⁻ -type semiconductor regions 7 are formed by ion-implanting n-type impurities such as arsenic (As) into the regions on both sides of the gate electrode 5 of the p-type well 3. Is formed (step S6). In the ion implantation 7a in step S6, ions are implanted in an oblique direction with respect to the main surface of the semiconductor substrate 1 as in the first embodiment. Further, step S7 and subsequent steps are performed in the same manner as in the first embodiment, but the description thereof is omitted here.

  Also in this embodiment, the same effect as in the first embodiment can be obtained. Furthermore, in the present embodiment, ion implantation in step S6 is performed with the sidewall 20 formed on the sidewall of the gate electrode 5. For this reason, even if ions are implanted obliquely with respect to the main surface of the semiconductor substrate 1 in step S6, the gate electrode 5 can be prevented from being damaged by the ion implantation. Therefore, the characteristics and reliability of the formed MISFET 11 can be further improved. Moreover, when the formation of the sidewall 20 is omitted as in the first embodiment, the number of manufacturing steps can be reduced, and the manufacturing time and the manufacturing cost can be reduced.

(Embodiment 3)
FIG. 17 is a process flow diagram showing a manufacturing process of a semiconductor device according to another embodiment of the present invention. 18 and 19 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process. Since the manufacturing process up to (step S5 in FIG. 2) is the same as that in the first embodiment, the description thereof is omitted here, and the subsequent manufacturing process will be described.

As shown in FIG. 18, after the steps S1 to S5 are performed in the same manner as in the first embodiment to form the structure shown in FIG. 2 and before the ion implantation 7a in step S6, p Ge (germanium) is ion-implanted at a high concentration in regions on both sides of the gate electrode 5 of the mold well 3 to form an amorphous layer 30 having a depth of, for example, about 20 nm from the surface of the semiconductor substrate 1 (p-type well 3) (see FIG. Step S31). In the ion implantation (pre-amorphization ion implantation) 30a in step S31, the acceleration energy can be set to, for example, about 10 keV, and the dose (implantation amount) can be set to, for example, 10 ¹⁴ / cm ² or more. Similarly to the ion implantation 7a in step S6 of the first embodiment, the ion implantation 30a in step S31 is also performed in a predetermined direction from a direction oblique to the main surface of the semiconductor substrate 1, that is, a direction perpendicular to the main surface of the semiconductor substrate 1. Impurity ions can also be incident and implanted in a direction inclined at an angle. In addition to Ge, Si (silicon) ion implantation may be used as the ion implantation 30a in step S31.

The subsequent steps are the same as those in the first embodiment. That is, as shown in FIG. 19, by ion-implanting n-type impurities such as arsenic (As) into regions on both sides of the gate electrode 5 of the p-type well 3, (a pair of) n ⁻ -type semiconductor regions 7 Is formed (step S6). In the ion implantation 7a in step S6, ions are implanted in an oblique direction with respect to the main surface of the semiconductor substrate 1 as in the first embodiment. Further, step S7 and subsequent steps are performed in the same manner as in the first embodiment, but the description thereof is omitted here. Further, after the sidewall 20 is formed on the side wall of the gate electrode 5 as in step S21 in the second embodiment, Ge ion implantation in step S31 in the present embodiment can be performed. Further, the region (amorphous layer 30) that has been made amorphous by the ion implantation 30a in step S31 is recrystallized in the long wavelength laser annealing process in step S9.

FIG. 20 is a graph showing the threshold voltage of an n-channel type MISFET. The horizontal axis of the graph of FIG. 20 corresponds to the gate length, and the vertical axis of the graph of FIG. 20 corresponds to the threshold voltage _Vth . The graph of FIG. 20 shows the case of this embodiment in which ion implantation 30a for preamorphization is performed (corresponding to “with preamorphization ion implantation” in the graph of FIG. 20), and for preamorphization. The case of Embodiment 1 in which the ion implantation 30a is not performed (corresponding to “no pre-amorphization ion implantation” in the graph of FIG. 20) is shown, and these are subjected to the long wavelength laser annealing treatment as described above. It has been broken. Further, as a comparative example, the graph of FIG. 20 also shows the case where the annealing process in step S9 is performed by RTA such as lamp annealing (corresponding to “RTA (lamp annealing)” in the graph of FIG. 20).

  As shown in the graph of FIG. 20, the threshold value of the MISFET when the gate length is shortened by performing the oblique ion implantation in step S6 and the long wavelength laser annealing in step S9 as in the first embodiment. Although the voltage drop (short channel effect) can be suppressed, the threshold value of the MISFET when the gate length is shortened by performing the pre-amorphization ion implantation 30a in step S31 as in the present embodiment. It becomes possible to further suppress the voltage drop (short channel effect). Therefore, the gate length of the MISFET can be shortened, which is advantageous for downsizing and high integration of the semiconductor device (semiconductor integrated circuit device).

  In addition, after the ion implantation process for pre-amorphization in step S31 and before the long-wavelength laser annealing process in step 9 (that is, the process between step S31 and step S9), the process temperature (the temperature of the semiconductor substrate) Preferably does not exceed 450 ° C. For example, it is preferable that the film formation temperature (CVD film formation temperature) of the insulating film for forming the sidewall 8 in step S7 is 450 ° C. or lower. As a result, the state in which the surface layer portions (for example, the region from the surface to a depth of about 20 nm, the amorphous layer 30) in the regions on both sides of the gate electrode 5 of the p-type well 3 are amorphized until the long wavelength laser annealing step in step S9. This can be maintained, and the effect of suppressing the decrease in the threshold voltage of the MISFET when the gate length is shortened as described above can be obtained more accurately.

(Embodiment 4)
FIG. 21 is a process flow diagram showing manufacturing steps of a semiconductor device according to another embodiment of the present invention. 22 to 24 are main-portion cross-sectional views during the manufacturing process of the semiconductor device of the present embodiment. Since the manufacturing process up to (step S5 in FIG. 2) is the same as that in the first embodiment, the description thereof is omitted here, and the subsequent manufacturing process will be described.

After the steps S1 to S5 are performed in the same manner as in the first embodiment and the structure shown in FIG. 2 is formed, before the ion implantation 7a in step S6 is performed, in this embodiment, FIG. As shown, the sidewall 8 is formed on the sidewall of the gate electrode 5 in the same manner as in step S7 of the first embodiment. Then, in the same manner as in step S8 of the first embodiment, an n-type impurity such as arsenic (As) is ion-implanted into regions on both sides of the gate electrode 5 and the sidewall 8 of the p-type well 3 ( A pair of n ⁺ -type semiconductor regions 9 are formed. Further, after the ion implantation for forming the n ⁺ type semiconductor region 9, annealing treatment can be performed at 1050 ° C. for about 1 second, thereby making the impurity concentration distribution in the n ⁺ type semiconductor region 9 uniform. It can also be made.

Next, as shown in FIG. 23, the sidewall 8 is removed (step S41). Then, in the same manner as in step S6 of the first embodiment, n-type impurities such as arsenic (As) are ion-implanted into regions on both sides of the gate electrode 5 of the p-type well 3, thereby (a pair of) n ^A -type semiconductor region 7 is formed. In this ion implantation 7a, ions are implanted in an oblique direction with respect to the main surface of the semiconductor substrate 1, as in the first embodiment.

Next, in the same manner as in step S9 in the first embodiment, a long wavelength laser annealing process is performed in order to activate the impurities introduced into the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9.

Next, as shown in FIG. 24, a sidewall (sidewall spacer, sidewall insulating film) 8a made of an insulating film such as silicon oxide, silicon nitride, or a laminated film thereof is formed on the sidewall of the gate electrode 5. Next, as shown in FIG. (Step S42). The sidewall 8a can be formed in the same manner as the sidewall 8. By forming the sidewall 8a, it is possible to prevent the silicide film 12b on the n ⁺ type semiconductor region 9 from coming into contact with the gate electrode 5 when the silicide films 12a and 12b are subsequently formed.

  The subsequent steps are the same as those in the first embodiment. That is, the silicide films 12a and 12b, the insulating film 13, the contact hole 14, the plug 15, the wiring 16, the insulating film 17, and the like are formed, but the description thereof is omitted here. Further, after removing the sidewall 8 in step S41, the sidewall 20 is formed on the side wall of the gate electrode 5 as in step S21 of the second embodiment, and then the ion implantation in step S6 of the present embodiment. 7a can also be performed. In addition, after the sidewall 8 is removed in step S41, the ion implantation 30a for preamorphization is performed as in step S31 of the third embodiment, and then the ion implantation 7a of step S6 of the present embodiment is performed. It can also be done.

Also in this embodiment, substantially the same effect as in the first to third embodiments can be obtained. Further, in the present embodiment, the sidewall 8 does not exist on the n ⁻ type semiconductor region 7 in the long wavelength laser annealing process in step S9. For this reason, even if the annealing time of the long wavelength laser annealing treatment is short, the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 can be heated more uniformly.

(Embodiment 5)
FIG. 25 is a process flow diagram showing manufacturing steps of the semiconductor device according to another embodiment of the present invention. 26 and 27 are fragmentary cross-sectional views of the semiconductor device of the present embodiment during the manufacturing process. Since the manufacturing process up to (step S8) in FIG. 5 is the same as that in the first embodiment, the description thereof will be omitted here, and the subsequent manufacturing process will be described.

After the structure shown in FIG. 5 is formed by performing steps S1 to S8 in the same manner as in the first to third embodiments, before the long wavelength laser annealing process in step S9 is performed, in this embodiment, As shown in FIG. 26, the sidewall 8 is removed (step S51). After removing the side wall 8, in order to activate the impurities introduced into the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 as in step S9 of the first embodiment, a long wavelength laser annealing process is performed. I do.

Next, as shown in FIG. 27, on the side wall of the gate electrode 5, a side wall (side wall spacer, side wall insulating film) 8b made of an insulating film such as silicon oxide, silicon nitride, or a laminated film thereof is formed. (Step S52). The sidewall 8b can be formed in the same manner as the sidewall 8. By forming the sidewall 8b, it is possible to prevent the silicide film 12b on the n ⁺ type semiconductor region 9 from coming into contact with the gate electrode 5 when the silicide films 12a and 12b are subsequently formed.

  The subsequent steps are the same as those in the first embodiment. That is, the silicide films 12a and 12b, the insulating film 13, the contact hole 14, the plug 15, the wiring 16, the insulating film 17, and the like are formed, but the description thereof is omitted here.

Also in this embodiment, substantially the same effect as in the first to third embodiments can be obtained. Further, in the present embodiment, the sidewall 8 does not exist on the n ⁻ type semiconductor region 7 in the long wavelength laser annealing process in step S9. For this reason, even if the annealing time of the long wavelength laser annealing treatment is short, the n ⁻ type semiconductor region 7 and the n ⁺ type semiconductor region 9 can be heated more uniformly.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The present invention is effective when applied to a method of manufacturing a semiconductor device having a MISFET.

It is a process flow figure showing a manufacturing process of a semiconductor device which is one embodiment of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is one embodiment of this invention. FIG. 3 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 2; FIG. 4 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 3; FIG. 5 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 4; FIG. 6 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 5; It is a graph which shows the wavelength dependence of the absorption coefficient of silicon. It is explanatory drawing of intrinsic absorption. It is explanatory drawing of free electron absorption. It is a graph which shows impurity concentration distribution before and behind annealing. It is a graph which shows the correlation with the junction depth and sheet resistance of the impurity diffusion layer formed by ion implantation and subsequent various annealing. It is a graph which shows the sheet resistance of the impurity diffusion layer formed by ion implantation and subsequent annealing. Is a graph showing the I _off -I _on characteristics of MISFET. It is a process flow figure showing a manufacturing process of a semiconductor device which is other embodiments of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 16 is a fragmentary cross-sectional view of the semiconductor device during a manufacturing step following that of FIG. 15; It is a process flow figure showing a manufacturing process of a semiconductor device which is other embodiments of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 19 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 18; It is a graph which shows the threshold voltage of n channel type MISFET. It is a process flow figure showing a manufacturing process of a semiconductor device which is other embodiments of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 23 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 22; FIG. 24 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 23; It is a process flow figure showing a manufacturing process of a semiconductor device which is other embodiments of the present invention. It is principal part sectional drawing in the manufacturing process of the semiconductor device which is other embodiment of this invention. FIG. 27 is an essential part cross sectional view of the semiconductor device during a manufacturing step following FIG. 26;

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 Element isolation region 3 P-type well 4 Gate insulating film 5 Gate electrode 6 Insulating film 7 N ^- type semiconductor region 7a Ion implantation 8 Side wall 8a Side wall 8b Side wall 9 n ⁺ type semiconductor region 9a Ion implantation 11 MISFET
12a silicide film 12b silicide film 13 insulating film 14 contact hole 15 plug 15a barrier film 16 wiring 16a titanium film 16b titanium nitride film 16c aluminum film 16d titanium film 16e titanium nitride film 17 insulating film 20 sidewall 30a ion implantation 30 amorphous layer

Claims (5)

A method of manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate having a first semiconductor region of a first conductivity type;
(B) forming a gate insulating film on the first semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) In order to form a second semiconductor region of a second conductivity type, a part of which is located below the gate electrode, in the first semiconductor region on both sides of the gate electrode, A process of introducing impurities by performing ion implantation in an oblique direction,
(E) forming a sidewall insulating film on the sidewall of the gate electrode;
(F) After the step (e), in order to form second conductive type third semiconductor regions whose end portions are separated from the lower portions of the side walls of the gate electrode in the first semiconductor regions on both sides of the gate electrode, A step of introducing impurities by performing ion implantation;
(G) A step of performing long-wavelength laser annealing with a wavelength of 3 μm or more in order to activate the impurities introduced in the steps (d) and (f). A method of manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate having a first semiconductor region of a first conductivity type;
(B) forming a gate insulating film on the first semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) forming a first sidewall insulating film on the sidewall of the gate electrode;
(E) In order to form a second semiconductor region of a second conductivity type, a part of which is located below the gate electrode, in the first semiconductor region on both sides of the gate electrode, A process of introducing impurities by performing ion implantation in an oblique direction,
(F) forming a second sidewall insulating film on the sidewall of the gate electrode;
(G) After the step (f), in order to form second conductive type third semiconductor regions whose end portions are separated from the lower portions of the side walls of the gate electrode in the first semiconductor regions on both sides of the gate electrode, A step of introducing impurities by performing ion implantation;
(H) A step of performing long wavelength laser annealing with a wavelength of 3 μm or more in order to activate the impurities introduced in the steps (e) and (g). A method of manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate having a first semiconductor region of a first conductivity type;
(B) forming a gate insulating film on the first semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) performing an ion implantation of Ge or Si to amorphize the first semiconductor region on both sides of the gate electrode;
(E) After the step (d), in order to form a second semiconductor region of a second conductivity type, a part of which is located below the gate electrode, in the first semiconductor region on both sides of the gate electrode, A process of introducing impurities by implanting ions in an oblique direction with respect to the main surface of the semiconductor substrate;
(F) forming a sidewall insulating film on the sidewall of the gate electrode;
(G) After the step (f), in order to form second conductive type third semiconductor regions whose end portions are separated from the lower portions of the side walls of the gate electrode in the first semiconductor regions on both sides of the gate electrode, A step of introducing impurities by performing ion implantation;
(H) A step of performing long wavelength laser annealing with a wavelength of 3 μm or more in order to activate the impurities introduced in the steps (e) and (g). A method of manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate having a first semiconductor region of a first conductivity type;
(B) forming a gate insulating film on the first semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) forming a sidewall insulating film on the sidewall of the gate electrode;
(E) After the step (d), in order to form a second conductivity type second semiconductor region whose end is separated from the lower side of the side wall of the gate electrode in the first semiconductor region on both sides of the gate electrode, A step of introducing impurities by performing ion implantation;
(F) The step of removing the sidewall insulating film after the step (e),
(G) After the step (f), in order to form a second conductivity type third semiconductor region, a part of which is located below the gate electrode, in the first semiconductor region on both sides of the gate electrode, A process of introducing impurities by implanting ions in an oblique direction with respect to the main surface of the semiconductor substrate;
(H) A step of performing long wavelength laser annealing with a wavelength of 3 μm or more in order to activate the impurities introduced in the steps (e) and (g). A method of manufacturing a semiconductor device comprising the following steps:
(A) preparing a semiconductor substrate having a first semiconductor region of a first conductivity type;
(B) forming a gate insulating film on the first semiconductor region;
(C) forming a gate electrode on the gate insulating film;
(D) In order to form a second semiconductor region of a second conductivity type, a part of which is located below the gate electrode, in the first semiconductor region on both sides of the gate electrode, A process of introducing impurities by performing ion implantation in an oblique direction,
(E) forming a sidewall insulating film on the sidewall of the gate electrode;
(F) After the step (e), in order to form second conductive type third semiconductor regions whose end portions are separated from the lower portions of the side walls of the gate electrode in the first semiconductor regions on both sides of the gate electrode, A step of introducing impurities by performing ion implantation;
(G) a step of removing the sidewall insulating film after the step (f);
(H) A step of performing long-wavelength laser annealing with a wavelength of 3 μm or more in order to activate the impurities introduced in the steps (d) and (f) after the step (g).

Images