JP4679830B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a metal silicide film on a source / drain region.

  In recent years, high integration in semiconductor integrated circuit devices has greatly advanced. In MOS (Metal Oxide Semiconductor) type semiconductor devices, miniaturization of elements such as transistors and high performance have been achieved. In particular, with regard to the gate insulating film which is one of the elements constituting the MOS structure, the thinning is rapidly progressing to cope with the miniaturization, high speed operation and low voltage of the transistor.

Conventionally, a silicon oxide film (SiO ₂ film), a silicon oxynitride film (SiON film), or the like has been used as a material constituting the gate insulating film. However, when these materials are used, there is a problem that leakage current increases as the film thickness is reduced. In a sub 0.1 μm generation CMOS (Complementary Metal Oxide Semiconductor), the gate insulating film requires a performance of 1.5 nm or less in terms of a silicon oxide equivalent film thickness. For this reason, a material having a large relative dielectric constant such as a metal oxide film or a metal silicate film (metal silicate film) is used as a gate insulating film, and leakage current is suppressed by increasing the film thickness.

  On the other hand, CMOS (Complementary Metal Oxide Semiconductor) using silicon as the gate electrode material has a problem in that the inversion capacitance is reduced due to the presence of a depletion layer formed in the vicinity of the gate insulating film and the device performance is lowered. On the other hand, instead of silicon, a method has been proposed in which a metal or a material having a band structure equivalent to that of a metal is used as a gate electrode material, thereby suppressing depletion of the electrode and ensuring a large inversion capacitance. (Refer nonpatent literature 1.).

Further, conventionally, a metal silicide layer such as titanium silicide (TiSi ₂ ), cobalt silicide (CoSi ₂ ) or nickel silicide (NiSi) is used to reduce the resistance of the source / drain regions in the MOSFET. It has been made to form. In particular, nickel silicide is known as a material that effectively suppresses an increase in layer resistance and gate leakage current associated with device miniaturization.

A. Chatterjee et al., International Electron Devices Meeting (IEDM), 1997, p. 821

  However, when a high dielectric constant insulating film such as hafnium oxide is used as the gate insulating film and a nickel silicide film is formed in the source / drain region, the resistance of the source / drain region is reduced and the gate leakage current is reduced. There was a problem of being unable to achieve both. The reason is considered as follows.

  In general, a CVD (Chemical Vapor Deposition) method is used to form a metal oxide such as hafnium oxide. The film formation is performed at a low temperature in order to reduce the influence on the impurity distribution in the substrate. In this case, since a film formed at a low temperature contains many dangling bonds and impurities, it is necessary to perform a heat treatment (post deposition annealing) at a temperature of 600 ° C. or higher after the film formation. However, such heat treatment at a high temperature causes aggregation in the nickel silicide film on the source / drain regions formed earlier, so that the nickel silicide film loses a continuous structure and the layer resistance increases. Further, as the thickness of the aggregated nickel silicide islands increases, the PN junction approaches and the gate leakage current increases.

  As described above, when the nickel silicide film is formed on the source / drain regions before the gate insulating film is formed, heat of 600 ° C. or more is applied at the time of forming the gate insulating film from the viewpoint of nickel silicide aggregation resistance. There was a problem that I could not. For this reason, the thermal process of the gate insulating film must be performed at a temperature of 600 ° C. or less, and it has been difficult to improve the film quality of the gate insulating film.

  The present invention has been made in view of such problems. That is, an object of the present invention is to provide a method of manufacturing a semiconductor device that can achieve both a reduction in resistance of a source / drain region and a reduction in gate leakage current.

  Other objects and advantages of the present invention will become apparent from the following description.

In the present invention, a step of forming a sacrificial gate electrode on a silicon substrate via a sacrificial gate insulating film, a step of forming a side wall insulating film on a side wall portion of the sacrificial gate electrode, and the formation of the side wall insulating film Using the sacrificial gate electrode as a mask, implanting impurities into the silicon substrate to form source / drain regions, forming a first metal silicide film on the source / drain regions, and embedding the sacrificial gate electrode Forming an interlayer insulating film on the silicon substrate, processing the interlayer insulating film to expose the surface of the sacrificial gate electrode, and etching the sacrificial gate electrode to expose the sacrificial gate insulating film When a step of forming a groove portion reaching the silicon substrate by etching the sacrificial gate insulating film, a gate insulating film on the inner surface and the interlayer insulating film of the groove 55 ℃ and forming below, heating and forming a heat absorbing film on the gate insulating film, at least one of the flash and the laser beam to the gate insulating film by irradiating the silicon substrate from the side of the heat absorbing film processing possess a step, the performing, and is characterized in that to perform the respective steps as described above in the order described above.

  In the method for manufacturing a semiconductor device of the present invention, the heat absorption film can be a silicon film. In this case, a step of forming a metal film on the silicon film after the heat treatment, and a step of reacting the silicon film and the metal film by the heat treatment to form a second metal silicide film on the gate insulating film. You can also have. The film thickness of the silicon film is preferably 30 nm or more. The silicon film is preferably an amorphous silicon film.

  In the method for manufacturing a semiconductor device of the present invention, the gate insulating film may have a high dielectric constant insulating film. In this case, the high dielectric constant insulating film can be an oxide film or a silicate film of at least one metal selected from the group consisting of hafnium, zirconium, lanthanum, and cesium.

  As described above, according to the present invention, a heat absorption film is formed on a gate insulating film, and at least one of flash light and laser light is irradiated to the silicon substrate from the side of the heat absorption film to heat-treat the gate insulating film. As a result, the gate insulating film can be efficiently heated without causing aggregation of the first metal silicide film.

  A method for manufacturing a semiconductor device according to the present embodiment will be described with reference to FIGS. In these drawings, the same reference numerals indicate the same parts.

  First, a silicon oxide film is embedded in a predetermined region of the silicon substrate 1, and an element isolation insulating film 2 and a sacrificial gate insulating film 3 having an STI (Shallow Trench Isolation) structure are formed (FIG. 1). The film thickness of the element isolation insulating film 2 can be about 300 nm, for example. The sacrificial gate insulating film 3 can be a silicon oxide film having a thickness of about 5 nm, for example. In this case, the silicon oxide film is preferably formed by oxidation at a high temperature of 700 ° C. or higher. Thereby, since a dense silicon oxide film can be formed, damage to the silicon substrate 1 can be reduced when the dummy gate electrode is removed in a later step.

Next, after implanting B (boron) into the silicon substrate 1, the impurity is diffused by performing a heat treatment to form the P-type diffusion layer 4 shown in FIG. 1. For example, after implanting B with an implantation energy of 130 keV and a dose of 5 × 10 ¹² cm ⁻² , heat treatment can be performed at a temperature of 900 ° C.

  Next, a polycrystalline silicon film 5 is formed to a thickness of about 150 nm by a CVD (Chemical Vapor Deposition) method. By forming the silicon film 5 with a thin film thickness, the shape of the gate electrode formed in a later process can be improved.

  Next, after forming a silicon nitride film 6 with a film thickness of about 50 nm on the silicon film 5, the silicon nitride film 6 is processed into a predetermined shape using a lithography technique. Then, using the processed silicon nitride film 6 as a hard mask, the silicon film 5 is processed into the shape of the gate electrode (FIG. 2). In FIG. 2, a silicon film 5 is a sacrificial gate electrode, and a gate electrode that actually operates is formed in a later step. A silicon oxide film may be formed instead of the silicon nitride film and used as a hard mask.

  Thereafter, the exposed sacrificial gate insulating film 3 is removed by etching using the silicon nitride film 6 as a hard mask (FIG. 3).

Next, As is selectively ion-implanted into the region of the P-type diffusion layer 4 using the silicon nitride film 6 as a mask. Thereafter, activation by heat treatment is performed to form an N-type extension region 7 (FIG. 4). For example, As can be implanted at an implantation energy of 5 keV and a dose of 3 × 10 ¹⁴ cm ⁻² . In order to suppress the short channel effect, a halo region (not shown) may be formed by further ion implantation of B. The implantation of B can be performed, for example, with an implantation energy of 10 keV and a dose amount of 3 × 10 ¹⁴ cm ⁻² .

  Next, after forming a silicon nitride film 8 as a sidewall insulating film on the entire surface, the silicon nitride film 8 is removed by reactive ion etching except for the sidewall portion of the sacrificial gate electrode portions (5, 6). Thereby, the structure shown in FIG. 5 is obtained. A silicon oxide film may be used instead of the silicon nitride film.

Next, As is selectively ion-implanted into the region of the P-type diffusion layer 4 using the sacrificial gate electrode portion (5, 6) on which the silicon nitride film 8 is formed as a mask. After removing the resist, activation by heat treatment is performed, whereby the N-type source / drain regions 9 can be formed (FIG. 6). For example, after implanting As with an implantation energy of 30 keV and a dose of 5 × 10 ¹⁵ cm ⁻² , heat treatment can be performed at a temperature of 1,000 ° C. for 3 seconds.

  Next, after a nickel film 10 is deposited on the entire surface by sputtering, heat treatment is performed to form a nickel silicide film 11 (first metal silicide film) on the source / drain regions 9 (FIG. 7). Here, since the silicon nitride film 6 is formed on the silicon film 5, the nickel silicide film 11 is not formed in this portion. The film thickness of the nickel film 10 can be set to, for example, about 10 nm. Further, the heat treatment at the time of silicidation can be set to about 450 ° C., for example.

  After the silicidation is completed, the unreacted nickel film 10 is removed using a mixed solution of ammonia, hydrogen peroxide solution and water.

  Next, as the first interlayer insulating film 12, a silicon oxide film is formed on the entire surface by plasma CVD (FIG. 8). Here, the thickness of the first interlayer insulating film 12 is set to be equal to or greater than the value obtained by adding the thickness of the silicon nitride film 6 to the thickness of the silicon film 5. For example, the thickness of the first interlayer insulating film 12 can be about 100 nm to 300 nm.

  The first interlayer insulating film 12 may be formed by stacking two or more insulating films having different refractive indexes. Since a certain amount of light is reflected at the interface of media having different refractive indexes, it is possible to control the light transmittance of the entire first interlayer insulating film 12 by appropriately selecting the material and film thickness. become. For example, after forming a silicon nitride film by plasma CVD at a low temperature of about 450 ° C., a silicon oxide film may be similarly formed thereon to form the first interlayer insulating film 12. In this way, the reflectivity of the first interlayer insulating film 12 is increased, and the heat treatment of the gate insulating film 14 to be described later is performed using at least one of flash light and laser light. It is possible to heat the gate insulating film 14 while suppressing the temperature rise of the nickel silicide film 11 formed in the above.

  Next, the surface of the first interlayer insulating film 12 is flattened using a CMP (Chemical Mechanical Polishing) method until the surface of the silicon nitride film 6 is exposed. Thereafter, the silicon nitride film 6 is removed, and the silicon film 5 is selectively removed by dry etching. Thereby, the structure shown in FIG. 9 is obtained.

  Next, the sacrificial gate insulating film 3 exposed by the removal of the silicon film 5 is selectively removed by dry etching or wet etching to form a groove 13 reaching the silicon substrate 1 (FIG. 10).

  Next, a gate insulating film 14 is formed on the inner surface of the trench 13 and the first interlayer insulating film 12 (FIG. 11). For example, a silicon oxynitride film is formed by combining a low-temperature (550 ° C. or lower) plasma oxidation method and a plasma nitridation method. Alternatively, a hafnium oxide film having a thickness of about 3 nm may be formed after a silicon oxide film having a thickness of about 1 nm is formed. Also in this case, the silicon oxide film and the hafnium oxide film are preferably formed at a low temperature so as not to change the impurity distribution in the silicon substrate 1 as much as possible. In addition, a high dielectric constant insulating film other than the hafnium oxide film may be used. For example, at least one or more selected from the group consisting of hafnium (Hf), zirconium (Zr), lanthanum (La), and cerium (Ce). A metal oxide film or a silicon oxide film can be used.

  After the gate insulating film 14 is formed, a heat treatment for removing dangling bonds and impurities contained in the gate insulating film 14 is performed. In this embodiment, this heat treatment is performed for a short time (for example, several millimeters). It is characterized by using a heat source that radiates strong energy in a time of less than a second) and forming a heat absorption film before heat treatment. Specifically, the gate insulating film 14 is heat-treated by irradiating the substrate with the flash 23 from the heat absorption film 15 side (FIG. 12). Note that laser light may be irradiated instead of flash light, and both flash light and laser light may be irradiated. In this sense, in the present embodiment, the heat absorption film 15 can also be referred to as a light shielding film. The flash light irradiation can be performed using, for example, a xenon flash lamp, and the laser light irradiation can be performed using, for example, an infrared laser.

  By providing the heat absorption film 15, the energy of light transmitted through the heat absorption film 15 can be reduced. Accordingly, as shown in FIG. 12, by forming the heat absorption film 15 on the inner surface of the groove 13 and the first interlayer insulating film 12, the nickel silicide film 11 formed on the source / drain region 9 is In addition to the light shielding by the interlayer insulating film 12, the heat absorption film 15 is also shielded. For this reason, since the light energy reaching the nickel silicide film 11 is reduced, the heating amount for the nickel silicide film 11 can be reduced. In this case, the propagation of heat to the nickel silicide film 11 can be further reduced by using a material having a large heat capacity (for example, a silicon oxide film) for the first interlayer insulating film 12. According to the heating using light energy in the present invention, the temperature rise of the nickel silicide film 11 is caused by the heat absorption through the first interlayer insulating film 12 as well as the light absorption described above. Therefore, in order to suppress the temperature rise of the nickel silicide film 11, it is particularly important to select a material having a large heat capacity for the first interlayer insulating film 12.

  On the other hand, a flash lamp, an infrared laser, or the like can irradiate much light energy instantaneously, so that the temperature rise can be increased only near the surface of the film. According to the present embodiment, since the heat absorption film 15 is formed on the outermost surface, the heat absorption film 15 selectively rises in temperature in combination with the characteristic that it easily absorbs light energy. For this reason, the gate insulating film 14 in contact with the heat absorption film 15 is efficiently heated via the heat absorption film 15.

  As described above, the heat absorption film 15 is formed before the heat treatment, and the substrate is irradiated with at least one of flash light and laser light from the heat absorption film 15 side without causing aggregation of the nickel silicide film 11. The gate insulating film 14 can be efficiently heated. Therefore, dangling bonds and impurities contained in the gate insulating film 14 are removed without increasing the layer resistance of the nickel silicide film 11 and increasing the gate leakage current, thereby improving the film quality of the gate insulating film 14. Can do.

  In the present invention, a silicon film can be used as the heat absorption film 15.

  FIG. 16 shows changes in light absorption characteristics depending on the film thickness of a polycrystalline silicon film. FIG. 16 shows that there is almost no change in the extinction coefficient between the film thickness of 30 nm and the film thickness of 60 nm. However, when the film thickness is 10 nm, the extinction coefficient at a wavelength of 350 nm or less decreases as a whole, and the light transmittance is reduced. You can see it grows.

  FIG. 17 shows changes in light absorption characteristics depending on the film thickness of an amorphous silicon film. FIG. 17 shows that there is almost no change in the extinction coefficient between the film thickness of 30 nm and the film thickness of 60 nm. However, when the film thickness is 10 nm, the extinction coefficient at the wavelength of 800 nm or less decreases as a whole, and the light transmittance is reduced. You can see it grows.

  FIG. 18 is an example of an emission spectrum of a xenon flash lamp used for heat treatment. FIG. 19 compares the absorption characteristics of the polycrystalline silicon film and the amorphous silicon film. In FIG. 19, the thickness of each silicon film is 30 nm. From these figures, it can be seen that the amorphous silicon film absorbs light on the longer wavelength side more than the polycrystalline silicon film, so that the light of the flash lamp can be absorbed more efficiently.

  As described above, both the polycrystalline silicon film and the amorphous silicon film can be used as the heat absorption film 15, but the amorphous silicon film is more preferable from the viewpoint of absorbing light more efficiently. Used. Further, it is desirable that both the polycrystalline silicon film and the amorphous silicon film have a film thickness of 30 nm or more. Note that the silicon film may be formed using either a CVD method or a low-temperature sputtering method.

  After finishing the heat treatment, a nickel film (not shown) is formed on the entire surface, and then the heat treatment is performed to react the nickel film with the underlying silicon film (heat absorption film 15), A nickel silicide film 16 (second metal silicide film) is formed (FIG. 13). Thereby, a gate electrode made of the nickel silicide film 16 can be obtained. Here, the temperature of the heat treatment is preferably about 400 ° C. The heat treatment time is set to a time sufficient for the nickel silicide film 16 to be formed to contact the gate insulating film 14.

  Note that the second metal silicide film is not necessarily the same metal as the first metal silicide film. For example, the second metal silicide film may be formed using other metal films such as a cobalt film, a titanium film, and a molybdenum film instead of the nickel film. In this case, the temperature of the heat treatment for silicidation is preferably set as appropriate according to the type of metal film.

  After the silicidation is completed, after removing the unreacted nickel film, impurities may be ion-implanted into the nickel silicide film 16 as necessary. Thereby, the work function of the nickel silicide film 16 can be changed.

  Next, the nickel silicide film 16 and the gate insulating film 14 are removed by the CMP method or the etch back method except for the inside of the trench 13.

  Next, after the second interlayer insulating film 17 is formed, the contact 18 and the wiring 19 are formed to obtain the structure shown in FIG.

  In the present embodiment, the recessed portion (reference numeral 20 in FIG. 13) of the gate electrode may be embedded with an appropriate metal film. For example, after the step shown in FIG. 13, a titanium nitride film 21 and a tungsten film 22 are formed in order, and these films are removed by the CMP method except for the recessed portion 20. Thereafter, when the contact 18 and the wiring 19 are formed after the second interlayer insulating film 17 is deposited, the structure shown in FIG. 15 is obtained. According to the structure shown in the figure, since the tungsten film 22 reduces the layer resistance of the gate electrode, the delay time of the circuit can be reduced and the operation speed can be improved.

  In the above embodiment, the silicon film is used as the heat absorption film, but the present invention is not limited to this. For example, a metal film such as tantalum (Ta), molybdenum (Mo), tungsten (W), ruthenium (Ru), platinum (Pt) and iridium (Ir) or a nitride of these metals, an oxide of ruthenium and iridium, or A film made of silicon germanium or the like can also be used as the heat absorption film. However, when a gate electrode made of metal silicide is formed after using a film made of a material other than a silicon film as a heat absorption film, the silicon film is formed after removing the heat absorption film, and a metal is formed thereon. It is necessary to form a film and form a silicide.

  As described above, according to the present invention, the first metal silicide is formed by forming the heat absorption film on the gate insulating film and irradiating the silicon substrate with at least one of flash light and laser light from the heat absorption film side. The gate insulating film can be efficiently heated without causing film aggregation. In this case, the interlayer insulating film is a laminated film, and the temperature of the metal silicide film is further increased by appropriately selecting the material and the film thickness of each film so that the reflectance of light in the interlayer insulating film is increased. Can be suppressed. In other words, in the present invention, a great effect is obtained in the order of 1) a combination of a heat absorption film and an interlayer insulation film having a high reflectance, 2) only a heat absorption film, and 3) only an interlayer insulation film having a high reflectance.

  In the above embodiment, an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor) has been described as an example, but the present invention is not limited to this. The present invention may be applied to a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor) or a CMOSFET (Complementary Metal Oxide Semiconductor Effector).

  Furthermore, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

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Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Element isolation insulating film 3 Sacrificial gate insulating film 4 Diffusion layer 5 Silicon film 6 Silicon nitride film 7 Extension region 8 Silicon nitride film 9 Source / drain region 10 Nickel film 11, 16 Nickel silicide film 12 First interlayer insulation Film 13 Groove 14 Gate insulating film 15 Heat absorption film 17 Second interlayer insulating film 18 Contact 19 Wiring 21 Titanium nitride film 22 Tungsten film 23 Flash

Claims (7)

Forming a sacrificial gate electrode on the silicon substrate via a sacrificial gate insulating film;
Forming a sidewall insulating film on the sidewall portion of the sacrificial gate electrode;
Using the sacrificial gate electrode formed with the sidewall insulating film as a mask and implanting impurities into the silicon substrate to form source / drain regions;
Forming a first metal silicide film on the source / drain regions;
Forming an interlayer insulating film on the silicon substrate so as to embed the sacrificial gate electrode;
Processing the interlayer insulating film to expose the surface of the sacrificial gate electrode;
Etching the sacrificial gate electrode to expose the sacrificial gate insulating film;
Etching the sacrificial gate insulating film to form a groove reaching the silicon substrate;
Forming a gate insulating film on the inner surface of the groove and the interlayer insulating film at 550 ° C. or lower ;
Forming a heat absorption film on the gate insulating film;
Performing a heat treatment on the gate insulating film by irradiating the silicon substrate with at least one of flash light and laser light from the heat absorption film side ;
The method of manufacturing a semiconductor device, characterized in that have a, and performs the respective steps as described above in the order described above.   The method of manufacturing a semiconductor device according to claim 1, wherein the heat absorption film is a silicon film. Forming a metal film on the silicon film after the heat treatment;
The method for manufacturing a semiconductor device according to claim 2, further comprising a step of reacting the silicon film and the metal film by heat treatment to form a second metal silicide film on the gate insulating film.   4. The method for manufacturing a semiconductor device according to claim 2, wherein the thickness of the silicon film is 30 nm or more.   The method of manufacturing a semiconductor device according to claim 2, wherein the silicon film is an amorphous silicon film.   The method of manufacturing a semiconductor device according to claim 1, wherein the gate insulating film has a high dielectric constant insulating film.   7. The method of manufacturing a semiconductor device according to claim 6, wherein the high dielectric constant insulating film is an oxide film or a silicate film of at least one metal selected from the group consisting of hafnium, zirconium, lanthanum, and cerium.

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