JP5117076B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device manufacturing method and a semiconductor device, and more particularly, to a semiconductor device having an N-channel MIS (Metal Insulator Semiconductor) transistor and a P-channel MIS transistor and having a biased distribution of P-channel MIS transistors. The present invention relates to a manufacturing method and a semiconductor device having an N-channel MIS transistor and a P-channel MIS transistor.

  Today, electronic devices are always required to be small, highly functional, and high-performance. In order to obtain small, high-performance, and high-performance electronic devices, system-on-chip (SoC) is downsized and high-performance. Progress is also being made. A system-on-chip is a semiconductor device in which functional units such as a logic circuit unit, a storage unit, and an interface circuit unit are mixedly mounted on one semiconductor chip. In order to reduce the size and increase the performance of the system-on-chip, the field effect Improvements in integration density of circuit elements such as transistors and higher performance of circuit elements have been achieved.

  For example, when increasing the integration density of a field effect transistor, the field effect transistor is miniaturized (downsized) in accordance with a scaling law. As a result of the miniaturization, the gate insulating film becomes thinner as a result of which the gate insulating film capacity increases, thereby increasing the on-current and improving the speed performance of the field effect transistor.

  In addition, by making the field effect transistor a surface channel type, the driving performance is improved as compared to the case of the buried channel type. In general, in a surface channel type N channel field effect transistor or a buried channel type P channel field effect transistor, a gate electrode is formed of N type polysilicon (polysilicon doped with an N type impurity), and the surface channel type P channel is formed. In the field effect transistor, the gate electrode is formed of P-type polysilicon (polysilicon doped with P-type impurities).

  However, when the thickness of the gate insulating film is reduced to a certain degree or more, the direct tunnel current passing through the gate insulating film increases and the power consumption increases. That is, the gate leakage current increases and the power consumption increases. For example, in a silicon oxide film (thermal oxide film) often used as a gate insulating film, the gate leakage current increases when the film thickness is reduced to about 2 nm or less. When the thickness of the gate insulating film is reduced, the impurity doped in the gate electrode is easily diffused out to reach the semiconductor substrate. When the impurity reaches the semiconductor substrate, the threshold voltage of the field effect transistor or The drive current fluctuates and its performance and reliability are reduced. In particular, boron frequently used as a P-type impurity tends to cause outward diffusion.

  For example, when boron doped in the gate electrode of a surface channel type P-channel field effect transistor causes outward diffusion to reach the semiconductor substrate, resistance to negative bias temperature instability (NBTI) (NBTI) Hereinafter, it will be abbreviated as “NBTI reliability”).

  In order to increase the gate insulating film capacity and suppress the gate leakage current, the gate insulating film is made of a high dielectric constant dielectric film that can obtain a desired gate insulating film capacity even if it is thicker than the silicon oxide film. It is desirable to form. In order to suppress the outward diffusion of boron, it is desirable to form the gate insulating film with an insulating material containing nitrogen atoms.

  From these viewpoints, a silicon oxynitride film is frequently used as a material for a gate insulating film in a semiconductor device having a fine surface channel type P-channel field effect transistor. Although it is possible to form the gate insulating film only by the silicon oxynitride film, from the viewpoint of suppressing the outward diffusion of boron, the gate is formed by the laminated film in which the silicon oxynitride film is laminated on the silicon oxide film. An insulating film may be formed.

  The silicon oxynitride film that is the source of the gate insulating film can be formed by a chemical vapor deposition method (CVD method), as described in Patent Document 1, for example. In order to form a silicon oxynitride film having a good film quality with few dangling bonds and impurity levels, for example, as described in Patent Documents 2 to 4, a silicon substrate (single crystal silicon substrate or SOI) is used. It is preferable to grow a silicon oxynitride film on the silicon substrate by heat-treating (Silicon on Insulator) substrate or the like) in a predetermined atmosphere.

  Then, as described in Patent Document 5, once a silicon oxynitride film as a base of a gate insulating film is formed and then annealed in a predetermined atmosphere, holes (holes) are formed. The silicon oxynitride film with better film quality can be obtained by removing the OH group (hydroxyl group) contributing to the trap of) and the nitrogen atom with unstable bond state and reducing the number of interface states.

  For the gate insulating film including the silicon oxynitride film, for example, a film that becomes the source of the gate insulating film is formed, and a polysilicon film that is the source of the gate electrode is formed on the gate insulating film. After that, the polysilicon film and the gate insulating film are sequentially patterned by etching in this order. At this time, a gate electrode is obtained from the polysilicon film.

Japanese Unexamined Patent Publication No. 7-135208 JP-A-10-189949 JP 2000-208510 A JP 2003-78132 A JP 2004-247528 A

  However, when forming the MIS transistor, after forming the gate insulating film and the gate electrode as described above, the sidewalls are formed, the impurity diffusion regions (source region and drain region) are formed, and the interlayer insulating film is formed. Is done. The film quality of the gate insulating film is deteriorated in the process of forming these sidewalls, impurity diffusion regions, or interlayer insulating films. As a result, in a semiconductor device having a surface channel type P-channel field effect transistor, the outward diffusion of boron doped in the gate electrode of the P-channel field effect transistor is suppressed by the gate insulating film for a long period of time. And the reliability of the NTBI decreases.

  In order to obtain a semiconductor device having a surface channel type fine P-channel field effect transistor and high NTBI reliability, after forming an interlayer insulating film on the semiconductor substrate, silicon oxynitride contained in the gate insulating film It is desirable to anneal the material film. Since the annealing temperature at this time is relatively high, it is necessary to prevent disconnection of the wiring due to exposure to a high temperature, for example, disconnection of the wiring in the logic circuit section.

  The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that includes a fine P-channel MIS transistor of a surface channel type and that can easily manufacture a semiconductor device having high NBTI reliability as the entire device. For the purpose.

  Another object of the present invention is to obtain a semiconductor device that includes a fine P-channel MIS transistor of a surface channel type and that can easily obtain an NBTI-reliable device as a whole.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, a storage unit region that finally becomes a static random access memory (SRAM) and a logic circuit unit region that finally becomes a logic circuit unit are formed on one side. The silicon oxide contained in the gate insulating film of the MIS transistor formed in the memory region is selectively annealed by selectively performing laser annealing on the memory region in the semiconductor substrate. The nitride film is modified. Prior to the selective annealing, an electrical insulating film is formed in advance on the semiconductor substrate so as to cover each of the P channel MIS transistors in the logic circuit region and each of the P channel MIS transistors in the memory region.

  In one embodiment of the semiconductor device of the present invention, the memory area and the logic circuit area are formed on one side of the semiconductor substrate, and each of the P channel MIS transistors in the logic circuit area and An interlayer insulating film is formed to cover each of the P-channel MIS transistors in the memory region, and the atomic ratio of silicon atoms in the metal silicide in the memory region and the metal silicide in the logic circuit region. The number ratio of silicon atoms is different from each other.

  Here, each of the P-channel MIS transistors formed in the memory region includes a gate insulating film including a silicon oxynitride film, a gate electrode formed into a metal silicide over a predetermined depth from the upper surface, have. Each of the P channel MIS transistors formed in the logic circuit region has a gate electrode that is metal silicided from the upper surface to a predetermined depth. The above-mentioned “atom ratio of silicon atoms” means the atomic ratio of silicon atoms in the metal silicide formed on the gate electrode of the P-channel MIS transistor. In the memory area and the logic circuit area, the disilicide contents in the metal silicide are different from each other.

  In one embodiment of the method for manufacturing a semiconductor device of the present invention, the silicon oxynitride film included in the gate insulating film of the P-channel MIS transistor formed in the memory region is used as the source of the interlayer insulating film. Since it is modified by selective annealing after the formation of the electrical insulating film, the gate insulating film (silicone) is formed in a later process after the modification as compared with the case where the silicon oxynitride film is modified before the electrical insulating film is formed. It is suppressed that the oxynitride film) is damaged. In addition, since selective annealing is performed on the memory area, the temperature increase of the logic circuit area that is not the target of the selective annealing is suppressed, and as a result, the logic circuit area is exposed to a high temperature. The disconnection of the wiring resulting from this can be easily prevented.

  The gate insulating film formed in the logic circuit area is not annealed, but the number of P-channel MIS transistors is much larger in the memory area than in the logic circuit area. NBTI reliability can be improved by considering the overall obtained semiconductor device. Therefore, according to the above embodiment, it becomes easy to manufacture a semiconductor device having a surface channel type fine P-channel MIS transistor and having high NBTI reliability as the entire device.

  When the semiconductor device in which the gate electrode of the P-channel MIS transistor formed in each of the memory region and the logic circuit region is partially metal-silicided is manufactured as described above, the P having undergone selective annealing is manufactured. The metal silicide composition differs between the gate electrode of the channel MIS transistor and the gate electrode of the P-channel MIS transistor that has not undergone selective annealing. More specifically, the content of disilicide in the metal silicide is different between the memory area and the logic circuit area. As a result, the aspect ratio of silicon atoms in the metal silicide in the memory region and the atomic ratio of silicon atoms in the metal silicide in the logic circuit region are different from each other. The semiconductor device can be obtained.

  DESCRIPTION OF EMBODIMENTS Hereinafter, a method for manufacturing a semiconductor device and embodiments of the semiconductor device according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the embodiments described below.

(Embodiment 1)
The method for manufacturing a semiconductor device of the present invention performs selective annealing, and in this selective annealing, laser annealing is selectively performed on a predetermined portion of a semiconductor substrate on which a P-channel MIS transistor is formed. The semiconductor substrate is, for example, a silicon wafer or an SOI substrate on which a plurality of system-on-chip intermediate products are formed. For each intermediate product, a first functional region having a relatively high integration density of a P-channel MIS transistor whose gate insulating film contains silicon oxynitride, for example, for a storage unit that finally becomes a storage unit such as an SRAM. A region and a second functional region in which the integration density of the P-channel MIS transistors is relatively low, for example, a region for a logic circuit portion that finally becomes a logic circuit portion are formed. In addition, an electrical insulating film for an interlayer insulating film is formed to cover each of the P channel MIS transistors.

  FIG. 1 is a plan view schematically showing an example of a semiconductor substrate on which selective annealing is performed. The semiconductor substrate 10 shown at the same time is obtained by forming a plurality of system-on-chip intermediate products 100A on a silicon wafer 1, and each of the intermediate products 100A has three functional regions, that is, two formed separately from each other. The memory section regions MR, MR and one logic circuit section LR located between the two memory section regions MR, MR are provided. Each intermediate product 100A is arranged with the orientation of the storage area MR aligned.

  In each of the memory region MR, for example, a P-channel MIS transistor and an N-channel MIS transistor (both not shown in FIG. 1) constituting a complementary MIS (Complementary MIS) transistor. Are formed in a predetermined number. Each of the logic circuit portions LR is formed with, for example, a P-channel MIS transistor, an N-channel MIS transistor, and a wiring that forms a predetermined circuit (none of which is shown in FIG. 1). Yes. The above-mentioned electrical insulating film for interlayer insulating film (not shown in FIG. 1) covers each MIS transistor and other circuit elements formed on each intermediate product 100A on the silicon wafer 1. Is formed.

  At least the gate insulating film of each MIS transistor formed in the memory region MR includes a silicon oxynitride film. The gate insulating film may consist of only one silicon nitride film, or may have a two-layer structure in which a silicon oxynitride film is stacked on a silicon oxide film, or a silicon oxide film. It may have a three-layer structure in which a silicon oxynitride film and a silicon oxide film are stacked in this order on a physical film. The integration density of the P-channel MIS transistors having such a gate insulating film is higher in the memory region MR than in the logic circuit region LR. Each memory area MR corresponds to a “first function area” in the present invention, and each logic circuit area LR corresponds to a “second function area” in the present invention.

  FIG. 2 is a cross-sectional view schematically showing the intermediate product 100A. As shown in the figure, an N-type active region (N-type well) 3 and a P-type active region (P-type well) 5 are formed in a predetermined pattern on a silicon wafer 1 constituting a semiconductor substrate 10. At the same time, an element isolation region 7 is formed so as to partition the active regions 3 and 5 in plan view.

  A surface channel type P-channel MIS transistor 20P and a surface channel type N-channel MIS transistor 30N that form a complementary MIS transistor are formed in the memory region MR in the intermediate product 100A. These MIS transistors 20P and 30N both have an LDD (Lightly Doped Drain) structure.

  The P-channel MIS transistor 20P is a gate made of P-type polysilicon (including a nickel silicide layer S described later) disposed on the semiconductor substrate 10 via a gate insulating film 11 made of a silicon oxynitride film. The electrode 13 includes offset spacer films OS and OS formed on both side surfaces of the gate electrode 13 in the line width direction, and sidewall spacers SW and SW disposed on the offset spacer films OS. It also has a source region 15, a drain region 17 and two extension regions 19, 19 formed by doping the N-type active region 3 with a P-type impurity. In each of the gate electrode 13, the source region 15, and the drain region 17, a nickel silicide layer S is formed from the upper surface to a predetermined depth.

  Similarly, the N-channel MIS transistor 30 is made of N-type polysilicon (including a nickel silicide layer S described later) disposed on the semiconductor substrate 10 via a gate insulating film 21 made of a silicon oxynitride film. ), The offset spacer films OS and OS formed on both side surfaces of the gate electrode 23 in the line width direction, and the side wall spacers SW and SW disposed on each offset spacer film OS. ing. The P-type active region 5 also has a source region 25, a drain region 27, and two extension regions 29, 29 formed by doping an N-type impurity. In each of the gate electrode 23, the source region 25, and the drain region 27, a nickel silicide layer S is formed from the upper surface to a predetermined depth.

  On the other hand, in the logic circuit region LR, as described above, the P-channel MIS transistor, the N-channel MIS transistor, and the wiring for forming a predetermined circuit are formed. Only the channel-type N-channel MIS transistor 32N appears. The N channel MIS transistor 32N constitutes one complementary MIS transistor together with, for example, a buried channel P channel MIS transistor not shown in FIG. The structure of N channel MIS transistor 32N is the same as that of N channel MIS transistor 30N described above.

  A liner stress film 35 made of, for example, silicon nitride is formed on the semiconductor substrate 10 so as to cover each MIS transistor 20P, 30N, 32N and other circuit elements formed on the semiconductor substrate 10. Then, an electrical insulating film 40A for an interlayer insulating film is formed so as to cover the liner stress film 35. The electrical insulating film 40A is made of, for example, silicon oxide.

  In the selective annealing in the method for manufacturing a semiconductor device of the present invention, laser annealing is selectively performed on each memory region MR that is the first functional region. In this selective annealing, the memory region MR is irradiated with the laser beam LB as shown in FIG. 2, and the gate insulating films 11 and 21 formed in the memory region MR are heated to a predetermined temperature. The When the laser beam is scanned in a predetermined direction on the semiconductor substrate 10 shown in FIG. 1, the selective annealing can be easily performed.

  At this time, in consideration of the reflection of the laser beam LB on the surface of the electrical insulating film 40A (see FIG. 1), the reflection of the laser beam LB at the interface between the layers, and the absorption of the laser beam LB in each layer, It is preferable to select the laser beam power and the irradiation time so that the gate insulating films 11 and 21 are heated to about 800 to 1100 ° C. For example, if the power of the laser beam LB is 1400 W and the irradiation time at each irradiation spot is about 1 second, the gate insulating films 11 and 21 can be heated to about 1000 ° C. relatively easily. It is also possible to provide a reflective film on the electrical insulating film 40A and adjust the heating temperature of the gate insulating films 11 and 21 while keeping the power of the laser beam LB at a constant value.

  The atmosphere for performing the selective annealing can be an inert atmosphere, for example, a mixed atmosphere of hydrogen gas and nitrogen gas, and the selective annealing can be performed under reduced pressure or under normal pressure. . If necessary, selective annealing in an inert atmosphere and selective annealing in an oxidizing atmosphere may be combined.

  By performing the selective annealing in this way, the dangling bonds in the silicon oxynitride film formed in the memory region MR are terminated, in other words, in each of the gate insulating films 11 and 21. The dangling bonds can be terminated to improve the film quality. Further, the interface morphologies of the silicon oxynitride films (gate insulating films 11, 21) formed in the memory region MR are improved, and the interface existing between the gate insulating film 11 and the gate electrode 13 is improved. The number of levels and the number of interface states existing between the gate insulating film 21 and the gate electrode 23 can be reduced. Further, the number of impurity levels in each of the gate insulating films 11 and 21 can be reduced.

  As a result, even when the gate electrode 13 of the P-channel MIS transistor 20P is doped with boron as a P-type impurity, the outward diffusion of the boron into the active region 3 is suppressed by the gate insulating film 11 over a long period of time. The NBTI reliability can be improved. In addition, the performance of the P-channel MIS transistor 20P can be improved. Since the selective annealing is performed on the memory area MR, the temperature rise of the logic circuit area LR that is not the target of the selective annealing is suppressed, and as a result, the logic circuit area LR is heated to a high temperature. The disconnection of the wiring due to the exposure can be easily prevented.

  The surface channel type P-channel MIS transistors formed in the logic circuit region RL cannot be improved in NBTI reliability because annealing is not performed. However, the number of surface channel type P-channel MIS transistors is not There are overwhelmingly more in the use area MR than in the logic circuit area LR. In addition, the MIS transistor in the logic circuit area LR can be made relatively large.

  Therefore, when considering the entire semiconductor device finally obtained from the intermediate product 100A (see FIG. 1), the electrical insulating film 40A (see FIG. 1) is formed as compared with the case where the above-described selective annealing is not performed. Compared to the case where the gate insulating films 11 and 21 are modified before, it is easy to obtain a film having high NBTI reliability.

When selective annealing is performed as described above, the composition of nickel silicide changes in the MIS transistors 20P and 30N (see FIG. 1) formed in the memory region MR. That is, the nickel silicide layer S formed on the gate electrodes 13 and 23, the nickel silicide layer S formed on the source regions 15 and 25, and the nickel silicide layer S formed on the drain regions 17 and 27 (FIG. 1). In each of the reference), the content of nickel monosilicide (NiSi) decreases while the content of nickel disilicide (NiSi ₂ ) increases.

  As a result, the atomic ratio of silicon atoms in the nickel silicide formed on the gate electrode of each MIS transistor formed in the memory region MR and the logic circuit region LR not subjected to annealing (see FIG. 1), the atomic ratio of silicon atoms in the nickel silicide formed on the gate electrode of each MIS transistor is different from each other. Even when another metal silicide such as cobalt silicide is formed in place of nickel silicide, the composition change is caused by laser annealing as described above. The composition of the metal silicide can be analyzed using, for example, a TEM-EELS (Transmission Electron Microscope—Electron Energy Loss Spectroscopy) method.

  A target semiconductor device (system-on-chip) is obtained by constructing a desired integrated circuit on the semiconductor substrate 10 after performing the selective annealing described above, and then cutting out by dicing.

  In constructing the integrated circuit, first, a contact hole reaching the upper surface of the silicon wafer 1 (the upper surfaces of the active regions 3 and 5) is formed at a predetermined position of the electrical insulating film 40A (see FIG. 2). The electric insulating film 40A is formed into a first interlayer insulating film. Next, after the contact hole is filled with a conductive material such as tungsten to form a contact plug, a second interlayer insulating film is formed on the first interlayer insulating film, and a via is formed at a predetermined portion of the second interlayer insulating film. Contacts and wiring are formed. Thereafter, a desired number of interlayer insulating films in which via contacts and wirings are formed at predetermined positions are laminated on the second interlayer insulating film to obtain the integrated circuit.

  FIG. 3A is a cross-sectional view schematically showing an example of each of the first interlayer insulating film and the contact plugs provided in the first interlayer insulating film. Among the constituent elements shown in the figure, those common to the constituent elements shown in FIG. 2 are denoted by the same reference numerals as those used in FIG. 2 and description thereof is omitted.

The first interlayer insulating film 40 shown in FIG. 3A is obtained by providing a contact hole at a predetermined location of the electric insulating film 40A shown in FIG. FIG. 3A shows six contact holes CH _{1 to} CH ₆ and a total of six contact plugs 43 a to 43 f provided for each contact hole CH _{1 to} CH ₆ .

The contact holes CH _{1 to} CH ₆ are formed by, for example, providing an etching mask having a predetermined shape on the electrical insulating film 40A shown in FIG. 2 and etching the electrical insulating film 40A. Further, the contact plugs 43a~43f, for example, after forming a blanket layer by depositing a conductive material such as tungsten over the contact holes CH ₁ to CH ₆ in and the first interlayer insulating film 40, the blanket The blanket film is formed by chemical mechanical polishing until a region of the film located on the upper surface of the first interlayer insulating film 40 is removed.

  FIG. 3-2 is a cross-sectional view schematically showing an example of a semiconductor device manufactured by the method for manufacturing a semiconductor device of the present invention, and is also a cross-sectional view schematically showing an example of the semiconductor device of the present invention. Among the constituent elements shown in the figure, those common to the constituent elements shown in FIG. 3A are denoted by the same reference numerals as those used in FIG. 3A and their description is omitted.

  In the semiconductor device 100 shown in FIG. 3B, a second interlayer insulating film 50 is formed on the first interlayer insulating film 40 shown in FIG. 3A, and via contacts are formed at predetermined positions of the second interlayer insulating film 50. Wiring is formed. Further, a desired number of interlayer insulating films in which via contacts and wirings are formed at predetermined positions are laminated on the second interlayer insulating film. In FIG. 3B, the second interlayer insulating film 50 and the third interlayer insulating film 60 appear.

  In the second interlayer insulating film 50, a predetermined number of dual damascene wirings are formed including six dual damascene wirings 53a to 53f whose side surfaces and bottom surfaces are covered with barrier metal layers 51a, 51b, 51c, 51d, 51e or 51f. Has been. The third interlayer insulating film 60 is formed with a predetermined number of dual damascene wirings including three dual damascene wirings 63a, 63b, 63c whose side surfaces and bottom surfaces are covered with barrier metal layers 61a, 61b or 61c. Yes. Each dual damascene wiring is an integrally formed product of a via contact and a wiring connected to the via contact, and is formed of, for example, copper.

  The barrier metal layer and the dual damascene wiring are formed by, for example, forming an inorganic film, depositing a damascene wiring material, and chemical mechanical polishing in this order. In addition to the via hole, a trench in which a wiring portion in the dual damascene wiring is formed is formed in the interlayer insulating film in which the dual damascene wiring is to be formed. An inorganic film serving as a base of the barrier metal layer is formed in each via hole, each trench, and on the upper surface of the interlayer insulating film formed in the interlayer insulating film by a CVD method or the like, and then each via hole and each trench is formed. A damascene wiring material such as copper is deposited on the above inorganic film by plating so as to be buried. Thereafter, the surplus damascene wiring material and the region formed on the upper surface of the interlayer insulating film (excluding the bottom of the trench) in the inorganic film that is the source of the barrier metal layer are formed by chemical mechanical polishing. Removed. As a result, the above-described barrier metal layer and dual damascene wiring are obtained.

  In the semiconductor device 100, as described above, an integrated circuit is constructed by laminating a desired number of interlayer insulating films having via contacts and wirings formed at predetermined positions on the second interlayer insulating film 50. Each MIS transistor formed in the memory area MR (see FIG. 2) constitutes an SRAM section, and each MIS transistor formed in the logic circuit area LR (see FIG. 2) is a logic circuit. Part. Therefore, the semiconductor device 100 has two SRAM units and one logic circuit unit.

(Embodiment 2)
In the method for manufacturing a semiconductor device of the present invention, the structure of each MIS transistor in the first functional region that is the target of selective annealing can be made to have no metal silicide. For example, when nickel silicide is subjected to a high-temperature annealing treatment, the nickel silicide is agglomerated to form a portion having a high electrical resistance, which may deteriorate the performance of the MIS transistor. If each MIS transistor formed in the first functional region does not have metal silicide, the occurrence of the high electrical resistance is prevented, and as a result, the performance of the MIS transistor is prevented from being deteriorated.

(Embodiment 3)
In the method for manufacturing a semiconductor device of the present invention, the dose amount of the P-type impurity at the gate electrode in each of the P-channel MIS transistors in the first functional region to be selectively annealed is determined by the integration density of the P-channel MIS transistors. The dose amount of the P-type impurity at the gate electrode in the P channel MIS transistor in the relatively low second function region can be reduced. For example, the dose amount of the P-type impurity at the gate electrode in each of the P-channel MIS transistors formed in the first functional region is set as the P-type impurity at the gate electrode in the P-channel MIS transistor formed in the second functional region. The dose can be halved.

  When the dose amount of the P-type impurity at the gate electrode in each P-channel MIS transistor is adjusted in this way, the effective voltage applied to the semiconductor substrate is lowered in the P-channel MIS transistor formed in the first functional region. Out diffusion of P-type impurities doped in the gate electrode is suppressed. In combination with the selective annealing described above, the NBTI reliability of the P-channel MIS transistor formed in the first functional region is improved.

  As described above, the semiconductor device manufacturing method and the semiconductor device of the present invention have been described with reference to the embodiments. However, as described above, the present invention is not limited to the above-described embodiments. For example, how many functional regions are to be formed on a semiconductor substrate is appropriately selected according to functions and performance required for the semiconductor device to be manufactured or according to the use of the semiconductor device to be manufactured. Is possible. In addition to the dual damascene wiring, the wiring in the integrated circuit constructed on the semiconductor substrate may be a single damascene wiring. The semiconductor device manufacturing method of the present invention can be variously modified, modified, combined, etc. in addition to those described above.

  Further, the semiconductor substrate on which selective annealing is performed, that is, the semiconductor substrate formed up to the electrical insulating film 40A (see FIG. 2) that is the base of the interlayer insulating film may be manufactured by itself or manufactured by others. May be purchased.

  When the semiconductor substrate 10 formed up to the electrical insulating film 40A shown in FIG. 2 is manufactured by itself, first, as shown in FIG. 4A, the active regions 3 and 5 and the element isolation region 7 are formed at predetermined positions. The silicon oxynitride film ON which is the source of the gate insulating films 11 and 21 (see FIG. 2) and the polysilicon film PL which is the source of the gate electrodes 13 and 23 (impurities doped) ) And form. For example, after the silicon oxynitride film ON is subjected to heat treatment in an oxidizing atmosphere on the silicon wafer 1 to grow a thermal oxide film (silicon oxide film) on the surface, the thermal oxide film is subjected to plasma nitriding treatment or the like It is formed by nitriding by this method. Further, the polysilicon film PL is activated by, for example, forming an undoped polysilicon film by a PVD method or a CVD method and adding a P-type or N-type impurity to a predetermined portion of the polysilicon film and activating the polysilicon film PL. It is formed.

  Next, the silicon oxynitride film ON and the polysilicon film PL are respectively patterned, and as shown in FIG. 4B, polysilicon serving as a source of the gate insulating film 11 and the gate electrode 13 (see FIG. 2). An electrode 13A is obtained. Although not shown in FIG. 4B, other gate electrodes and polysilicon electrodes are also formed together with the gate insulating film 11 or the polysilicon electrode 13A.

  Further, after providing an ion implantation mask having a predetermined shape on the silicon wafer 1 after the polysilicon electrode 13A is formed, a P-type impurity is implanted into the silicon wafer 1 and activated, as shown in FIG. In this manner, impurity diffusion regions 19A and 19A that are the basis of each extension region 19 (see FIG. 2) are obtained. Further, after providing an ion implantation mask having a predetermined shape on the silicon wafer 1, N-type impurities are implanted into the silicon wafer 1 and activated, as shown in FIG. Impurity diffusion regions 29A and 29A that are the basis of (see FIG. 2) are obtained. However, only one impurity diffusion region 29A appears in FIG.

  The patterning of the silicon oxide film ON and the polysilicon film PL (see FIG. 4A) is performed, for example, after an etching mask having a predetermined shape is provided on the polysilicon film PL, the polysilicon film PL and the silicon oxide film ON is performed in this order, and the etching mask is removed after the patterning of the silicon oxide film ON.

  Next, each of the gate insulating films and each of the polysilicon electrodes is covered, and the inorganic insulating film serving as the base of the offset spacer film OS (see FIG. 2) and the base of the sidewall spacer SW (see FIG. 2). After the inorganic insulating films are formed in this order by, for example, the CVD method and stacked on the semiconductor substrate 10, these films are etched back. As a result, as shown in FIG. 4C, each offset spacer film OS and each sidewall spacer SW are obtained.

  Further, after providing an ion implantation mask of a predetermined shape on the silicon wafer 1, a P-type impurity is implanted into the silicon wafer 1 and activated, as shown in FIG. 4-3, the source region 15 (see FIG. 2). ) And the impurity diffusion region 17A which becomes the source of the drain region 17 (see FIG. 2). Further, after providing an ion implantation mask having a predetermined shape on the silicon wafer 1, an N-type impurity is implanted into the silicon wafer 1 and activated, thereby causing an impurity diffusion region to be a source of the source region 25 (see FIG. 2), Then, an impurity diffusion region that is a source of the drain region 27 (see FIG. 2) is obtained. In FIG. 4C, only the impurity diffusion region 27 </ b> A serving as the source of the drain region 27 appears among the impurity diffusion regions serving as the source of the source region 25 and the drain region 27.

  With the formation of the impurity diffusion regions 15A and 17A, the end portions on the polysilicon electrode 13A side in the impurity diffusion regions 19A and 19A shown in FIG. 4-2 remain as extension regions 19 (see FIG. 4-3). Similarly, the extension regions 29 and 29 shown in FIG. 2 are formed in accordance with the formation of the impurity diffusion regions that are the sources of the source region 25 and the drain region 27, respectively.

  Next, a nickel film serving as a raw material of the nickel silicide layer S (see FIG. 2) is formed so as to cover each polysilicon electrode, each offset spacer film, each side wall spacer, and the surface of the semiconductor substrate, respectively. The nickel film and each polysilicon electrode are reacted by heat treatment at a temperature of the temperature, and the nickel film is reacted with the impurity diffusion region that is the source of the source region and the drain region. The remaining nickel film that did not contribute to the reaction is removed by etching.

  As shown in FIG. 4-4, the polysilicon electrode 13 </ b> A is nickel-silicided from the upper surface side to a predetermined depth by the above reaction to form a nickel silicide layer S, which becomes the gate electrode 13. Further, the impurity diffusion region 15A (see FIG. 4-3) serving as the source of the source region and the impurity diffusion region 17A (refer to FIG. 4-3) serving as the source of the drain region are respectively nickel from the upper surface side to a predetermined depth. A source region 15 having a nickel silicide layer S and a drain region 17 having a nickel silicide layer S are obtained. Although not shown in FIG. 4-4, other polysilicon electrodes and impurity diffusion regions are similarly nickel-silicided to become predetermined gate electrodes, source regions, or drain regions.

  Next, as shown in FIGS. 4-5, the liner stress film | membrane 35 is formed into a film by CVD method, for example. Then, an electrically insulating material such as silicon oxide is isotropically deposited on the liner stress film 35, densified by heat treatment, and then planarized by chemical mechanical polishing, as shown in FIG. An electrical insulating film 40A serving as an insulating film is obtained. By forming the electrical insulating film 40A in this way, a system-on-chip intermediate product 100A (see FIG. 1) is formed on the silicon wafer 1, and the semiconductor substrate 10 (see FIG. 1) on which selective annealing is performed. Is obtained.

It is a top view which shows roughly an example of the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the intermediate product of the system on chip | tip currently formed in the semiconductor substrate shown in FIG. 1 is a cross-sectional view schematically showing an example of a first interlayer insulating film formed in the process of manufacturing a semiconductor device based on a method for manufacturing a semiconductor device of the present invention and a contact plug provided in the first interlayer insulating film. is there. 1 is a cross-sectional view schematically showing an example of a semiconductor device manufactured based on the method for manufacturing a semiconductor device of the present invention, and is also a cross-sectional view schematically showing an example of the semiconductor device of the present invention. It is sectional drawing which shows roughly 1 process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the other process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the other process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the other process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the other process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention. It is sectional drawing which shows schematically the other process at the time of producing the semiconductor substrate in which selective annealing is performed with the manufacturing method of the semiconductor device of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon wafer 10 Semiconductor substrate 11, 21 Gate insulating film (silicon oxide film)
13, 23 Gate electrode 15, 25 Source region 17, 27 Drain region 20P Surface channel type P channel MIS transistor 30N Surface channel type N channel MIS transistor 32N Embedded channel type N channel MIS transistor 40A Source of interlayer insulating film Electrical insulating film 40 Interlayer insulating film (first interlayer insulating film)
50 Second interlayer insulating film 60 Third interlayer insulating film 100A System-on-chip intermediate product 100 Semiconductor device (system-on-chip)
S Nickel silicide layer MR Memory area (first functional area)
LR logic circuit (second functional area)
LB laser light

Claims (8)

A first functional region having a relatively high integration density of a P-channel MIS transistor in which a silicon oxynitride film is included in the gate insulating film, and a second functional region having a relatively low integration density of the P-channel MIS transistor. Laser annealing is selectively performed for the first functional region on a semiconductor substrate formed on one side and on which an electrical insulating film for an interlayer insulating film covering each of the P-channel MIS transistors is formed. A method of manufacturing a semiconductor device, comprising: performing selective annealing for modifying each of the gate insulating films formed in the first functional region.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the P channel MIS transistor is a surface channel type P channel MIS transistor.   3. The semiconductor according to claim 1, wherein the selective annealing is to heat the gate insulating film formed in the first functional region to a temperature in a range of 800 to 1100 ° C. 4. Device manufacturing method.   The method for manufacturing a semiconductor device according to claim 1, wherein the selective annealing is performed in an inert atmosphere.   5. The method of manufacturing a semiconductor device according to claim 4, wherein the inert atmosphere is a mixed gas atmosphere of hydrogen gas and nitrogen gas.   6. The method of manufacturing a semiconductor device according to claim 4, wherein an atmospheric pressure of the inert atmosphere is a normal pressure.   7. The method of manufacturing a semiconductor device according to claim 1, wherein each of the P-channel MIS transistors has a gate electrode that is metal-silicided from a top surface to a predetermined depth. .   The P-channel MIS transistor formed in the first functional region has a smaller impurity dose to the gate electrode than the P-channel MIS transistor formed in the second functional region. Item 8. A method for manufacturing a semiconductor device according to any one of Items 1 to 7.

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