JP2006073728A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the generation of a trap in a gate insulating film upon forming a shallow bonding diffusion layer by activation through irradiation of short wavelength light. <P>SOLUTION: In the manufacture of a semiconductor device, a gate electrode is formed at first on a substrate through the gate insulating film. Impurity is poured to form the diffusion layer employing at least the gate electrode as a mask. On the other hand, fluorine ion is poured before or after pouring the impurity for forming the diffusion layer employing at least the gate electrode as the mask. Further, light having wavelength of about ≤1,000 nm is irradiated for a period of time within about 1 ms. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a semiconductor device. More specifically, the present invention relates to a method for forming a semiconductor device having at least a transistor.

  In recent years, with the miniaturization and high integration of semiconductor devices, the gate length of transistors has also been reduced. Further, in a transistor having a short gate length, the threshold voltage roll-off phenomenon is remarkable. For this reason, as a countermeasure against the roll-off phenomenon, a shallow junction of the diffusion layer composed of the source / drain and the extension is being promoted. For example, in a transistor having a gate length of about 50 nm, the junction depth of the source / drain and the extension needs to be set within about 20 nm.

  As a technique for realizing such an ultra-shallow junction, light having a wavelength of 1000 nm or less is extremely short as a heat treatment for activation after source / drain and extension implantation instead of conventional RTA (Rapid-Thermal-Anneal). Time and irradiation methods are being studied. As described above, by performing the heat treatment for a short time at a high temperature, it is possible to activate the impurity while suppressing the diffusion of the impurity implanted into the Si substrate, and to realize the shallow junction of the diffusion layer. (For example, refer to Patent Document 1).

JP 2004-63574 A

Incidentally, for example, a flash lamp is used in the heat treatment at a high temperature for a short time as described above, and the light source of the flash lamp usually includes light having a short wavelength of 500 nm or less. When the light having such a short wavelength is irradiated for activating the diffusion layer, the gate insulating film may be damaged by the light. Specifically, for example, the silicon oxide film (SiO ₂ ) that forms the gate oxide film contains hydrogen (H), and a large number of Si—H bonds exist. It is about 3eV. Therefore, it is conceivable that the Si—H bond is broken when light corresponding to this wavelength of about 420 nm or less is received. When the Si-H bond is broken, an electron trap or a hole trap is easily formed in the gate insulating film. When the trap is formed, electrons or holes flowing in the channel region are scattered with the charge trapped in the trap, which causes a problem that mobility in the transistor is lowered.

  Therefore, the present invention solves the above problems and manufactures an improved semiconductor device that can form a shallow junction diffusion layer by irradiation with short wavelength light while suppressing the occurrence of traps in the gate insulating film. A method is provided.

  The present invention includes a gate electrode forming step of forming a gate electrode on a substrate via a gate insulating film, a fluorine ion implantation step of implanting fluorine ions using at least the gate electrode as a mask, and at least the gate electrode as a mask A diffusion layer forming step of implanting impurities to form a diffusion layer, and a first heat treatment step of irradiating light having a wavelength of about 1000 nm or less for a time of about 1 second or less.

In this invention, the fluorine ion implantation step may be performed after the impurity implantation step.
In the present invention, the fluorine ion implantation step may implant about 1 × 10 ¹⁵ / cm ² or more of fluorine ions.

In addition, the present invention may include a second heat treatment step of applying a heat treatment within about 1 second at a temperature of about 1000 ° C. or less after the first heat treatment step.
In addition, the present invention may include a third heat treatment step of applying a heat treatment within about 2 minutes at a temperature of about 600 ° C. or less before the first heat treatment step.

  Moreover, this invention may be provided with the amorphization process which amorphizes the area | region which forms the said diffusion layer before the said diffusion layer formation process.

  Further, in the present invention, the diffusion layer forming step includes an extension forming step of forming an extension by implanting impurities using at least the gate electrode as a mask, and forming a sidewall on the side surface of the gate electrode, A source / drain forming step of implanting impurities and forming a source / drain using the gate electrode and the sidewall as a mask may be provided.

  In the present invention, fluorine (F) ions are implanted before or after the impurity implantation for forming the diffusion layer. Therefore, in the heat treatment for activating the diffusion layer, even when Si-H in the gate insulating film is cut by irradiation with light having a short wavelength, Si and F in which the bond is cut can be bonded. As a result, a Si—F bond with strong bonding force can be formed in the gate insulating film, and a shallow junction diffusion layer by irradiation with short wavelength light can be formed while suppressing the generation of traps in the gate insulating film. Can be formed.

Embodiments of the present invention will be described below with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof is simplified or omitted.
In addition, in the following embodiments, when referring to the number of each element, quantity, quantity, range, etc., the reference is made unless otherwise specified or the number is clearly specified in principle. The number is not limited. Further, the structures described in the embodiments, steps in the method, and the like are not necessarily essential to the present invention unless otherwise specified or clearly specified in principle.
Further, in the embodiment, when the term “substrate” is simply used, it means a device including elements and the like formed on the Si substrate 2 in that state.

Embodiment 1 FIG.
1 is a schematic sectional view for illustrating a semiconductor device according to a first embodiment of the present invention.
In the cross section shown in FIG. 1, pWELL 6 is formed in a region separated by element isolation 4 on Si substrate 2. A gate insulating film 8 is formed on the Si substrate 2 on which the pWELL 6 is formed, and a gate electrode 10 is formed on the gate insulating film 8. The gate length of the gate electrode 10 is about 50 nm. A silicon oxide film 12 is formed on the side surface of the gate electrode 10, and spacers 14 are formed on both sides of the silicon oxide film 12. A sidewall 16 is formed outside the spacer 14.

  A halo layer 18 is formed at least near the outer periphery of the surface of the Si substrate 2 where the gate electrode 10 is formed, and an extension 20 is formed in a portion shallower than the halo layer 18. The halo layer 18 is for preventing punch-through from the extension 20. The extension 20 is a diffusion layer having a low impurity concentration and a shallow junction. The extension junction depth is about 20 nm.

A source / drain 22 is formed on the surface of the Si substrate 2 at least near the outer periphery of the region where the gate electrode 10 and the sidewall 16 are formed. The source / drain 22 is a diffusion layer having a higher impurity concentration and a deep junction depth than the extension 20. The junction depth of the source / drain 22 is about 70 nm.
Further, the surface of the gate electrode 10 and the surface of the source / drain 22 are silicided to form NiSi layers 24 and 26, respectively.

  As described above, the silicon nitride film 32 and the silicon oxide film 34 are sequentially stacked on the Si substrate 2 by embedding the gate electrode 10 and the sidewalls 16 formed on the Si substrate 2. A contact plug 36 is formed through the silicon nitride film 32 and the silicon oxide film 34 and connected to the NiSi layer 26 of the source / drain 22. An insulating film 38 is formed on the silicon oxide film 34, and a Cu wiring 40 is formed at a position connected to the contact plug 36.

  The structure described above is similar to a conventional semiconductor device. However, in the semiconductor device according to the first embodiment, as will be described later, fluorine (F) is implanted into the Si substrate 2 before or after impurity implantation for forming the extension 20 and the source / drain 22. Thus, a large number of Si-F bonds are formed in the gate insulating film 8. Therefore, the possibility that an electron trap or a hole trap is generated in the channel region is small, and the semiconductor device has good device characteristics.

FIG. 2 is a flowchart for illustrating the method for manufacturing the semiconductor device according to the first embodiment of the present invention. 3 to 13 are schematic cross-sectional views for explaining states in each manufacturing process of the semiconductor device.
A method for manufacturing a semiconductor device according to the first embodiment of the present invention will be specifically described below with reference to the drawings.

  First, referring to FIG. 3, after element isolation 4 is formed on Si substrate 2 (step S2), B ions are implanted to form pWELL 6 (step S4). Thereafter, the gate insulating film 8 is formed (step S6). As the gate insulating film 8, it is conceivable to use a silicon oxide film or a laminated film of a silicon oxynitride film and a high dielectric constant film. Next, a polysilicon film is formed on the gate insulating film (step S8), and a hard mask 42 for etching the polysilicon film is formed on the polysilicon film (step S10). Thereafter, the polysilicon film is plasma-etched using the hard mask 42 as a mask, thereby forming the gate electrode 10 made of the polysilicon film (step S12). Here, the gate length of the patterned gate electrode 10 is set to about 50 nm. After the etching, the hard mask 42 is removed.

  Next, the surface of the gate electrode 10 is oxidized (step S14). Thereby, the damage received by plasma etching can be recovered. In addition, as a result of this step, a silicon oxide film 12 is formed on the surface of the gate electrode 10 as shown in FIG.

  Next, as shown in FIG. 5, the spacer 14 is formed (step S16). The spacer 14 first forms a silicon nitride film of about 10 nm on the substrate surface so as to cover the gate electrode 10. After that, by performing etch back, the silicon nitride film remains only on the side surface of the gate electrode 10, and the spacer 14 made of the silicon nitride film is formed. At the same time as this etch back, the portion of the gate insulating film 8 exposed on the Si substrate 2 is also removed.

Next, as shown in FIG. 6, the halo layer 18 is formed (step S18). The halo layer 18 is formed by implanting B or In ions with an energy of about 2 × 10 ¹³ / cm ^2, about 10 keV for B, and about 150 keV for In. The halo layer 18 functions as a punch-through stopper.

Next, as shown in FIG. 7, the extension 20 is formed (step S20). The extension 20 is formed by implanting, for example, As ions into the substrate at an energy of about 1 × 10 ¹⁵ / cm ^{2 and} about ² to 4 keV using the gate electrode 10 and the spacer 14 formed on the side surface as a mask. Is done.

  Next, the sidewall 16 is formed (step S22). In forming the sidewalls 16, first, as shown in FIG. 8, a silicon oxide film 44, a silicon nitride film 46, and a silicon oxide film 48 are sequentially formed on the entire surface of the substrate. Next, the silicon oxide film 48 and the silicon nitride film 46 are etched back to leave the silicon oxide film 48 and the silicon nitride film 46 only on the side surfaces of the gate electrode 10. Thereafter, as shown in FIG. 9, the lowermost silicon oxide film 44 is selectively removed by wet etching. Thereby, the side wall 16 can be formed while minimizing damage to the Si substrate 2.

Next, the source / drain 22 is formed (step S24). Here, the source / drain 22 is formed by implanting As ions with an energy of about 5 × 10 ¹⁵ / cm ^{2 and} about 40 keV using the gate electrode 10 and the sidewall 16 formed on the side surface of the gate electrode 10 as a mask. Is done.

Next, as shown in FIG. 10, F ions are implanted (step S26). F ions are implanted into the Si substrate 2 and the gate electrode 10 with an energy of about 1 × 10 ¹⁶ / cm ^{2 and} about 10 keV.
Next, heat treatment is performed at about 600 ° C. for about 2 minutes (step S28). As a result, F ions implanted into the Si substrate 2 and the gate electrode 10 diffuse to the gate insulating film 8.

After that, as shown in FIG. 11, a flash lamp is used to irradiate light having a wavelength of 1000 nm or less for about 1 millisecond (step S30). Further, heat treatment is subsequently performed at about 800 ° C. for about 1 second (step S32).
The impurities implanted into the source / drain 22 and the extension 20 are activated by the heat treatment by the flash lamp annealing. In addition, in flash lamp annealing, it is considered that many Si—H bonds in the gate insulating film 8 are broken. However, here, F ions are implanted in advance and diffused to the gate insulating film 8. Therefore, by this flash lamp annealing and subsequent heat treatment, the Si dangling bonds generated by the Si-H bond breaking and the Si existing dangling bonds are combined with F ions, and a large number of Si-F bonds are bonded. Is formed. Since this bond is stronger than the Si—H bond, it is not cut by flash lamp annealing, and exists in the gate insulating film 8 as an Si—F bond.

  Next, as shown in FIG. 12, NiSi layers 24 and 26 are formed (step S34). In forming the NiSi layers 24 and 26, first, a Ni film is formed on the entire surface of the substrate. After that, by applying heat treatment, Si and Ni react with each other at the portion where Si is in contact with the Ni film, that is, the surfaces of the gate electrode 10 and the source / drain 22, and NiSi layers 24 and 26 are formed in a self-aligned manner. The Thereafter, the unreacted Ni film is removed.

  Next, a silicon nitride film 32 and a silicon oxide film 34 are sequentially stacked on the substrate so as to embed the gate electrode 10 and the like formed on the Si substrate 2 (steps S36 and S38). Here, the silicon nitride film 32 functions as an etching stopper film during contact hole formation. Thereafter, the surface of the silicon oxide film 34 is planarized by CMP (step S40).

  Next, as shown in FIG. 13, the contact plug 36 is formed (step S42). The contact plug 36 first opens a contact hole by etching so as to penetrate a predetermined position of the silicon oxide film 34 and the silicon nitride film 32, and fills the contact hole with tungsten (W) or the like to flatten the surface. It is formed by doing.

  Further, a Cu wiring 40 connected to the insulating film 38 and the contact plug 36 is formed on the silicon oxide film 34 (steps S44 and S46), thereby forming a semiconductor device as shown in FIG.

  As described above, in the first embodiment, after the source / drain 22 is formed, F ions are implanted, and then flash lamp annealing is performed. Here, at the time of flash lamp irradiation, the Si—H bond existing in the gate insulating film 8 is cut by light having a short wavelength in the flash lamp. However, due to this flash lamp and subsequent heat treatment, Si dangling bonds that have been broken in the bond and Si that originally existed in the insulating film and F ions implanted in advance are bonded to form a Si-F bond. To do. Accordingly, generation of traps in the gate insulating film can be suppressed. In the first embodiment, the shallow junction of about 20 nm or less is realized for the source / drain 22 and the extension 20 by performing flash lamp annealing while suppressing the occurrence of traps. ing. Therefore, according to the first embodiment, a semiconductor device having a shallow junction diffusion layer with good device characteristics can be obtained.

  In the first embodiment, the case where F ions are implanted after the source / drain 22 is formed has been described. However, the present invention is not limited to this. F ions may be performed immediately before the source / drain 22 implantation or before the extension 20 is formed, and the same effect can be obtained in this way.

Further, in the first embodiment, the case where the implantation amount of F ions is 1 × 10 ¹⁶ / cm ² and the implantation energy is 10 keV has been described. However, the present invention is not limited to this. However, in order to effectively form a Si—F bond in the gate insulating film 8, the implantation amount of F ions is desirably 1 × 10 ¹⁵ / cm ² or more.

  In the first embodiment, the case where flash lamp annealing is performed has been described. However, in the present invention, the high-temperature and short-time heat treatment for realizing the shallow junction of the diffusion layer is not limited to that using a flash lamp. This heat treatment may be performed at a temperature of about 1100 ° C. or more and about 1 millisecond or less using light having a wavelength of about 1000 nm or less. For example, laser annealing may be considered. However, considering the strength of the Si—F bond, the wavelength of light used for this annealing is preferably about 200 nm or more.

  In the first embodiment, the case where the two-stage heat treatment is performed, that is, the flash lamp annealing and the subsequent heat treatment at about 800 ° C. within one second has been described. Thus, even if heat treatment is performed at about 800 ° C. or less for about 1 second after the flash lamp annealing, problems such as diffusion of the source / drain 22 can be suppressed. Further, in the flash lamp annealing, many Si—H bonds are broken. Therefore, in order to bond the implanted F ions and Si dangling bonds more reliably, it is effective to perform a heat treatment at a lower temperature for a shorter time than the flash lamp annealing after the flash lamp annealing. This heat treatment is preferably about 1000 ° C. or less and within about 1 second, and more preferably about 800 ° C. to 900 ° C. and within about 1 second. However, the present invention is not limited to this, and may be heat treatment only with flash lamp annealing. Even with flash lamp annealing alone, the Si-H bond Si or Si dangling bonds that have been cut to some extent can be Si-F bonds, and the effect of suppressing trap generation can be obtained. it can.

  In the first embodiment, the case where heat treatment is performed at about 600 ° C. for about 2 minutes in order to diffuse F ions after F ion implantation and before flash lamp annealing has been described. Thereby, the implanted F ions can be diffused into the gate insulating film 8 in advance, and Si—F bonds can be more effectively formed in the subsequent heat treatment. The temperature of this diffusion is not necessarily limited to this, but is desirably about 600 ° C. to 700 ° C. and within about 2 minutes in order to suppress the diffusion of impurities implanted into the source / drain 22. However, the present invention does not necessarily include such heat treatment. Even when the heat treatment for such F ion diffusion is not performed, since F ions are diffused to some extent into the gate insulating film 8, it is not possible to form Si—F bonds in the subsequent heat treatment. Can be obtained to some extent.

  In the first embodiment, the case where the source / drain 22 and the extension 20 are formed has been described. However, the present invention is not necessarily limited to such a structure, and can also be applied to the case where a uniform diffusion layer having a uniform implantation concentration and implantation depth is formed by one impurity implantation. .

Embodiment 2. FIG.
14 and 15 are schematic cross-sectional views for explaining a state in the manufacturing process of the semiconductor device according to the second embodiment of the present invention.
The semiconductor device in the second embodiment is similar to the semiconductor device described in the first embodiment. However, in the first embodiment, the surface of the Si substrate 2 is amorphized (amorphized) before the extension 20 is formed.

Specifically, the gate insulating film 8, the gate electrode 10, the silicon oxide film 12, the spacer 14 and the like are formed on the substrate through the same process as in the first embodiment (steps S2 to S16), and then the embodiment. Similar to 1, the halo layer 18 is formed.
Thereafter, in the second embodiment, as shown in FIG. 14, the vicinity of the surface of the Si substrate 2 is made amorphous to form an amorphous layer 50. The amorphous layer 50 is formed, for example, by implanting Ge ions at about 1 × 10 ¹⁵ / cm ^{2 and} about 10 keV.

Next, as in the first embodiment, the extension 20 is formed (step S20). However, since the amorphous layer 50 is formed here, the implantation amount is about 1 × 10 ¹⁵ / cm 2 and the implantation energy is about 2 to 4 keV. Thereafter, sidewalls are formed, and the source / drain 22 is formed (steps S22 to S24). In consideration of the formation of the amorphous layer 50, the implantation amount of impurities in forming the source / drain 22 is about 5 × 10 ¹⁵ / cm 2 and the implantation energy is about 40 keV. Further, F ions are implanted (step S26). The injection amount is about 5 × 10 ¹⁵ / cm 2 and the injection energy is about 10 keV.

  Thereafter, as in the first embodiment, heat treatment such as flash lamp annealing is performed (steps S28 to S32). Subsequent steps are the same as those described in the first embodiment.

  As described above, in the second embodiment, the region for forming the diffusion layer is made amorphous in advance. Thereby, in the subsequent ion implantation for forming the extension 20 and the source / drain 22, the impurity can be sufficiently diffused with smaller energy. Therefore, the diffusion layer can be made shallower.

  Also, in the second embodiment, similarly to the first embodiment, activation using flash lamp annealing is performed. In this way, shallow junction of the diffusion layer can be realized by using amorphization and further using flash lamp annealing. In the second embodiment, F ions are implanted before flash lamp annealing. Therefore, even when the Si—H bond is cut by flash lamp annealing, the Si dangling bond can be replaced with the Si—F bond. Therefore, generation of traps can be suppressed, and a semiconductor device with good device characteristics can be obtained while realizing a shallow junction diffusion layer.

In the second embodiment, the case where Ge ions are implanted with an energy of about 1 × 10 ¹⁵ / cm 2 and about 10 keV for amorphization has been described. However, the present invention is not limited to this. For example, Si ions or the like may be implanted instead of Ge ions. Further, the injection amount and the injection energy are not limited to this, and can be determined in consideration of the junction depth of the diffusion layer.

  In the second embodiment, the case where F ions are implanted after the impurity implantation for forming the source / drain 22 has been described. However, the present invention is not limited to this, and as described in the first embodiment, it may be before the sole / drain 22 is injected or before the extension 20 is injected. It may be before injection.

  In the first and second embodiments, the case where an nMOS is formed has been described. However, the present invention is not limited to this, and can be applied to, for example, pMOS or CMOS.

  For example, in the first and second embodiments, the “gate electrode forming step” of the present invention is performed by executing steps S8 to S10, and the “fluorine ion implantation” of the present invention is performed by executing step S26. The “process” is executed, and by executing steps S20 to S24, the “diffusion layer forming process” is executed, and by executing step S30, the “first heat treatment process” is executed.

  Further, for example, in the first and second embodiments, the “second heat treatment step” of the present invention is executed by executing step S32, and the “third heat treatment step” is executed by executing step S28. The Further, for example, in the first and second embodiments, the “extension forming process” of the present invention is executed by executing step S20, and the “source / drain forming process” is executed by executing steps S22 to S24. Executed. Further, for example, in the second embodiment, by forming the amorphous layer 50, the “amorphization step” of the present invention is executed.

It is a cross-sectional schematic diagram for demonstrating the semiconductor device in Embodiment 1 of this invention. It is a flowchart for demonstrating the manufacturing method of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 1 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 2 of this invention. It is a cross-sectional schematic diagram for demonstrating the state of the manufacturing process of the semiconductor device in Embodiment 2 of this invention.

Explanation of symbols

2 Si substrate 4 Element isolation 6 pWELL
8 Gate insulating film 10 Gate electrode 12 Silicon oxide film 14 Spacer 16 Side wall 18 Halo layer 20 Extension 22 Source / drain 24, 26 NiSi layer 32 Silicon nitride film 34 Silicon oxide film 36 Contact plug 38 Insulating film 40 Cu wiring 42 Hard mask 44 Silicon oxide film 46 Silicon nitride film 48 Silicon oxide film 50 Amorphous layer

Claims (6)

A gate electrode forming step of forming a gate electrode on a substrate via a gate insulating film;
A fluorine ion implantation step of implanting fluorine ions using at least the gate electrode as a mask;
A diffusion layer forming step of implanting impurities and forming a diffusion layer using at least the gate electrode as a mask;
A first heat treatment step of irradiating light having a wavelength of about 1000 nm or less for a time within about 1 second;
A method for manufacturing a semiconductor device, comprising: ^{2. The} method of manufacturing a semiconductor device according to claim 1, wherein the fluorine ion implantation step implants fluorine ions of about 1 × 10 ¹⁵ / cm ² or more.   3. The method of manufacturing a semiconductor device according to claim 1, further comprising a second heat treatment step of applying a heat treatment within about 1 second at a temperature of about 1000 ° C. or less after the first heat treatment step. 4.   4. The semiconductor device manufacturing method according to claim 1, further comprising a third heat treatment step of applying a heat treatment within about 2 minutes at a temperature of about 600 ° C. or less before the first heat treatment step. 5. Method.   5. The method of manufacturing a semiconductor device according to claim 1, further comprising an amorphization step of amorphizing a region where the diffusion layer is formed before the diffusion layer formation step. . The diffusion layer forming step includes
Using at least the gate electrode as a mask, implanting impurities, and forming an extension; and
A source / drain forming step of forming a sidewall on the side surface of the gate electrode, implanting impurities using at least the gate electrode and the sidewall as a mask, and forming a source / drain;
The method of manufacturing a semiconductor device according to claim 1, comprising:

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