JP2014072306A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method, which achieve a short turn-off time and relatively low on-state voltage, and which inhibit increase in manufacturing cost.SOLUTION: A semiconductor device comprises: a first conductivity type collector region which has first and second principal surfaces opposite to each other and which has a higher activation rate of a first conductivity type impurity and less crystal defect on the second principal surface side than on the first principal surface side; a second conductivity type semiconductor substrate arranged on the first principal surface of the collector region; a first conductivity type base region arranged on the semiconductor substrate; a second conductivity type emitter region arranged on the base region; a gate insulation film arranged on the base region and at least between a drift region and the emitter region; a gate electrode arranged opposite to the base region via the gate insulation film; a collector electrode arranged on the second principal surface of the collector region; and an emitter electrode electrically connected with the emitter region.

Description

  The present invention relates to a semiconductor device having an IGBT structure and a method for manufacturing the semiconductor device.

  Insulated gate bipolar transistors (IGBTs) have high input impedance and low on-voltage, and are therefore used in motor drive circuits and the like. However, even if an off signal is applied to the control electrode (gate electrode), the IGBT is not turned off until the remaining holes injected from the P-type collector region into the N-type drift region are discharged from the drift region. . Furthermore, when the electrons remaining in the drift region pass through the collector region, holes are injected from the collector region into the drift region. For this reason, the IGBT has a problem that the turn-off time is long.

  Therefore, in order to improve the turn-off time of the IGBT, there is a method of reducing the carrier life by the low lifetime layer. Specifically, there are a method of forming a low lifetime layer by diffusing heavy metals such as gold and platinum, and a method of forming a low lifetime layer by irradiating radiation such as an electron beam or a neutron beam.

  However, there is a problem that the formation of the low lifetime layer causes a decrease in carrier lifetime, lowers the conductivity and modulation degree, which are the merits of the IGBT, and increases the on-voltage. In particular, when a low lifetime layer is formed in the drift region, there are problems such as breakdown voltage degradation, a problem of drawing a long tail current during turn-off, and an increase in on-voltage due to a decrease in carrier lifetime.

  For this reason, a method for realizing a short turn-off time and a low on-voltage with a low lifetime layer formed in the collector region by irradiation with high-energy particles and having at least a recombination peak in the collector region is proposed. (For example, refer to Patent Document 1).

JP-A-4-269874

  However, the formation of the low lifetime layer by irradiation with high energy particles is performed after the formation of the collector region. Therefore, a process for forming a low lifetime layer is added, and the manufacturing cost increases. Furthermore, the thickness of the write punch-through type IGBT and field stop type IGBT at the stage where the formation of the collector region is completed is 100 μm or less, which is thinner than the non-punch-through type IGBT. For this reason, the processing yield is likely to decrease due to, for example, cracking of the wafer during transportation before and after forming the low lifetime layer. As a result, the manufacturing cost increases.

  Moreover, in order to form a low lifetime layer at a desired depth, high-precision alignment is necessary. However, when the low lifetime layer is formed in the collector layer as in Patent Document 1, for example, there are variations in the manufacturing apparatus for forming the low lifetime layer and variations in the depth of the collector region of the semiconductor device. There is a tendency for errors to occur in the positional relationship between the low lifetime layer. As a result, the yield decreases and the manufacturing cost increases.

  In view of the above problems, an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that realize a short turn-off time and a relatively low on-voltage, and that suppress an increase in manufacturing cost.

  According to one aspect of the present invention, (i) having first and second main surfaces facing each other, the activity of the first conductivity type impurity on the second main surface side rather than the first main surface side A first conductivity type collector region having a high conversion rate and few crystal defects; (b) a second conductivity type semiconductor substrate disposed on the first main surface of the collector region; and (c) on the semiconductor substrate. And (d) an emitter region of the second conductivity type disposed on the base region, and (e) disposed on the base region at least between the semiconductor substrate and the emitter region. A gate insulating film; (f) a gate electrode disposed opposite the base region through the gate insulating film; (g) a collector electrode disposed on the second main surface of the collector region; Provided is a semiconductor device comprising an emitter region and an emitter electrode electrically connected

  According to another aspect of the present invention, (b) forming a first conductivity type base region on a second conductivity type semiconductor substrate; and (b) forming a second conductivity type emitter region on the base region. (C) a step of implanting a first conductivity type impurity from the lower surface opposite to the upper surface of the semiconductor substrate to the lower surface side of the semiconductor substrate; and (d) a first region closer to the lower surface than a region spaced from the lower surface. And heating the semiconductor substrate from the lower surface side so that the activation rate of the conductive impurities is high, and forming a first conductivity type collector region on the lower surface side of the semiconductor substrate. .

  ADVANTAGE OF THE INVENTION According to this invention, the short turn-off time and the comparatively low on-voltage can be implement | achieved, and the manufacturing method of the semiconductor device with which the increase in manufacturing cost was suppressed can be provided.

It is a typical sectional view showing the structure of the semiconductor device concerning the embodiment of the present invention. It is a graph which shows the influence which acts on the characteristic of the activation rate in IGBT. It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 1). It is typical process sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on embodiment of this invention (the 2). FIG. 9 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 3). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 4). FIG. 10 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 5). FIG. 6 is a schematic process cross-sectional view for explaining the manufacturing method of the semiconductor device according to the embodiment of the present invention (No. 6). It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the modification of embodiment of this invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on other embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness and the planar dimensions, the ratio of the lengths of the respective parts, and the like are different from the actual ones. Therefore, specific dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  The following embodiments exemplify apparatuses and methods for embodying the technical idea of the present invention, and the technical idea of the present invention includes the shape, structure, arrangement, etc. of components. It is not specified to the following. The embodiment of the present invention can be variously modified within the scope of the claims.

  As shown in FIG. 1, the semiconductor device 1 according to the embodiment of the present invention includes a first conductivity type collector region 10 having a first main surface 101 and a second main surface 102 facing each other, and a collector region 10. The second conductivity type semiconductor substrate 20 disposed on the first main surface 101, the first conductivity type base region 30 disposed on the semiconductor substrate 20, and a part of the upper surface of the base region 30 are selected. Embedded emitter region 40 of the second conductivity type, collector electrode 90 disposed on second main surface 102 of collector region 10, and emitter electrode 80 electrically connected to emitter region 40. Prepare.

  The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type. Hereinafter, a case where the first conductivity type is P type and the second conductivity type is N type will be described as an example.

  In the semiconductor device 1, the impurities injected into the collector region 10 are activated on the second main surface 102 side of the collector region 10, that is, on the collector electrode side, compared to the first main surface 101 side, that is, the semiconductor substrate side. The ratio (hereinafter referred to as “activation ratio”) is high and there are few crystal defects. The collector region 10 is made of silicon (Si), and the first conductivity type impurity in the collector region 10 is, for example, boron (B).

  The semiconductor device 1 is an insulated gate bipolar transistor (IGBT), and includes a gate insulating film 50 disposed on the base region 30 at least between the semiconductor substrate 20 and the emitter region 40, and the base region 30 via the gate insulating film 50. And a gate electrode 60 disposed to face each other. The example shown in FIG. 1 is a trench gate structure. That is, a groove extending from the upper surface of the emitter region 40 and penetrating at least the emitter region 40 and the base region 30 is formed. The gate insulating film 50 is disposed on the inner wall of the trench, and the gate electrode 60 is embedded in the trench through the gate insulating film 50. That is, the gate electrode 60 faces the base region 30 with the gate insulating film 50 interposed therebetween. The surface of the base region 30 facing the gate electrode 60 is the channel region 100.

  In the semiconductor device 1 of FIG. 1, the semiconductor substrate 20 includes an N-type buffer region (also referred to as a field stop region) 21 in contact with the collector region 10, and a buffer region 21 disposed between the buffer region 21 and the base region 30. Also have an N− type drift region 22 with a low impurity concentration. An interlayer insulating film 70 is disposed on the upper surface of the gate electrode 60, and an emitter electrode 80 connected to the emitter region 40 and the base region 30 is disposed on the interlayer insulating film 70.

  The operation of the semiconductor device 1 will be described. A predetermined collector voltage is applied between the emitter electrode 80 and the collector electrode 90, and a predetermined gate voltage is applied between the emitter electrode 80 and the gate electrode 60. For example, the collector voltage is about 300V to 1600V, and the gate voltage is about 10V to 20V. When the semiconductor device 1 is turned on in this way, the channel region 100 is inverted from P-type to N-type, and a channel is formed. Through the formed channel, electrons are injected from the emitter electrode 80 into the semiconductor substrate 20. The injected electrons cause a forward bias between the collector region 10 and the semiconductor substrate 20, and holes move from the collector electrode 90 through the collector region 10 in the order of the semiconductor substrate 20 and the base region 30. . As the current is further increased, holes from the collector region 10 increase and holes are accumulated below the base region 30. As a result, the on-resistance decreases due to conductivity modulation.

  When the semiconductor device 1 is switched from the on state to the off state, the gate voltage is set lower than the threshold voltage, for example, the channel region 100 is controlled by controlling the gate voltage to be the same potential or negative potential as the emitter voltage. Annihilate. Thereby, the injection of electrons from the emitter electrode 80 into the semiconductor substrate 20 is stopped, and the injection of holes from the collector region 10 into the semiconductor substrate 20 is also stopped. Since the potential of the collector electrode 90 is higher than that of the emitter electrode 80, a depletion layer spreads from the interface between the base region 30 and the semiconductor substrate 20 and holes accumulated in the semiconductor substrate 20 escape to the emitter electrode 80. .

  In general, in a high breakdown voltage IGBT, when a higher voltage than the emitter electrode, for example, 600 V is applied to the collector electrode, and the potential of the gate electrode (gate voltage) is made lower than the threshold voltage, the IGBT is turned off. The depletion layer extending from the PN junction at the boundary between the base region and the drift region is designed to extend to the extent that it reaches the collector region. The depletion layer is in a state where electrons are discharged.

  In the IGBT, when electrons are injected into the P-type collector region, holes are injected from the collector region into the drift region so as to cancel the electron injection. If there is a crystal defect layer in the collector region, electrons that have moved to the collector region are taken into the crystal defect layer. As a result, the state is the same as when electrons are not injected into the collector region, and holes are not injected from the collector region into the drift region, or the amount injected is very small.

  However, the semiconductor device 1 shown in FIG. 1 has a higher activation rate and fewer crystal defects on the collector electrode side of the collector region 10 than on the semiconductor substrate side. That is, there are few crystal defects in the collector region 10 as a whole while increasing crystal defects on the drain region side of the collector region 10. As a result, the trapping of electrons injected from the drift region 22 in the crystal defects in the entire collector region 10 can be limited to a certain amount, and an increase in on-voltage can be suppressed.

  On the other hand, since the semiconductor substrate side of the collector region 10 has more crystal defects than the collector electrode side, electrons injected from the semiconductor substrate 20 at the turn-off time are effectively captured on the semiconductor substrate side of the collector region 10. For this reason, the injection amount of holes from the collector region 10 to the semiconductor substrate 20 is easily controlled while suppressing an increase in the ON voltage. As a result, the semiconductor device 1 can obtain high-speed switching characteristics with a short turn-off time.

The ratio of the first conductivity type impurities implanted into the semiconductor substrate 20 to form the collector region 10 to be covalently bonded to the atoms constituting the semiconductor substrate 20 by activation is 90% or less as a whole. preferable. FIG. 2 shows the results of investigating the influence of the activation rate in the IGBT on the characteristics. The horizontal axis in FIG. 2 is the switching time tf indicating the turn-off time, and the vertical axis is the collector-emitter saturation voltage V _CESAT . In FIG. 2, the case where the activation rate is 100% is indicated by the characteristic A, and the case where the activation rate is 90% is indicated by the characteristic B. As shown in FIG. 2, when the activation rate is 90%, the switching time tf is shorter at the same saturation voltage V _CESAT than when the activation rate is 100%. .

  In the embodiment of the present invention, the “crystal defect” refers to lattice distortion (diffusion of particles having different sizes, such as atomic vacancies, dangling bonds, or impurities that are conductivity type determining atoms). This refers to the state of crystal defects in which (interstitial distortion) occurs.

  A method for manufacturing the semiconductor device 1 according to the embodiment of the present invention will be described with reference to FIGS. In addition, the manufacturing method described below is an example, and it is needless to say that it can be realized by various other manufacturing methods including this modified example.

As shown in FIG. 3, a P-type base region 30 is formed on the upper surface 201 of the N− type semiconductor substrate 20. For example, the base region 30 is formed using an epitaxial growth method or an ion implantation method and diffusion. Next, as shown in FIG. 4, an N ⁺ -type emitter region 40 is selectively formed on a part of the upper surface of the base region 30 by using, for example, an ion implantation method and diffusion.

Using a photolithographic technique and an etching technique, a groove having an opening on the emitter region 40 and penetrating the emitter region 40 and the base region 30 and reaching the semiconductor substrate 20 is formed. Then, a gate insulating film 50 is formed on the inner wall of the trench. For example, a silicon oxide (SiO ₂ ) film is formed by a thermal oxidation method. Thereafter, a polysilicon film to which impurities are added is embedded in the trench. Further, the surface of the base region 30 is planarized by a polishing process such as chemical mechanical polishing (CMP) to form the gate electrode 60 as shown in FIG.

  After the interlayer insulating film 70 is formed on the gate electrode 60, an emitter electrode 80 connected to the emitter region 40 and the base region 30 is formed on the interlayer insulating film 70 as shown in FIG.

  As indicated by an arrow in FIG. 7, the second conductivity type impurity is implanted into the semiconductor substrate 20 from the lower surface 202 of the semiconductor substrate 20, and an annealing process is performed. Thereby, the second conductivity type buffer region 21 is formed on the lower surface side of the semiconductor substrate 20. The remaining region of the semiconductor substrate 20 where the buffer region 21 is formed is a drift region 22. The impurity concentration of the buffer region 21 is set higher than that of the drift region 22.

Next, in order to form the collector region 10, a first conductivity type impurity is implanted into the semiconductor substrate 20 from the lower surface 202 of the semiconductor substrate 20 as indicated by an arrow in FIG. 8. The dose of the impurity implanted at this time is, for example, about 1 × 10 ¹¹ to 10 ¹⁴ cm ⁻² . Then, the semiconductor substrate 20 is heated from the lower surface 202 side so that the activation rate of the first conductivity type impurity is higher in the vicinity of the lower surface 202 than the region on the drift region 22 side separated from the lower surface 202. As a result, the collector region 10 having a higher activation rate of the first conductivity type impurity on the second main surface 102 side than on the first main surface 101 side is formed. Therefore, in the collector region 10, there are fewer crystal defects on the second main surface 102 side than on the first main surface 101 side.

  Since the collector region 10 is formed on the lower surface side of the semiconductor substrate 20 using ion implantation and heat treatment as described above, the lower surface 202 of the semiconductor substrate 20 and the second main surface 102 of the collector region 10 coincide with each other. To do.

  Thereafter, the collector electrode 90 is formed on the second main surface 102 of the collector region 10 to complete the semiconductor device 1 shown in FIG.

  In general, since the implanted dopant ions are not activated only by ion implantation, the activation treatment after ion implantation is a necessary step. In the embodiment of the present invention, “activity” is used to describe the ratio of implanted ions that contribute to the total carrier concentration of the base material into which ions are implanted. During ion implantation, bombardment by dopant ions to the crystal lattice of the matrix is substantially applied, and the ions collide with the crystal lattice and are retained in the crystal lattice. Thereafter, by an activation process such as an annealing process, the implanted ions and the crystal lattice of the base material are rearranged in a more regular manner, and the ions are fixed at positions in the crystal lattice. Thereby, damage to the base material received by the dopant ions is recovered.

  In the embodiment of the present invention, the collector region 10 is formed by implanting impurities from the lower surface side of the semiconductor substrate 20 and further heating the semiconductor substrate 20 from the lower surface side to activate the impurities. At this time, by heating at a high temperature for a short time, the collector electrode 90 side becomes a well activated region, and the semiconductor substrate 20 side has a higher proportion of non-activation than the collector electrode 90 side. Can be realized. For example, when the activation rate on the collector electrode 90 side of the collector region 10 is 100%, the activation rate on the semiconductor substrate 20 side of the collector region 10 is 80% or less, preferably 40% or less. As a result, ions are not activated on the semiconductor substrate 20 side of the collector region 10 and a large number of crystal defects can be left.

  In order to form the collector region 10 having the above-described structure, when the collector region 10 is formed, the semiconductor substrate 20 is heated, for example, at a temperature of 1200 ° C. to 1300 ° C. within a few seconds or within one second. For this purpose, a laser annealing method, a flash annealing method, or the like is preferably used. That is, by appropriately setting the laser power and irradiation time in the laser annealing method, and appropriately setting the heating temperature and heating time in the flash annealing method, impurities on the collector electrode 90 side of the collector region 10 can be sufficiently obtained. As a result, many crystal defects can be left on the semiconductor substrate 20 side.

  The semiconductor substrate 20 is preferably made of Si. For example, in a substrate made of a compound semiconductor such as silicon carbide (SiC), it is known that 100% of implanted impurities are not activated even if annealing is performed. SiC is a compound of silicon (Si) and carbon (C), and the sizes of Si and C atoms are also different, for example, different from dopant ions such as nitrogen (N). Furthermore, the crystal structure is the hardest diamond structure. For this reason, even if it is desired to activate well, the dopant ions are not sufficiently replaced with the atoms of the base material.

  On the other hand, in a base material made of silicon, it is easy to replace dopant ions and Si by annealing. Boron (B) or the like can be used as an impurity implanted into the semiconductor substrate 20 in order to form the collector region 10.

  As described above, the collector region 10 is formed by impurity implantation and annealing. The depth at which the first conductivity type impurity is implanted into the semiconductor substrate 20 to form the collector region 10 is several μm, for example, about 1 to 3 μm from the lower surface 202 of the semiconductor substrate 20. For this reason, unlike the case where it is formed by epitaxial growth or the like, the collector region 10 has a thin film thickness of 1 to 3 μm or less. Therefore, the semiconductor device 1 is suitable for a light punch-through type IGBT or a field stop type IGBT in which the collector region 10 is thin.

  In the above manufacturing method, the portion in which the crystal defect of the collector region 10 generated when dopant ions are implanted into the semiconductor substrate 20 functions in the same manner as the low lifetime layer. Therefore, the semiconductor device 1 that effectively captures the electrons remaining in the drift region 22 at the time of turn-off can be manufactured without adding a special process for forming the low lifetime layer. For this reason, the increase in manufacturing cost can be suppressed.

  Further, the recombination of the low lifetime layer formed by irradiation with high energy particles generally has a Gaussian distribution. For this reason, if the peak of the low lifetime layer is formed on the drift region side of the collector region in order to shorten the turn-off time, a crystal defect occurs in the drift region, and the problem of pulling a long tail current at the time of turn-off deterioration or turn-off, Problems such as an increase in on-voltage due to a decrease in carrier lifetime occur.

  On the other hand, according to the manufacturing method of the semiconductor device according to the embodiment of the present invention that does not perform irradiation with high energy particles, a problem caused by irradiation with high energy particles does not occur. Furthermore, the high precision required to form the low lifetime layer at the desired depth is not necessary. Therefore, the semiconductor device 1 can be manufactured at a low cost with a short turn-off time without considering a positional relationship in which an error between the collector region and the low lifetime layer is likely to occur.

  As described above, according to the method of manufacturing a semiconductor device according to the embodiment of the present invention, the collector region 10 having a higher activation rate and fewer crystal defects is formed on the collector electrode side than on the semiconductor substrate side. . As a result, it is possible to obtain the semiconductor device 1 that realizes a short turn-off time and a relatively low on-voltage and suppresses an increase in manufacturing cost.

<Modification>
In the semiconductor device 1 shown in FIG. 1, the buffer region 21 is disposed between the collector region 10 and the drift region 22. However, as shown in FIG. 9, the buffer area 21 may not be arranged.

  However, by arranging the buffer region 21, the amount of holes remaining in the drift region 22 at the time of turn-off can be controlled to some extent. For this reason, turn-off time is suppressed. Further, by arranging the buffer region 21, when a ground potential or a reverse bias is applied between the gate and the emitter of the semiconductor device 1 and a depletion layer spreading from the base region 30 side of the drift region 22 is generated, the depletion layer is formed. It is possible to prevent the collector region 10 from reaching the buffer region 21.

(Other embodiments)
As mentioned above, although this invention was described by embodiment, it should not be understood that the description and drawing which form a part of this indication limit this invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  In the description of the embodiment already described, the example in which the semiconductor device 1 has the trench gate structure is shown. However, the present invention can also be applied when the semiconductor device 1 has a planar structure. FIG. 10 shows an example of a semiconductor device 1 having a planar structure. In the semiconductor device 1 shown in FIG. 10, the gate electrode 60 is disposed on the base region 30 via the gate insulating film 50. An interlayer insulating film 70 is disposed between the gate electrode 60 and the emitter electrode 80. The surface of the base region 30 that faces the gate electrode 60 through the gate insulating film 50 is a channel region.

  Also in the case of the semiconductor device 1 having the planar structure shown in FIG. 10, the activation rate is higher on the collector electrode side and the number of crystal defects is smaller than that on the semiconductor substrate side of the collector region 10. For this reason, the semiconductor device 1 which realizes a short turn-off time and a relatively low on-voltage and suppresses an increase in manufacturing cost can be obtained. Further, a second conductivity type carrier accumulation region having a higher impurity concentration than the drift region 22 may be sandwiched between the base region 30 and the drift region 22. In this case, the semiconductor substrate 20 may include a carrier accumulation region. Further, the activation rate of the collector region 10 may be changed between the active region and the outer peripheral region surrounding the active region. For example, a semiconductor device with a shorter turn-off time and a relatively lower on-voltage can be provided by lowering the activation rate on the outer peripheral region side than the active region.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... Semiconductor device 10 ... Collector region 20 ... Semiconductor base | substrate 21 ... Buffer region 22 ... Drift region 30 ... Base region 40 ... Emitter region 50 ... Gate insulating film 60 ... Gate electrode 70 ... Interlayer insulating film 80 ... Emitter electrode 90 ... Collector electrode DESCRIPTION OF SYMBOLS 100 ... Channel region 101 ... 1st main surface 102 ... 2nd main surface 201 ... Upper surface 202 ... Lower surface

Claims (10)

The first and second main surfaces facing each other, the activation rate of the first conductivity type impurities on the second main surface side is higher than the first main surface side, and there are few crystal defects; A collector region of a first conductivity type;
A second conductivity type semiconductor substrate disposed on the first main surface of the collector region;
A base region of a first conductivity type disposed on the semiconductor substrate;
An emitter region of a second conductivity type disposed on the base region;
A gate insulating film disposed on the base region at least between the semiconductor substrate and the emitter region;
A gate electrode disposed to face the base region via the gate insulating film;
A collector electrode disposed on the second main surface of the collector region;
A semiconductor device comprising: an emitter electrode electrically connected to the emitter region. The semiconductor substrate is
A buffer region in contact with the collector region;
The semiconductor device according to claim 1, further comprising: a drift region that is disposed between the buffer region and the base region and has a lower impurity concentration than the buffer region. The collector region is made of silicon;
The semiconductor device according to claim 1, wherein the first conductivity type impurity in the collector region is boron.   4. The semiconductor device according to claim 1, wherein a film thickness of the collector region is 3 μm or less. 5. A groove extending from the upper surface of the emitter region and penetrating at least the emitter region and the base region is formed,
The gate insulating film is disposed on an inner wall of the trench;
The semiconductor device according to claim 1, wherein the gate electrode is embedded in the trench through the gate insulating film. Forming a first conductivity type base region on a second conductivity type semiconductor substrate;
Forming an emitter region of a second conductivity type on the base region;
Injecting a first conductivity type impurity from a lower surface facing the upper surface of the semiconductor substrate to a lower surface side of the semiconductor substrate;
The semiconductor substrate is heated from the lower surface side so that the activation rate of the first conductivity type impurities is higher in the vicinity of the lower surface than in the region spaced from the lower surface, so that the first conductivity type collector region is formed on the semiconductor substrate. Forming on the lower surface side. A method for manufacturing a semiconductor device, comprising: Forming a second conductivity type buffer region on the lower side of the semiconductor substrate before forming the collector region;
The method of manufacturing a semiconductor device according to claim 6, wherein the collector region is formed on a surface side of the buffer region so that the buffer region remains on the lower side of the semiconductor substrate.   8. The method of manufacturing a semiconductor device according to claim 6, wherein the semiconductor substrate into which the first conductivity type impurity is implanted is heated at a temperature of 1200 ° C. to 1300 ° C. when the collector region is formed.   9. The method of manufacturing a semiconductor device according to claim 8, wherein the collector region is formed by heating the semiconductor substrate using a laser annealing method or a flash annealing method. Forming an opening in the emitter region and forming a groove that reaches the semiconductor substrate through the emitter region and the base region;
Forming a gate insulating film on the inner wall of the trench;
The method for manufacturing a semiconductor device according to claim 6, further comprising: forming a gate electrode inside the trench in which the gate insulating film is formed.

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