JPH03159245A - Lateral transistor - Google Patents

Abstract

PURPOSE:To contrive the improvement of a current-amplification factor and a reduction in a leakage current into a semiconductor substrate by a method wherein an emitter region and a collector region are formed by a vertical separated diffusion and the respective depths of the emitter and collector regions are sufficiently deepened to a buried region which is the lower layer of the regions. CONSTITUTION:The depths of an emitter region 6 and a collector region 7 are both extended to a buried region 2 which is the lower layer of the regions 6 and 7. By forming the regions 6 and 7 by a vertical separated diffusion, the regions 6 and 7 can be respectively formed deep to the region 2 which is the lower layer of the regions 6 and 7. Thereby, the effective area of an emitter and the effective area of a collector are both increased and with the collection efficiency of holes from the emitter improved, a current capacity is increased and a current amplification factor is improved. Moreover, the existence of a parasitic p-n-p transistor can be lessened and a leakage current into a substrate 1 is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION <Field of Industrial Application> The present invention relates to a lateral transistor incorporated in a semiconductor integrated device of a vertically separated type.

<Prior Art> FIG. 2 shows an example of the structure of a lateral pnp transistor incorporated in a semiconductor integrated device of a vertically separated type.

An n-type buried region 2 and an n-type buried region 2 are formed in the p-type silicon base Fi1.
A type epitaxial region 4 is formed. In this epitaxial region 4, a p+ emitter region 26 and a p° collector region 27, which were formed simultaneously in the base diffusion process of the npn transistor, and an n base contact region 8, which was formed simultaneously in the emitter diffusion process, are provided. Each is provided. In addition, around these regions, a lower surface isolation region 3 and an upper surface isolation region 5 are formed.
is formed.

With the above structure, holes injected from the emitter are diffused laterally and collected at the collector. That is, it operates as a lateral transistor.

<Problem to be Solved by the Invention> By the way, according to the lateral transistor having the structure shown in FIG. 2, the emitter region 26 and the collector region 27 are
Since it is formed at the same time as the base diffusion process of the npn type tosynister, its depth is shallow and both the effective emitter area and the effective collector area are small. For this reason, the collection efficiency of holes injected from the emitter is poor, and as a result, H
There is a problem that fe (current amplification factor) is low, and that the current capacity is small and the Hfe decreases greatly at high current. Furthermore, there is a parasitic pnp caused by the emitter region 26, epitaxial region 4, and p-type silicon substrate 1, and some of the holes injected from the emitter flow toward the substrate, resulting in a leakage current to the p-type silicon substrate 1. The problem was that it was big.

Means for Solving the Problems> The present invention has been made to solve the above problems.
The structure will be explained with reference to FIG. 1 corresponding to an embodiment. The present invention provides a lateral transistor (pnp type) incorporated in a semiconductor integrated device of a vertical separation type.
Both the depths of the emitter region 6 and the collector region 7 are
It is characterized by extending to the buried region 2 in the lower layer.

By forming the emitter region 6 and the collector region 7 by upper and lower separation diffusion, the emitter region and the collector region can be formed deep to the buried region 2 in the lower layer, thereby reducing the effective emitter area and the effective collector region. Both areas become larger, improving the efficiency of collecting holes from the emitter and increasing the current capacity.

Furthermore, the presence of parasitic pnp can be reduced.

<Example> FIG. 1 is a sectional view showing the structure of an embodiment of the present invention.

An n-type buried region 2 and an n-type epitaxial region 4 are formed on a p-type semiconductor substrate 1, and around the sides of the buried region 2, a lower surface p° isolation region 3 and an upper surface isolation region are formed. 5 is formed.

In the epitaxial region 4, n=base contact%
An M region 8 is formed. In addition, the epitaxial region 4
A P emitter region 6 consisting of a lower diffusion region 6a and an upper diffusion region 6b is formed therein, and a P collector region 6 consisting of a lower diffusion region 7a and an upper diffusion region 7b is formed around the sides of the emitter region 6. A region 7 is formed.

Emitter region 6 and collector region 7 are formed by a procedure described later, and extend into buried region 2 in the depth direction.

The upper surface of the epitaxial region 4 is covered with a protective film 9, and an emitter electrode 16, a collector electrode 17, and a base electrode 18 are formed, which are electrically connected to each region through contact holes in the protective film 9. ing.

Next, the manufacturing procedure of the above structure will be explained.

First, an n-type buried region 2 and a lower surface p-isolation region 3 are sequentially formed in a p-type semiconductor substrate 1 by diffusion. Simultaneously with this step of forming isolation region 3, lower surface isolation regions 6a and 7a of emitter region 6 and collector region 7, respectively, are formed.

Next, after laminating the n-type epitaxial region 4, the upper surface isolation region 5 is formed by diffusion. In this diffusion step, upper surface isolation regions 6b and 7b of emitter region 6 and collector region 7 are also formed at the same time.

Next, the npn to be incorporated into other regions of this semiconductor device
) Simultaneously with the emitter n' diffusion process of the transistor, an n' base contact region 8 is formed.

After forming a protective film 9 such as SiO□, each region 6
, 7.8, the lateral pn of the structure shown in FIG.
p) A transistor can be obtained.

As described above, by forming the emitter region 6 and the collector region 7 by upper and lower separation diffusion, the depth of each can be made sufficiently deep to the buried region 2 in the lower layer, and the effective emitter area and the effective collector area can be increased. Both become wider. As a result, holes injected from the emitter are efficiently collected in the collector, improving Hfe. Furthermore, parasitic pnp hardly exists, and leakage current to the p-type semiconductor substrate 1 is reduced. Furthermore, since the effective emitter area becomes larger, its current capacity becomes larger, and a decrease in Hfe at high currents can be suppressed.

<Effects of the Invention> As described above, according to the present invention, in a lateral transistor incorporated in a semiconductor integrated device of a vertical separation type, the emitter region and the collector region are formed by vertical separation diffusion, and the depth of each is reduced. Since the depth is sufficiently deep to reach the buried region in the lower layer, Hfe (current amplification factor) is improved and leakage current to the semiconductor substrate is reduced compared to the conventional case. Furthermore, it is possible to reduce the decrease in Hfe at high currents.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of an embodiment of the present invention. FIG. 2 is a cross-sectional view showing an example of the structure of a conventional lateral pnp transistor. 1... P-type semiconductor substrate 2... N-type buried region 3... Lower surface P" isolation region 4... N-type epitaxial region 5... Upper surface P" isolation region 6, 6a, 6b, 7・ 7a ・ 7b ・ 8 ・ 9 ・ 16 ・ 17 ・ 18 ・ p゛ Emitter region surface diffusion region (emitter region) Top surface diffusion region (emitter region) p゛ Collector region surface diffusion region (collector region) Top surface diffusion region (collector region ) n゛Base contact area protective film emitter electrode collector electrode base electrode

Claims (1)

[Claims] A lateral transistor incorporated in a semiconductor integrated device of a vertical diffusion separation type, characterized in that the depths of both an emitter region and a collector region extend to a buried region below the emitter region.