JPS59766Y2 - semiconductor equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a lateral transistor formed from a multi-collector formed in a semiconductor integrated circuit.

Generally, a semiconductor integrated circuit (hereinafter abbreviated as IC) has N
The conditions are favorable for the fabrication of PN type transistors, and it is extremely difficult to fabricate high performance vertical PNP (PNP) transistors in ICs.

In order to solve this problem, we changed the manufacturing method of NPN) transistor.
A process for making a P-type transistor is added and a so-called Darnonton connection is performed to improve electrical characteristics such as current amplification factor.

Yet another method is to use PNPN lateral transistors, which can be easily formed into ICs, as shown in FIG.

However, in a PNPN lateral transistor, it goes without saying that the transistor operation is mainly in the lateral direction, and the carrier loss is large, so the current amplification factor β of the lateral transistor is extremely small compared to that of a vertical transistor. .

Carriers that are not involved in current amplification are collected in the separation layer and the semiconductor substrate, forming a parasitic PNP transistor or causing thyristor operation in the separation layer region, causing oscillation.

The present invention improves the problem of sloping and provides a highly reliable lateral transistor comprising a multi-collector by providing a collector region for collecting carriers not involved in current amplification.

Furthermore, the semiconductor device of the present invention aims to equalize the carrier collection rate of each collector electrode of a lateral transistor in which a multi-collector is formed.

The present invention will be explained below based on the drawings.

FIG. 1 is a cross-sectional view of a typical lateral transistor.

1 is a P-type semiconductor substrate, 2 is an N-type semiconductor layer 3 is an N+ type buried layer, 4 is a P+ type isolation layer for separating IC elements,
5, 6, and 7 are an emitter region, a collector region, and a base region, respectively, formed in the N-type semiconductor layer 2 separated by the separation layer 4.

In such a lateral transistor, carriers injected from the emitter region 5 are lateral ae, as illustrated in FIG.
component and a vertical b component.

The a-component carriers diffusing in the lateral direction are in the collector region 6.
However, components that diffuse in the vertical direction have the disadvantage that they tend to reach the N+ type buried layer or be collected in the P+ type isolation layer, causing parasitic effects.

According to the embodiment of the present invention shown in FIG. 2, the above-mentioned parasitic effects are alleviated and a highly reliable device is obtained.

The configuration will be explained with reference to FIG. 2, a cross-sectional view of the semiconductor device.

1 is a P-type semiconductor substrate, 2 is an N-type semiconductor layer, 3 is an N+-type buried layer, and 4 is a P+-type bone separation layer 5 for isolating between IC elements. Emitter area 6
-1 is a P+ type first collector region surrounding the outer periphery of the emitter region 5, and 6-2 is a P+ type collector region surrounding the first collector region, which is deeper than the diffusion depth of the first collector region. It has reached the vicinity of the N+ type buried layer.

According to this configuration of the present invention, as illustrated in FIG. 1, the b component of carriers injected from the emitter region 5 and diffusing in the vertical direction is captured in the second collector region 6-2. , the parasitic effect of the P+ bone separation layer can be reduced as much as possible.

According to an embodiment of the present invention, the collector regions 6-1 and 6-
It is clear that the collector region can be formed in multiple layers up to a distance that can reach the lifetime of the carriers injected from the emitter region, without being limited to this. be.

In such a collector region, a multi-collector is formed by sequentially forming the collector region deeper from the innermost collector region toward the outside to reach the vicinity of the N+ type buried layer.
The object of the present invention can be achieved by forming the outermost collector region so as to reach the vicinity of the N+ type buried layer.

From the perspective of thermal theory and the current amplification factor of lateral transistors, it is possible to improve the carrier capture rate by interconnecting 6-1 and 6-2 with a conductor such as aluminum, thereby contributing to the improvement of the current amplification factor. , it's obvious.

Note that FIG. 3 is a schematic diagram of the semiconductor device of FIG. 2 viewed from above.

The emitter region is not limited to the embodiment shown in FIG. 3, but can be formed in various shapes such as a comb shape.

Of course, it is obvious that the shape of the emitter region can be formed as appropriate in the collector region as well.

The present invention uses the above-mentioned configuration to prevent parasitic phenomena occurring in semiconductor devices as much as possible, and also effectively captures carriers that conventionally do not participate in current amplification, thereby achieving high reliability. A lateral transistor is obtained.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a conventional lateral transistor, FIG. 2 is a sectional view of an embodiment of a semiconductor device according to the present invention, and FIG. 3 is a plan view of the embodiment of FIG. 1: P type semiconductor substrate, 2: N type semiconductor layer, 3: N+ type buried layer, 4: P+ type bone separation layer 5: Emitter region, 6: Collector region, 6-1.6-2: First and 2nd collector area, 7: base area.

Claims (1)

[Scope of utility model registration request] The N-type semiconductor layer provided on the P-type semiconductor layer is separated into a plurality of regions by a P-type separation layer, and an N+-type buried layer is provided under the separated N-type semiconductor layer, and the separated In a lateral transistor in which an emitter region, a collector region, and a base electrode extraction region are provided in an N-type semiconductor layer region, the lateral transistor has a multi-collector region consisting of two or more diffusion layers surrounding the emitter region. Ingredients,
A semiconductor device characterized in that the diffusion depth of the outer collector region is sequentially deeper than that of the inner collector region, so that the outermost collector region extends close to the buried layer.