JP3182175B2 - Darlington transistor and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Darlington transistor, and more particularly to a structure of a speed-up diode incorporated in a Darlington transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art FIG. 6 shows a speed-up diode (S).
FIG. 9 is a circuit diagram of a Darlington transistor incorporating UD). In a Darlington transistor, particularly a high-withstand-voltage Darlington transistor, it is necessary to incorporate a speed-up diode in order to remove minority carriers accumulated in the base region of the transistor at the subsequent stage at the time of turn-off in order to increase the speed.

FIG. 7 is a cross-sectional view of a conventional Darlington transistor having a built-in speed-up diode.
In the semiconductor substrate, an intori (N ⁻ ) layer 2 having a thickness of about 70 μm is formed on the N ⁺ layer 2 by epi growth or diffusion, and serves as a common collector region of the Darlington transistor. The back surface of the semiconductor substrate is a collector electrode 1 common to Darlington transistors. In the entry (N ⁻ ) layer 3, a preceding transistor 10 and a succeeding transistor 11 are formed. In each transistor, a P-type base region 4 is formed with a depth of about 20 μ and a surface concentration of about 10 ¹⁷ / cm ³ . And P
In the base region 4 of the N type, an N ⁺ type emitter region 6 is formed.
It is formed to a depth of about 5 μ.

The speed-up diode is formed at the same time as the emitter region 6 and has a depth of 3 μ and a surface concentration of 10 ²⁰ /.
cm ³ high concentration region 8 of N ⁺ type and high concentration region 8 of N ⁺ type
Is formed by a PN junction with a deep P ⁺ -type high concentration region 5 having a depth of 35 μm and a surface concentration of about 10 ²⁰ / cm ³ immediately below. The deep P ⁺ -type high-concentration region 5 is for preventing a parasitic NPN transistor operation (latch-up) due to the N ⁺ -type high-concentration region 8, the base region 4, and the entry (N ⁻ ) layer 3.

FIGS. 8 to 10 are cross-sectional views showing the steps of manufacturing a conventional Darlington transistor incorporating a speed-up diode. FIG. 8 shows an inventory on N ⁺ layer 2.
The P ⁺ -type high-concentration region 5 of the speed-up diode has just been formed on the semiconductor substrate on which the (N ⁻ ) layer 3 is formed. Next, FIG. 9 shows a state where the base region 4 is formed. FIG. 10 shows a state where the emitter region 6 has been formed. At the same time, an N ⁺ -type high-concentration region 8 serving as a speed-up diode is formed. Thereafter, the connection of the Darlington transistor, pads, and the like are formed by the electrodes 7, whereby the conventional Darlington transistor shown in FIG. 7 is completed.

[0006] However, in the prior art,
P just below the speed-up diode ⁺ High density area 8 of mold
When the depth is increased, the deepest base region
P⁺ From the bottom of the mold high concentration region 5^-)
A distance to the bottom of the layer 3 of about 35 μm is secured according to the withstand voltage.
There must be. Therefore, the transistor operation
From the bottom of the base region 4 below the emitter region 6
Entry (N^-) Distance to the bottom of layer 3 is more than necessary, 50 μm
Without speed-up diode
(35 μm) compared to the Darlington transistor
There is a problem that the current capacity is reduced.

[0007]

SUMMARY OF THE INVENTION In view of the above-mentioned problems in the prior art, the present invention provides a speed-up diode that does not reduce the current capacity of the Darlington transistor and does not cause a parasitic NPN transistor operation (latch-up). An object of the present invention is to provide a built-in Darlington transistor and a manufacturing method thereof.

[0008]

According to the Darlington transistor of the present invention, a P ⁺ -type high-concentration region having substantially the same depth as a base region is provided in a base region, and an N ⁺ -type region which is shallower than an emitter region is provided in the region. By forming the high-concentration region, a speed-up diode is formed.

[0009]

Since the speed-up diode is formed by a PN junction with the N ⁺ -type high-concentration region provided in the P ⁺ -type high-concentration region, the resistance corresponding to the base layer of the parasitic NPN transistor is low. No transistor operation (latch-up) occurs. Since the depth of the P ⁺ -type high-concentration region is almost the same as that of the base region, there is no P ⁺ -type high-concentration region deeper than the conventional base region.
The distance from the bottom of the base region to the bottom of the intori (N ⁻ ) layer can be shortened, and the same current capacity as that without the speed-up diode can be realized.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a speed-up of one embodiment of the present invention.
Cross section of Darlington transistor with built-in diode
FIG. N⁺ On layer 2, thickness 55μ, concentration 10¹⁴/
cm ^Three Intori (N^-) Semiconductor base on which layer 3 is formed
A board is used, and the back side of Darlington transistor
It is a collector electrode 1. This N⁺Layer 2 and int
Li (N^-3) Layer 3 is composed of the former transistor 10 and the latter transistor.
It becomes a common collector region of the transistor 11.

The preceding transistor 10 has a depth of 20 μm,
It is formed by a P-type base region 4 having a surface concentration of 10 ¹⁷ / cm ³ and an N ⁺ -type emitter region 6 having a depth of 5 μm and a surface concentration of 10 ²⁰ / cm ³ . Subsequent transistor 1
1 is also formed by a base region 4 having the same depth and concentration and an emitter region 6 having the same depth and concentration. In the speed-up diode, a P ⁺ -type high-concentration region 9 is provided in the base region of the transistor 11 at the subsequent stage, and N ^{+
A +} type high concentration region 8 is arranged, and a P ⁺ / N ⁺ junction forms a speed-up diode. Here, the depth of the P ⁺ region is 20 μm, and the surface concentration is 10 ¹⁹
/ Cm ^3, which is almost the same depth as the base region 4. The N ⁺ -type high-concentration region 8 is formed at the same time as the emitter region 6, but since the base is the P ⁺ -type high-concentration region 9,
The depth is shallower than the emitter region 6, about 2 μm, and the surface concentration is 10 ²⁰ / cm ³ .

The electrode 7 connects the base region 4 of the front-stage transistor 10 and the N ⁺ -type high-concentration region 8 of the speed-up diode of the rear-stage transistor 11. Also, an electrode serving as a base terminal B of the preceding transistor 10, an electrode serving as an emitter terminal E of the succeeding transistor 11, an emitter region 6 of the preceding transistor 10 and the succeeding transistor 11
The connection with the base region 4 is also formed by the electrode 7.

FIGS. 2 to 5 are cross-sectional views showing the steps of manufacturing a Darlington transistor according to an embodiment of the present invention. FIG.
A P-type region serving as a base region 4 having a depth of 10 in a semiconductor substrate having an entry (N ⁻ ) layer 3 on an N ⁺ layer 2.
It is formed by diffusion of about μ. At this time, no P-type region is formed in a portion to be a diffusion region of the speed-up diode.

FIG. 3 shows the P ^{+ of the} speed-up diode.
In this state, a P-type high-concentration impurity is deposited to form the high-concentration region 9. Fig. 2
In the base region of the subsequent transistor in which the P-type region is not formed.

FIG. 4 shows a state in which the base region 4 and the P ⁺ -type high-concentration region 9 of the speed-up diode have been formed by heat treatment. Here, the base region 4 and the P ⁺ -type high-concentration region 9 of the speed-up diode have substantially the same depth.

FIG. 5 shows a state in which the emitter region 6 and the N ⁺ region 8 of the speed-up diode are simultaneously formed by diffusion of N ⁺ type impurities. Emitter region 6 and N ⁺ region 8
In the case, the base P-type impurity is 10 ^{17 in the} base region.
/ Cm ³ , whereas in the P ⁺ region 9, 10 ¹⁹ / cm ³
Therefore, even if the same amount of high concentration N-type impurity is diffused, the emitter region 6 has a surface concentration of 10 ²⁰ / cm ³ and a depth of 5
μm, while the speed-up diode N
^{The +} region is as shallow as 10 ¹⁹ / cm ³ in surface concentration and 2 μm in depth.

Next, a metal such as aluminum is deposited on the electrode 7 to form a connection between the emitter and base electrodes and the preceding and succeeding transistors, thereby completing the Darlington transistor shown in FIG. According to the above steps, the number of mask steps is the same as that of the conventional technique, and the Darlington transistor of the present invention shown in FIG. 1 can be manufactured without complicating the steps.

In this Darlington transistor, since the P ⁺ -type high-concentration region 5 deeper than the conventional base region 4 is eliminated immediately below the speed-up diode, the speed-up diode has an indium (N ⁻ ) layer The distance to the bottom can be reduced from the conventional 50 μm to 35 μm. For this reason, the current capacity of the Darlington transistor can be increased to the same level as that without the speed-up diode. On the other hand, the N ⁺ -type high-concentration region 8 of the speed-up diode has a depth 2
The base resistance of the NPN parasitic transistor is sufficiently low because it is as shallow as μm and the lower portion is the P ⁺ type high concentration region 9. Therefore, the operation of the parasitic transistor due to the diffusion region of the speed-up diode can be suppressed as in the conventional case.

[0019]

As described above in detail, according to the present invention, a Darlington transistor with a built-in speed-up diode having a current capacity equivalent to that of a Darlington transistor without a speed-up diode can be used without causing parasitic transistor operation. It was realized. Further, by the manufacturing process of the present invention, the above-described Darlington transistor can be manufactured without increasing the number of mask steps as compared with the conventional one and without complicating the process.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view of a Darlington transistor according to one embodiment of the present invention.

FIG. 2 is a cross-sectional view of a manufacturing process of the Darlington transistor according to one embodiment of the present invention.

FIG. 3 is a cross-sectional view of a manufacturing process of the Darlington transistor according to one embodiment of the present invention.

FIG. 4 is a cross-sectional view of a manufacturing process of the Darlington transistor according to one embodiment of the present invention.

FIG. 5 is a cross-sectional view of a manufacturing step of the Darlington transistor according to one embodiment of the present invention.

FIG. 6 is a circuit diagram of a Darlington transistor incorporating a speed-up diode.

FIG. 7 is a cross-sectional view of a conventional Darlington transistor.

FIG. 8 is a cross-sectional view of a manufacturing process of a conventional Darlington transistor.

FIG. 9 is a cross-sectional view of a manufacturing process of a conventional Darlington transistor.

FIG. 10 is a cross-sectional view of a conventional Darlington transistor manufacturing process.

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/8222-21/8228 H01L 27 / 06,27 / 08,27 / 082

Claims (2)

(57) [Claims] In a Darlington transistor in which a speed-up diode is formed by providing a diffusion region in a base region of a transistor in a subsequent stage, the diffusion region of the speed-up diode has a depth substantially equal to that of the base region. Of the same conductivity type ,
A Darlington transistor, comprising: a region having a higher concentration than a base region; and a high concentration region provided in the high concentration region and having a shallower depth than the emitter region and the same conductivity type as the emitter region. A step of forming base regions of the transistors in the preceding and subsequent stages except for a diffusion region of the speed-up diode; and depositing a high-concentration impurity of the same conductivity type as the base region in the diffusion region of the speed-up diode. Forming the high-concentration impurity by heat treatment in a region having a higher concentration than the base region at substantially the same depth as the base region; and a high-concentration region having a conductivity type opposite to the base region. Forming a shallower than the emitter region in a high-concentration region of the same conductivity type as the base region.