JPH118252A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a diffusion layer parasitic capacity from increasing by forming a P-type diffusion layer that also plays a role of the side surface collector region of a vertical PNP transistor by forming a vertical groove through etching and by performing filling with a polycrystalline silicon layer, including a diffusion impurity for decreasing resistance. SOLUTION: A P-type diffused layer 3' of the entire portion of the surrounding part of the side surface collector region of a vertical PNP transistor is formed by performing the vertical groove etching of an N-type epitaxial layer 2 until a P-type embedded layer 3 is reached and further filling a polycrystalline silicon 23 whose resistance is decreased containing the P-type diffusion impurity. Therefore, the diffusion spread in the horizontal direction is determined less by the width of a groove 20 formed by the vertical groove etching, as compared with a case when a side surface collector region is formed due to thermal diffusion, thus suppressing the increase in the diffusion layer parasitic capacity of the side surface collector and improving the cut-off frequency of the vertical PNP transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement in a method of manufacturing a semiconductor device including a bipolar transistor having a high cutoff frequency, and more particularly to a vertical PNP transistor.

[0002]

2. Description of the Related Art In general, it is difficult to configure an analog circuit using a bipolar element only with an NPN transistor. In consideration of the output signal DC level or the dynamic range of the circuit, a PNP transistor is used. Due to the configuration, there is a need to use it in a level shift, an output amplifier section, and the like.

However, when such an analog circuit is formed into an IC, the above-mentioned PNP transistor is usually formed as a lateral type, so that the element size is large and the parasitic capacitance is large, and the frequency response is higher than that of the vertical type NPN transistor. , The so-called cutoff frequency f _T is 1/10 or less of that of the NPN transistor. As a result, the output frequency characteristic of the entire analog circuit becomes the cutoff frequency f _T
, Which is determined by the PNP transistor having a low threshold voltage.

In order to improve the cutoff frequency of the PNP transistor, a vertical structure may be used similarly to the NPN transistor. Hereinafter, a conventional example of the method of manufacturing the vertical PNP transistor will be described in order with reference to FIG. That is, as shown in FIG. 2A, an N-type buried layer 4 for bottom-side device isolation and a P-type buried layer 3 also serving as a bottom collector region of a vertical PNP transistor are formed in a P-type silicon substrate 1.
The thermal silicon oxide film formation, photoetching, thermal diffusion, and the like are repeated, and the thermal silicon oxide film is removed. Then, the N-type epitaxial layer 2 is formed.

Subsequently, in FIG. 2 (b), a P-type diffusion layer 3 'for element isolation and a side collector region is formed from the front side,
N-type well layer 5 serving as a base region of NP transistor
(FIG. 2 (c)). Further, a P + diffusion layer 33 serving as an emitter region and an N + diffusion layer 44 serving as a base electrode take-out are similarly formed (FIG. 2 (d)). Photoetching of the silicon oxide film 10 is performed, and an A1 electrode 8 for each terminal is formed by A1 film formation and photoetching, thereby completing a vertical PNP transistor as shown in FIG.

[0006]

By the way, it can be understood that the method of manufacturing a vertical PNP transistor according to the conventional method shown here has the following disadvantages.

First, as described above, in order to improve the cutoff frequency f _T of the PNP transistor, it is necessary to adopt a vertical structure. Further, the cut-off frequency f _{T of the} transistor is calculated from the relational expression (1) shown below from the collector-base time constant 1 / ωc and the time constant 1 / ω of the substrate storage capacitance.
It can be seen that improvement is achieved by reducing s (integrated circuit term).

1 / (2πf _T ) = 1 / ωe + 1 / ωb + 1 / ωd + 1 / ωc + 1 / ωs (1) where 1 / ωe: base-emitter time constant 1 / ωb: base transfer time constant 1 / ωd: collector Base Space Charge Layer Time Constant Here, in order to reduce the above time constants, it is necessary to reduce the collector resistance according to the following relational expressions (2) and (3).

[0009] _{1 / ωc = C CB R CC} ... (2) 1 / ωs = C CS R CC ... (3) where, C _CB: capacity of the reverse biased base-collector junction C _CS: reverse-biased substrate The collector junction capacitance R _CC : collector resistance However, the P-type diffusion layer 3 ′, which also serves as a side collector region for forming the collector region, is a P-type diffusion layer in order to reduce the resistance as long as it is formed by thermal diffusion. 3 'has a wider width and a deeper diffusion depth. Therefore, on the contrary, the parasitic capacitance of the diffusion layer increases and the time constant cannot be reduced.
Improvement of the cutoff frequency f _T is difficult. Also, vertical PNP
The base and emitter regions formed inside the collector region of the transistor are P-type diffusion layers 3 'also serving as side collector regions.
Is spread to the inside due to thermal diffusion, so that it is necessary to increase the area around the collector, which hinders the overall reduction in size of the transistor.

An object of the present invention is to reduce the resistance of the P-type diffusion layer also serving as the side collector region for improving the cut-off frequency f _T of the vertical PNP transistor, thereby preventing an increase in the diffusion layer parasitic capacitance. is there.

[0011]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides a vertical PNP transistor having a P-type diffusion layer which also serves as a side collector region by forming a vertical groove by etching and reducing the resistance. Buried in a polycrystalline silicon layer containing the diffusion impurity of the above.

According to the present invention, the P-type diffusion layer in the entire periphery of the side face collector region of the vertical PNP transistor is subjected to vertical groove etching until the N-type epitaxial layer reaches the P-type buried layer, and the low-level diffusion containing P-type diffusion impurities is further performed. It is formed by burying polycrystalline silicon having resistance. For this reason, compared to the case where the side surface collector region is formed by thermal diffusion, the lateral diffusion spread is determined by the groove width formed by the vertical groove etching, and is reduced. Therefore, the parasitic capacitance of the side collector region formed according to the present invention is reduced as compared with the conventional thermal diffusion method.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to FIG. FIG. 1A is the same as FIG. 2A of the conventional example.

Subsequently, in FIG. 1B, a P-type diffusion layer 3 'for element isolation and a side face collector region is formed from the front side,
N-type well layer 5 serving as a base region of NP transistor
Are similarly formed. (FIG. 1C) Further, a P + diffusion layer 33 serving as an emitter region and an N + diffusion layer 44 serving as a base electrode extraction are formed in the same manner (FIG. 1D). Etching is performed, and an A1 electrode 8 for each terminal is formed by A1 film formation and photoetching to complete a vertical PNP transistor as shown in FIG. 1 (e).

[0015]

As described above, according to the present invention, a P-type diffusion layer also serving as a side collector region of a vertical PNP transistor is formed, and an N-type epitaxial layer is subjected to vertical groove etching to contain a P-type diffusion impurity. Since the side collector region is buried with crystalline silicon, the side collector region can be reduced in resistance without increasing its width and diffusion depth.

As a result, the increase in the parasitic capacitance of the diffusion layer in the side collector region is suppressed, and the cutoff frequency f _T of the vertical PNP transistor can be further improved. Further, since the peripheral region of the side collector is less likely to expand inward than in the case of thermal diffusion, it can contribute to the miniaturization of the transistor.

[Brief description of the drawings]

FIG. 1 is a sectional view of a method for manufacturing a vertical PNP transistor according to the present invention.

FIG. 2 is a cross-sectional view of a conventional method for manufacturing a vertical PNP transistor.

[Explanation of symbols]

1: P-type silicon substrate, 2: N-type epitaxial layer, 2
0: etched vertical groove, 23: polycrystalline silicon, 3: P-type buried layer, 3 ': P-type diffusion layer, 33: P + diffusion layer (P-type high concentration layer), 4: N-type buried layer, 44: N + Diffusion layer (N
5: N-type well layer, 8: Al electrode, 1
0: Silicon oxide film.

Claims (1)

[Claims] 1. A first buried diffusion region of the other conductivity type is formed on a semiconductor substrate of one conductivity type, a second buried diffusion region of one conductivity type is formed, and then an epitaxial layer is formed. Forming a diffusion layer of the semiconductor substrate, the semiconductor substrate is etched in advance, and a polycrystalline semiconductor is buried in the semiconductor substrate.