JPH02105456A - Semiconductor device - Google Patents

Abstract

PURPOSE:To be provided with a bipolar random-access memory cell which has suppressed an emitter region and a spread of a lateral pnp transistor by a method wherein an impurity diffusion region is formed of the following: a highly doped buried polycrystalline layer whose one side face completely comes into contact with a dielectric insulating layer; a high-concentration impurity region which is formed by thermal diffusion from the polycrystalline silicon layer and is situated near the surface of the polycrystalline silicon layer. CONSTITUTION:An N<+> type buried layer C1 and an N<-> type semiconductor layer C2 are formed individually on a P-type semiconductor substrate S inside an element partitioned by dielectric insulating layers I2 for element isolation use; in addition, an emitter region E0 and a base region B for an NPN transistor are formed on the surface. A high-concentration impurity diffusion region E1 forming an emitter region for a lateral PNP transistor is formed to be adjacent to the base region B of the NPN transistor so as to surround a wall face of a P-type highly doped polycrystalline silicon layer P1; D1 to D4 are formed as their respective extraction electrodes.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having a bipolar transistor as a basic element.

[Conventional technology]

Bipolar random access memory device (hereinafter referred to as B
IP-RAM) is often used in devices that require high-speed operation, but today it is using cross-coupled pnpn memory cells with an NPN transistor flip-flop configuration loaded with PNP transistors. It has become mainstream. This is because it has the highest degree of integration.

, 4 and 5 are respectively an equivalent circuit diagram of a conventional cross-coupled pnpn memory cell and a sectional view of a semiconductor device showing the element structure on one side thereof. In FIG. 5, the cell element has an N+ type buried semiconductor layer C1 with a high impurity concentration formed on a P type semiconductor substrate S and a relatively low concentration N− type semiconductor layer C2 thereon as a collector region. The base region B and emitter region Eo formed on the surface constitute an NPN)-transistor, and the P<0> type impurity diffusion region E1 on the surface of the N-type semiconductor layer C2 serves as the emitter region of a lateral PNP transistor. It has become. Here, C5 is connected to the N+ type buried semiconductor layer C1 and the N− type semiconductor layer 02 region in the collector region.
! This is a heavily doped N+ type impurity diffusion region provided to connect with Dt with low resistance.

In the structure of this cell element, the high concentration impurity diffusion layer E1 for the emitter and the high concentration diffusion layer MC3 for leading out the collector electrode of the lateral PNP transistor provided adjacent to the dielectric insulation technology 2 are each formed with a high concentration (~ 1020
c+t+-3) and deep distance from the surface! (0.5~1μ
It is necessary to dope the impurity up to about m). However, in the commonly used thermal diffusion method or ion implantation method, in either case, doping deeply from the surface increases diffusion in the lateral direction with respect to the mask pattern. For example, if an opening for leading out an electrode is provided on the insulating protective film I using a mask pattern, the diffusion in the lateral direction parallel to the semiconductor surface becomes large as Xl + X2. Therefore, a mask pattern margin is required that takes the diffusion distances X, , X2 into consideration in advance, which hinders high integration.

Conventionally, in order to minimize the influence of this lateral diffusion margin, the high-concentration impurity diffusion layers E1 and C5 are each formed using a dielectric insulation layer for element isolation surrounding the outer periphery of the element.
The insulating layer I2 is disposed so as to be in contact with the insulating layer I2, and measures are taken to prevent lateral diffusion in one direction by the wall of the insulating layer I2.

[Problem to be solved by the invention]

As described above, in the conventional B i p -RAM cell element described above, the high concentration impurity diffusion regions E and C3 for the emitter region and collector electrode extraction of the lateral PNP transistor are masked to determine the regions.・Large diffusion in the lateral direction parallel to the substrate surface with respect to the pattern (
0.5 to 1 μm), it is necessary to estimate a margin in consideration of this spread in the device area, which causes a big problem in reducing the cell area for higher integration.

In addition, this large element area is due to the parasitic capacitance N Cc between the buried collector and the substrate, as shown in the equivalent circuit diagram of FIG.
Increasing s becomes a major cause of slowing down the operating speed of the circuit.Furthermore, due to the expansion of the emitter diffusion region E1 of the lateral PNP transistor, the junction area between the base and emitter increases, increasing the junction capacitance Ceb in this area. At the same time, variations in the diffusion distance reduce the transistor's amplification factor h'
. This has a large impact on the device characteristics and makes the device characteristics unstable.

In view of the above problems, an object of the present invention is to
An object of the present invention is to provide a semiconductor device including an emitter region of a transistor and a bipolar random access memory cell with suppressed expansion.

[Means to solve the problem]

According to the present invention, a semiconductor device in which an N-type or P-type impurity diffusion region is formed adjacent to a dielectric insulating layer for element isolation that isolates semiconductor elements formed on a surface of a semiconductor substrate from each other, The diffusion region is defined as ``a highly doped buried polycrystalline silicon layer whose one side is completely in contact with the dielectric insulating layer, and a highly concentrated impurity near the surface of the polycrystalline silicon layer formed by thermal diffusion from the polycrystalline silicon layer. It is configured by forming a region.

〔Example〕

FIG. 1 is a cross-coupled pn showing an embodiment of the present invention.
1 is a cross-sectional view of a semiconductor device showing the element structure on one side of a pn memory cell. FIG. According to this embodiment, the semiconductor device of the present invention has an N+ type buried layer C1 and an N
- type semiconductor layers C2 are respectively formed, and furthermore, an emitter region E of an NPN transistor is formed on the surface thereof. and base region B are formed. Also, a high concentration impurity diffusion region E forming the emitter region of the lateral PNP transistor.
1 is formed adjacent to the base region B of the NPN transistor so as to surround the wall surface of the P-type cavity doped polycrystalline silicon layer P1, and D1 to D4 are provided as respective extraction electrodes. The impurity diffusion region E1 for the emitter region of this lateral PNP transistor is a polycrystalline silicon layer P1 doped with a P-type impurity such as boron at a high concentration, which is formed directly under the extraction electrode D4 formed to the minimum necessary size. It can be formed by impurity diffusion (50.18 m) without a small amount of debris. In this way,
Dielectric insulation N r 2 for element isolation and polycrystalline silicon layer P
An unnecessary impurity diffusion region E1 for the emitter region is not formed in the region between 1 and 1, and impurities hardly need to be diffused into the insulating layer such as silicon oxide.

FIGS. 2(a) and 2(b) show the lateral P of the semiconductor device of the present invention.
In the process diagram for forming the emitter region of an NP transistor, the formation of highly doped polycrystalline silicon P for the buried electrode is as follows:
First, as shown in FIG. 2(a), this is performed before forming the dielectric insulation layer I2 for element isolation. That is, vertical trench etching is first performed on the substrate S, and then a polycrystalline silicon layer P1 doped with a P-type impurity at a high concentration is buried in this trench. Next, as shown in FIG. 2(b), a full 1° area for the element isolation dielectric insulating layer I2 is dug so as to include a part of the polycrystalline silicon layer P1 that is not buried. Insulating material is buried. The remaining polycrystalline silicon layer P becomes an impurity diffusion source with the minimum required size in contact with the insulator, so heat treatment at a temperature of 950°C for about 30 minutes will diffuse the impurity into the emitter. A region E is formed. In the emitter diffusion region having the above structure, the impurity diffusion distance X1 in the lateral direction parallel to the surface is minimized, so there is no need to take this margin into the cell area. Therefore, the collector-substrate capacitance CC5 becomes smaller, and at the same time, the emitter-collector capacitance ic eb of the PNP transistor also becomes smaller as the diffusion region is reduced.

Furthermore, since at least one surface of this diffusion region E is formed so as to be in contact with the dielectric insulating layer 2 for element isolation, no junction capacitance is formed in that portion, and it is slightly smaller than the junction by approximately 1.
A stray capacitance Cso that is two orders of magnitude smaller is simply created between the insulating layer (2). Therefore, the switching operation of the transistor cell becomes even faster.

FIG. 3 shows a cross-coupled p
1 is a cross-sectional view of a semiconductor device showing the element structure on one side of an npn memory cell. FIG. In this example, an N+ type impurity diffusion head region C9 for leading out the collector region of an NPN transistor is formed using the same method as in the previous example. teeth,
N-type impurities such as arsenic or phosphorus are used. At this time, the impurity-doped polycrystalline silicon layer has approximately 1000
℃ for several tens of minutes, the resistance becomes sufficiently low to the same level as the N+ buried layer C1, but the impurity diffusion path M in the lateral direction
X2 is small and hardly diffuses, so a margin for this spread is almost unnecessary, the cell area can be reduced, and the collector-substrate volume jiccs can also be reduced.

Although the case where the present invention is implemented in a cross-coupled pnpn memory cell has been described above, the present invention can be easily implemented in any element having a structure in which the impurity diffusion region is in contact with a dielectric insulating layer for element isolation.

〔Effect of the invention〕

As described in detail above, according to the present invention, the impurity diffusion region of, for example, a memory cell element formed in contact with a dielectric insulating layer for element isolation is a buried low-resistance conductor layer.
Since it consists of a small impurity diffusion region formed around it using this as a diffusion source, it is possible to significantly suppress the spread of the impurity diffusion layer in the lateral direction horizontal to the semiconductor surface, regardless of the depth of the diffusion region. can. Therefore, this expansion does not need to be included in the element area as a margin, so 1.
The device area can be reduced and the device can be highly integrated. Furthermore, since the reduction in element area also reduces the junction capacitance in the buried collector/substrate and the junction area formed around the impurity diffusion region, it is possible to increase the switching speed and circuit operation of the device.

[Brief explanation of the drawing]

FIG. 1 is a cross-coupled pn showing an embodiment of the present invention.
A cross-sectional view of a semiconductor device showing the element structure on one side of a pn memory cell, FIGS. 2(a) and 2(b) are process diagrams for forming the emitter region of a lateral PNP transistor of the semiconductor device of the present invention, and FIG. A cross-sectional view of a semiconductor device showing an element structure on one side of a cross-coupled pnpn memory cell showing another embodiment of the present invention, FIGS. 4 and 5 are equivalent to a conventional cross-coupled pnpn memory cell, respectively. FIG. 2 is a cross-sectional view of a semiconductor device showing a circuit diagram and an element structure on one side thereof. S...P type semiconductor substrate, C1...N+ type buried semiconductor layer, C2...N- type semiconductor layer, C3...N+ type impurity diffusion region, B...NPN)-base region of transistor, Eo...NPN) Emitter region of transistor, E
l... High concentration impurity diffusion region forming the emitter region of the PNPh transistor, Pl... P-type cavity doped polycrystalline silicon layer, ■1... Insulating protective film, ■2... Dielectric material for element isolation Insulating layer, D1 to D4... Leading electrode, X,
, X2...Diffusion distance. X2 Hirototo distance Figure 3 Figure 2

Claims (1)

[Claims] An N type or P
In a semiconductor device in which a type of impurity diffusion region is formed, the impurity diffusion region is formed by thermal diffusion from a highly doped buried polycrystalline silicon layer that completely contacts one side surface of the dielectric insulating layer and the polycrystalline silicon layer. 1. A semiconductor device comprising a high concentration impurity region near the surface of a polycrystalline silicon layer to be formed.