JPH02231726A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform a high speed switching by using materials having the different qualities in the active base region and in the inactive base region of a transistor. CONSTITUTION:An embedded layer 2 is selectively formed in a silicon substrate 1. An epitaxial growth layer 3 is grown. A ground oxide film 4 is formed by thermal oxidation. A nitride film 5 is further formed. A region which is to become an element is made to remain, and the ground oxide film 4 and the nitride film 5 are removed. An insulating isolation oxide film 6 is formed. Then, a collector lead-out electrode 7 and a first polysilicon film 8 are formed. Thereafter, a CVD oxide film 9 is formed. A PSG film 11 is formed. The epitaxial growth layer 3 is etched. Heat treatment is performed in N2 atmosphere, and an outer base layer 16 is formed. A silicon epitaxial layer 13 is further formed and activated. Thereafter, base and collector electrodes 14 and an aluminum electrode 15 is formed. Thus, high speed switching operation can be performed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device with shallow junctions,
The present invention relates to a bipolar semiconductor integrated circuit device suitable for high-speed switching operation.

[Conventional technology]

In recent years, due to advances in lithography technology, bipolar transistors that perform high-speed switching operations have been designed using the 1.0 μm rule, and the emitter-base gap has also been formed using self-7-line technology that is unaffected by lithography technology, resulting in a reduction in emitter width. As a result, it is becoming possible to effectively create objects with a diameter of 0.5 μm or less. Furthermore, in order to increase speed, it is necessary not only to reduce the size in the horizontal direction, but also to make each joint shallower in the vertical direction. There is a problem with the punch-through between the emitter and collector when reducing the width, and there is a limit to the width reduction. A countermeasure against this is to increase the base concentration, but if it is increased, the injection efficiency from the emitter will decrease and the amplification effect will no longer occur. Therefore, as a method to solve this problem, a hetero-U junction bipolar transistor (hereinafter referred to as HBT), which uses materials with different bandwidths for the emitter, base, or both, is being researched. By the way, considering the compatibility with the current process using silicon, it is desirable to use a wide bandgap material for the emitter or a material with a narrow bandgap and belonging to the same group 4 as silicon for the base. . Furthermore, considering future transistor scaling (horizontal direction), it is considered desirable to use a narrow bandgap material as the base.

[Problem to be solved by the invention]

As mentioned above, it is considered optimal for the HBT material and structure to use a narrow bandgap material, particularly a mixed crystal of silicon and germanium, for the base. However, if a transistor made of a different material is used as a base and the transistor is scaled down in the horizontal direction, it becomes necessary to adopt a self-line structure in a narrow bandgap HBT. However, there was no effective method for forming the lead-out electrode of the base portion.

[Means to solve the problem]

A semiconductor integrated circuit device of the present invention includes a first island-like region made of an epitaxial growth layer of a first conductivity type separated on a diffusion layer and selectively buried in a silicon substrate; a second conductivity type second island region having a thickness of 500λ or less and made of a mixed crystal of silicon and germanium selectively formed within the island region; A third conductive type third conductivity type formed in contact with the second island-like region, has a depth equal to or greater than the second island-like region, and is located within the first island-like region. an island-like region and a second
A fourth island-like region of the first conductivity type, which has an area equal to or smaller than the second island-like region and whose main component is silicon and which forms a pn junction with the second island-like region, is formed on the island-like region. have

According to the present invention, a new proposal is made regarding a method for drawing out the base part in a cerephaline structure of a narrow bandgap HBT, and the active base region and the inactive base region of the transistor are made of different materials,
A semiconductor integrated circuit device is obtained in which these are connected by a self-line.

〔Example〕

In order to better understand the present invention, the present invention will now be described with reference to examples.

FIGS. 1(a) to 1(e) are cross-sectional views of the main steps of the first embodiment of the present invention. First, as shown in FIG. 1(a), a buried layer 2 is selectively formed in a silicon substrate 1 through an As-doped silicon film coating and indentation diffusion process. moreover,
An epitaxial growth layer 3 is grown to a thickness of 1.0 μm, and an underlying oxide film 4 with a thickness of 500 μm is formed thereon by thermal oxidation. Furthermore, a nitride film 5 with a thickness of 1000 is formed,
Using photolithography technology, the underlying oxide film 4 and the nitride film 5 are removed, leaving a region that will become an element in the future, and then an insulating isolation oxide film 6 is formed to a thickness of about 1.2 μm. Next, as shown in FIG. 1(b), a collector lead-out electrode 7 is formed by thermal diffusion, and a first polysilicon film 8 doped with 3000 ml of poron is formed, which will become the base lead-out electrode in the future. do. Thereafter, a CVD oxide film 9 with a thickness of 3,000 wafers is formed as a cover by a CVD growth method.

Furthermore, as shown in Fig. 1(c), the future emitter electrode,
The first polysilicon film 8 and CVD oxide film 9 are etched by photolithography at the location where the active base region is to be formed to form an opening, and a BSG is formed to insulate and separate the base extraction electrode polysilicon film and the emitter electrode polysilicon film. Film thickness 3000
The BSG film is attached by hand, and then etched by RIE method so as to leave the BSG film on the side wall of the opening.
A G film 11 is formed. Furthermore, the opening with the BSG film 11 left on the side wall is used to form an epitaxial growth layer 3 in a region where a mixed crystal of silicon and germanium will be grown in the future using the RIE method.
The outer base layer 16 was formed by etching to a depth of 400 mm and then heat-treating in nitrogen.

Next, as shown in FIG. 1(d), a mixed crystal of silicon and germanium doped with 1019/d of poron (silicon: germanium = 7:3 mixed crystal) is selectively grown, and then As is grown on top of it. A silicon epitaxial layer 13 doped with 10H/d is grown, and lamp annealed, 9
Activate at 00℃ for 10 seconds. Thereafter, the base and collector electrodes 14 are formed by photolithography. Further, as shown in FIG. 1(e), an aluminum electrode 15 is formed to complete the transistor of the present invention.

FIGS. 2(a) to 2(e) are cross-sectional views of the main steps of the second embodiment of the present invention. In FIG. 2(a), in the same manner as in FIG. 1(a), a buried layer 22 is selectively formed on a silicon substrate 21, followed by an epitaxial layer 23, and selectively formed as a transistor. This is where an insulating isolation oxide film 26 is formed so as to leave the element region.

Furthermore, as shown in FIG. 2(b), the collector extraction electrode 2
7. First polysilicon film 28 doped with boron, CV
A D oxide film 29 is formed, and then heat treated in an N2 atmosphere, and the first polysilicon film 28 and CVD oxide film 29, which will become an external base region in the future, are etched by the RIE method to form an opening in the same manner as in the first embodiment. A CVDSiOz film 31 for emitter-base separation is left on the side wall of the opening by RIE, and then the P+ diffusion layer 31 diffused in FIG. 2(b) is etched by RIE only at the opening. After that, the first
In the same manner as in the embodiment, a silicon-germanium mixed crystal 32 and an As-doped silicon epitaxial layer 33 are formed.
A contact 34 is opened, and an aluminum electrode 35 is formed as shown in FIG. 2(e), thereby completing the transistor of this example.

〔Effect of the invention〕

As described above, by using the present invention, it is possible to provide a fine and high-speed switching transistor in which an emitter-based pn junction can be formed with a cerephaline structure, which can be easily adapted to a conventional silicon process. In this example, the ratio of silicon and germanium mixed crystal was silicon:germanium = 7:3, but by changing this ratio, the state of the band gap on the base side was changed, and the rise voltage (V ,) low transistor,
In other words, a transistor suitable for scaling in the horizontal direction can also be provided.

... Contact, 15.35 ... Aluminum electrode.

Claims (1)

[Claims] A first conductivity type silicon layer provided on a diffusion layer selectively buried in a silicon substrate and insulated from the silicon layer.
a second island region of a second conductivity type made of a mixed crystal of silicon and germanium selectively formed in the first island region; of the second conductivity type that surrounds and is in contact with the second island-like region, has a depth equal to or greater than the second island-like region, and is located within the first island-like region. a third island-like region made of silicon; and a third island-like region of the first conductivity type mainly composed of silicon, which is in contact with the second island-like region and forms a pn junction with the second island-like region. 1. A semiconductor integrated circuit device having four island-like regions.