JPS61285764A - Semiconductor device characterized by high withstand voltage - Google Patents

Abstract

PURPOSE:To decrease the parasitic capacity of a semiconductor layer directly beneath a bonding pad, by providing an electrode taking out metal film at least at the upper of an innermost field limiting ring, and forming an active semiconductor region at a place shallower than the field limiting ring. CONSTITUTION:A part of an inner field limiting ring (FLR) 50a is protruded to the inner side. At the upper part of this part, bonding pads 46a and 47a are formed through an insulating film 45. The FLR 50a is formed as an island region independent of a p-type semiconductor layer 43 and not connected to the bonding pads 46a and 47a electrically. Therefore, the collector-base junction capacity becomes small, and the switching speed becomes high. The same bias as that for the base is applied to the bonding pads formed on the FLR 50a. Therefore, the pads operate as field plates, and reliability is improved. The bonding pads are not extended to outermost FLR 50b so that the pads are operated as the field plates.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention forms a plurality of active semiconductor regions in a semiconductor substrate,
The present invention relates to a semiconductor device in which an electrode lead metal film connected to an active semiconductor region consisting of an active semiconductor region is formed on the main surface of a semiconductor substrate via an insulating film, and a wire conductor is connected to the electrode lead metal film by bonding. In particular, in high-voltage semiconductor devices in which a field limiting ring is formed surrounding an active semiconductor region in order to achieve high breakdown voltage, switching speed is improved by reducing parasitic capacitance, and the frequency is increased. This relates to technology for improving characteristics.

(Conventional technology) In recent years, improvements in microfabrication technology have allowed devices to be miniaturized to near their limits, resulting in the emergence of high-speed, high-performance semiconductor devices or semiconductor integrated circuits that reduce the parasitic capacitance of devices. ing. However, not everything can be miniaturized; there are some parts where miniaturization is possible and some parts where it is not.

Particularly in high-power transistors, the current capacity is large, so thick wires are used to take out the electrodes, and along with this, there is a wide flat film pattern called a bonding pad that is connected to the wire.
For high power devices, this bonding band requires a large area. Generally, the semiconductor region immediately below the bonding pad is a region to which the same bias is applied as the base region in a bipolar transistor and the source region in a MOS transistor.

FIG. 4 shows the structure of a conventional high-voltage semiconductor device in which a bipolar transistor is formed. FIG. 4 (a) is a diagrammatic plan view, and FIG. FIG. Two bonding bands for a base region and an emitter region are formed on the silicon chip. An n-type silicon epitaxial layer 2 is grown on an n3-type silicon semiconductor substrate 1 to form a silicon substrate having an n-on n' structure. In the epitaxial layer 2, a p-type semiconductor layer 3 is formed which acts as a base region which is an active semiconductor region, and within this p-type semiconductor layer there is formed an n+ type thick conductor layer 4 which acts as an emitter region which is an active semiconductor region. is forming. An insulating film 5 is formed on the main surface of the epitaxial layer N2, and the n
°-type half body layer 4 ohmically connected emitter 11 electrode film 6 is extended over insulating film 5 to form a large-area bonding pad 6a, to which wire conductor 8 is connected by bonding. . Further, the base An electrode film 7, which is ohmically connected to the p-type semiconductor layer 3 through another opening 5b made in the insulating film 5, is also extended on the insulating film 5 to constitute a bonding pad 7a, and a wire is connected here. The conductor VA9 is connected by bonding.

In addition, in FIG. 4, a field lifting ring (hereinafter abbreviated as FLR) 10a consisting of two p-type semiconductor layers surrounds the bipolar transistor.
10b is formed to achieve high voltage resistance.

Conventional MOS transistors were thought to be low-voltage, low-power devices, but with recent developments in semiconductor manufacturing technology and circuit design technology, high-voltage and high-power designs have become possible, and they are now being used as power devices. The position has been secured.

A typical example of such a power MOS transistor is DSA (Diffusion Self-Alig).
There are some with nment) structure. DSA-MOS) transistors have a channel region formed in a self-aligned manner by double diffusion, and a p-carved structure is used to form the channel region by the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon electrode. It is characterized in that it performs diffusion of impurities and diffusion of n+ type impurities to form the source region.

FIG. 5 shows the structure of a conventional high-voltage semiconductor device in which a DSA-MOS transistor is formed, and FIG. 6(a) is a plan view showing the cell structure with the Al electrode film etc. removed. , FIG. 6(b) is a sectional view taken along the line A-AvA in FIG. 6(a). It has an n-on-n9 structure in which an n-type epitaxial layer 12 with a lower impurity concentration is formed on a semiconductor substrate 11, and these constitute a drain region. Although the drain electrode is not shown in the drawing, it is formed on the back surface of the semiconductor substrate 11. A gate polycrystalline silicon film 14 is formed on the epitaxial layer 12 via a gate oxide film 13, and an opening is formed in this polycrystalline silicon film 14 to form a so-called cell. In the epitaxial layer 12, a p-type trench conductor layer 15, a p-type semiconductor layer 16, and an n+-type ring conductor layer 17 are formed. Since the channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 16 and the n+ type ring conductor layer 17, an extremely short channel region with a channel length of several microns or less can be formed. The source metal electrode film 18 is ohmically connected to both the n-type hot conductor layer 17 and the p-type groove conductor layer 15 in contact with the p-type semiconductor layer 16. Further, the gate electrode metal film 19 is connected to the polycrystalline silicon film 14. These source and gate electrode metal films 18 and 1
Reference numeral 9 extends over the insulating film 20 to constitute large-area bonding pads 18a and 19a, to which wire conductors vA21 and 22 are bonded and connected, respectively.

Here, the first p'' located in the p+ type trench conductor layer 15 cell
type semiconductor layer 15a, and a second p'' type semiconductor layer 15b located so as to surround a cell aggregation region formed by aggregation of cells.
, an FLR 15c consisting of a third p+ type semiconductor layer provided to further surround the second p+ type semiconductor layer 15b in order to increase the source-drain breakdown voltage (Vnss), and a bonding pad 1 for the source region and gate region.
A fourth p-type semiconductor layer 15d and a fifth p-type semiconductor layer 15d and a fifth
A p'' type semiconductor layer 15e is formed together in the same process step.

The pattern of the gate polycrystalline silicon film 13 may be a lattice pattern or a stripe pattern, and FIG. 6(a) shows a lattice pattern. When a positive voltage is applied between the gate and the source to turn on the channel, current flows vertically from the semiconductor substrate 11, passes through the channel region, and flows into the source region. Therefore, in order to take out this current, a bonding pad 18a, which is generally made of Al and has a large area, is formed, and the wire conductor 21 is drawn out from this bonding pad. The source electrode 18 is
A first p" type semiconductor layer 15a located in an opening formed in the gate polycrystalline silicon film 14 called a cell, and a second p" type semiconductor layer 15a surrounding the aggregate formed by the cells.
type semiconductor layer 15b and the fourth. It is electrically connected to the fifth semiconductor layers 15d and 15e. Therefore, the fifth P3 type semiconductor layer 15d directly under the bonding pad 19a of the gate electrode also has the same potential as the source region.

(Problems to be Solved by the Invention) In the high voltage semiconductor device configured as described above, one factor for improving the switching speed of the MOS transistor is to reduce the source-drain junction capacitance. In order to reduce this source-drain junction capacitance, it is important to keep the impurity concentration in the source region low, and also to keep the capacitance of the source region that occupies the limited silicon chip as small as possible. On the other hand, in planar type transistors for high power and high withstand voltage,
Impurity diffusion to a certain depth (in bipolar transistors, this is diffusion to form the base region 3, and in MOS
) In transistors, it is difficult to obtain a transistor with a high withstand voltage and a wide safe operation area unless diffusion (diffusion for forming the p+ type hot conductor layer 15) is performed.

Naturally, in a DSA-MOS transistor, forming the p° type thick conductor layer 15 deeply increases the volume of the source region. Moreover, the p" type semiconductor layers 15d and 15e directly under the bonding pads have a large area compared to other regions.

For example, when using a wire conductor with a diameter of 300 μm, 70
It has an area of 0 x 1500μIll''.

As described above, in a conventional semiconductor device, there is a semiconductor layer having a large volume and a vast area directly under the bonding pad, and there is a semiconductor layer that has a large volume and a vast area, and the area between the source and the drain or the collector of this part is This has the drawback that the parasitic capacitance between the bases becomes significantly large and the switching speed decreases.

Furthermore, in conventional semiconductor devices, in order to achieve a high breakdown voltage, the base region and the diffusion layer of the FLR, which are formed simultaneously, need to have a radius of curvature large to some extent, so they are deeply diffused. However, when the impurity is formed by deep diffusion, the impurity concentration gradient becomes gentle, resulting in poor frequency characteristics.

The above-mentioned drawbacks are not limited to the above-mentioned planar transistors and MOS transistors, but also occur in semiconductor devices including 5IT (static induction transistors) and diodes.

An object of the present invention is to provide a high-performance, high-voltage semiconductor device that operates at high speed and has improved frequency characteristics by reducing the parasitic capacitance of a semiconductor layer directly under a bonding pad.

(Means for Solving the Problems) The present invention includes an active semiconductor region formed in a semiconductor substrate, and at least one field limiting ring surrounding the active semiconductor region and connected to the active semiconductor region. , in a semiconductor device in which a metal film for taking out an electrode by a wire conducting wire is formed on the main surface of a semiconductor substrate via an insulating film, the metal film for taking out an electrode is provided above at least the innermost field limiting ring, and Field limiting in the semiconductor area
It is characterized by being formed shallower than a ring.

(Function) In the present invention, an electrode extraction metal film, which is a bonding butt, is provided above a field limiting ring that is completely separated from an active semiconductor region that is electrically connected to this metal film. However, since this field limiting ring does not constitute parasitic capacitance, switching speed can be improved.

Further, especially in a bipolar transistor, since the active semiconductor region is formed shallowly, its impurity concentration gradient becomes steep, and frequency characteristics can be improved.

(Embodiment) FIG. 1 shows a first embodiment of a high breakdown voltage semiconductor device of the present invention, and in this embodiment, a bipolar transistor is formed on a silicon chip.

An n-type epitaxial layer 42 is grown on an n1-type semiconductor substrate 41, and this epitaxial layer includes a p-type semiconductor layer 43 forming a base region and an n-type semiconductor layer 43 forming an emitter region.
A field limiting ring (FLR) 50a is formed as well as a half body layer 44 of the type 44.

50b. An insulating film 45 is formed on the surface of the epitaxial layer 42, an emitter electrode metal film 46 and a base electrode metal film 47 are formed on this insulating film, and openings 45a and 45b are formed in the insulating film 45 through these metal films. a p-type semiconductor layer 43 and an n-type half layer 44, respectively.
Make an ohmic connection. Further, these metal electrode films 46 and 47 are extended on the insulating film 45, and are emitter bonding pad 46a and base bonding pad 47a.
and wire conductors 4 to these bonding pads.
8 and 49 are bonded. In the present invention,
As shown in FIG. 1(a), a part of the inner FLR 50a is made to protrude inward, and bonding butts 46a and 47a are formed above this part with an insulating film 45 interposed therebetween.

Since the FLR 50a is configured as an island region independent from the p-type semiconductor layer 43 and is not electrically connected to the bonding pads 46a and 47a, the collector-base junction capacitance is small and the switching speed is high. Furthermore, since the same bias as the base is applied to the bonding band formed on the FLR 50a, it functions as a field plate, improving reliability. In order to act as a field plate in this way, the bonding pad is placed on the outermost F.
The configuration is such that it does not extend to the LR 50b. Furthermore, the P-type semiconductor layer 43 constituting the base region is FLR.
Since it is formed shallower than 5, Oa, and 50b, the impurity concentration gradient in the base region becomes steep, and the frequency characteristics are significantly improved. In this way, switching
A high-performance, high-voltage bipolar transistor with high speed and excellent frequency characteristics can be obtained.

Further, to show a numerical example of this embodiment, the depth of the base P-type semiconductor layer 43 is 2 to 3 μm, and the depth of the emitter n-type semiconductor layer 44 is 2 to 3 μm.
The depth of FLR 50a and 50b is 1.5 #n+, and the depth of FLR 50a and 50b is 10 μm. In addition, in other numerical examples, the above-mentioned depths are 1 to 1.5 pta and 0.5 to 0.75 μm, respectively.
and 5 μm. Generally, the depth of the base P-type semiconductor layer 43 and the depth D2 of the FLRs 50a and 50b are D, ≦
It is preferable to configure it so as to satisfy the relationship: 0.7 x [l.

FIGS. 2(a) to 2(C) are cross-sectional views for explaining the manufacturing process of the high voltage semiconductor device having the bipolar transistor shown in FIG. 1. An n-type epitaxial layer 42 with a low impurity concentration is grown on an n-type semiconductor substrate 41 to form an n-on-n type semiconductor substrate. Next, after selectively diffusing p-type impurities to form deep p-type field limiting rings 50a and 50b, an oxide film 45 is formed on the surface.

This state is shown in FIG. 2(a).

Next, an opening is formed in the oxide film 45, and p-type impurities are selectively diffused to form a shallow p-type base diffusion layer 43.

This state is shown in FIG. 2(b).

Furthermore, an opening is formed in the oxide film 45 and n-type impurities are diffused into the p-type base diffusion layer 43 to form an n++ emitter diffusion layer 4.
form 4. This state is shown in FIG. 2(c).

Finally, contact openings 45a and 45 are formed in the oxide film 45.
After the formation of layer b, two films are deposited and patterned to form electrode films 46 and 47, thereby making it possible to manufacture a bipolar transistor as shown in FIG. 2(d).

In the high voltage semiconductor device of the present invention, the position of the bonding band is different from that of conventional semiconductor devices, and the p-type
Although the LR and the p-type base diffusion layer are formed sequentially rather than simultaneously, the manufacturing process is not so complicated.

FIG. 3 shows a second embodiment of the high voltage semiconductor device of the present invention, in which a DSA-MOS transistor is formed. An n-type epitaxial layer 62 is formed on an n++ semiconductor substrate 61 to constitute a silicon substrate with an n-on n+ structure. The epitaxial layer 62 includes a tp" type semiconductor layer 63a selectively located within the cell and for improving ohmic contact resistance with the source Af electrode, and a second p" type semiconductor layer located around the cell assembly. layer 63b;
The second p'' type semiconductor layer is surrounded by FLRs 63c and 63d formed of p'' type half layers surrounding the second p'' type semiconductor layer in a ring shape.

In the conventional semiconductor device, as shown in FIG. 5, bonding pads are formed above the p+ type groove conductor layers 15d and 15e that are continuous with the second p+ type semiconductor layer 15b located around the cell assembly. However, in the present invention, the second
PL formed independently of the p" type semiconductor layer 63b
Formed above R63c. Furthermore, in the present invention, the second p'' type semiconductor layer 63b is formed to be shallower than the field limiting rings 63c and 63d.

Next, after forming a gate insulating film 64 to a thickness of about 1,000 wafers, a polycrystalline silicon film 65 serving as a gate electrode material is selectively formed to a thickness of about 6,000 wafers. Subsequently, boron ions are implanted using the gate polycrystalline silicon film 65 as a mask to form a p-type semiconductor layer 66 constituting a channel region. Next, phosphorus ions are implanted to form an n-type thick conductor layer 67 constituting a source region, and then a silicon oxide film 68 is formed by CVD. Next, silicon oxide film 6
After forming an opening for taking out the electrode, the electrode film 69 is removed.
is selectively formed to a thickness of about 4 μm. At this time, an Al electrode film 69 is selectively formed on the silicon oxide film 68, and bonding pads 69a and 69b are formed.

The bonding pad 69a is connected to the gate polycrystalline silicon film 65, and a gate wire conducting wire 70 is connected thereto.
Bonding. In addition, the bonding pad 69
b is connected to both the n-type thick conductor layer 67 and the p-type semiconductor layer 66, and a source wire conductor 71 is bonded thereto.

In the semiconductor device of the present invention described above, the FLR 6 located directly below the bonding pads 69a and 69b
3c is separated from the second p+ type semiconductor layer 63b and formed into an island shape, so that the parasitic capacitance between the source and drain becomes extremely small, and the switching speed is significantly improved. . Furthermore, since the field limiting rings 63c and 63d are formed sufficiently deep, a high breakdown voltage can be achieved.

The present invention is not limited to the embodiments described above, and numerous changes and modifications are possible. The present invention is based on the MIS described above.
The present invention is not limited to semiconductor devices and bipolar type semiconductor devices, but can also be applied to, for example, electrostatic induction type semiconductor devices and semiconductor devices having bonding pads such as diodes. Furthermore, it is applicable not only to individual semiconductor devices but also to composite integrated circuits in which high-frequency transistors, high-power transistors, low-voltage transistors, etc. coexist. Furthermore, in the embodiments described above, p-type and n-type
The type can also be reversed. Furthermore, the n-type epitaxial layer may be an n-type semiconductor layer formed by a pulling method.

(Effects of the Invention) According to the present invention, since the semiconductor region having a vast volume directly under the bonding pad is configured as a field limiting ring that is independently separated from the source region or the base region, The junction capacitance between the transistors can be reduced, and the switching speed can therefore be improved. Particularly in bipolar transistors, since the active semiconductor region is formed shallowly, the frequency characteristics can be improved.

Additionally, when multiple field limiting rings are provided and the bonding band is formed so as not to reach the outermost field limiting ring, the bonding pad must function as a field plate. Therefore, it is possible to obtain the effect of improving the stability of the operation.

[Brief explanation of drawings]

FIGS. 1(a) and (b) are a cross-sectional view and a plan view showing the structure of a first embodiment of a high voltage semiconductor device of the present invention, and FIGS. 2(a) to (d) are the same sequential manufacturing steps. FIG. 3 is a cross-sectional view showing the structure of a second embodiment of the high voltage semiconductor device of the present invention, and FIGS. 4(a) and 4(b) show the structure of an example of a conventional semiconductor device. 5 is a sectional view showing the configuration of another example of a conventional semiconductor device; FIGS. 6(a) and (b) are the same (a plan view and a sectional view showing the configuration of a part thereof It is a sectional view. 41-.N9 type semiconductor substrate 42-..N type epitaxial layer 43-...P type base region 44-.N
Type emitter region 45 --- Insulating film 46a, 47a --- Bonding pad 48
．． 49--Wire conductors 50a, 50b--Field limiting ring 6 t-n'' type semiconductor substrate, 62--n type epitaxial layer 63a--First p'' type semiconductor layer 63b-th 2p+ type semiconductor layers 63c, 63d...Field limiting ring 64--gate insulating film 65--polycrystalline silicon film 66--p-type semiconductor layer 67--n-type trench conductor layer 68-- Insulating film 69--Electrode metal film 69a, 69b--Bonding pad 70.7
1.- Wire conductor made by patent attorney Oki Sugimura eI3
- M
No-Q ℃ 1～-1
--lFigure 4Figure 6 (a) (b)

Claims (1)

[Claims] 1. A metal film having an active semiconductor region formed on a semiconductor substrate and at least one field limiting ring surrounding the active semiconductor region, and an electrode lead-out metal film connected to the active semiconductor region by a wire conductor is connected to the main surface of the semiconductor substrate. In a semiconductor device formed on top with an insulating film,
A high breakdown voltage semiconductor device, characterized in that the electrode extraction metal film is provided above at least the innermost field limiting ring, and the active semiconductor region is formed shallower than the field limiting ring.