JPS61265833A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS61265833A
JPS61265833A JP60106847A JP10684785A JPS61265833A JP S61265833 A JPS61265833 A JP S61265833A JP 60106847 A JP60106847 A JP 60106847A JP 10684785 A JP10684785 A JP 10684785A JP S61265833 A JPS61265833 A JP S61265833A
Authority
JP
Japan
Prior art keywords
semiconductor layer
type semiconductor
type
layer
bonding pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60106847A
Other languages
Japanese (ja)
Inventor
Yoshitaka Sasaki
芳高 佐々木
Yoshitaka Oishi
好高 大石
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Corp
Original Assignee
TDK Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by TDK Corp filed Critical TDK Corp
Priority to JP60106847A priority Critical patent/JPS61265833A/en
Publication of JPS61265833A publication Critical patent/JPS61265833A/en
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
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    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
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    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/732—Vertical transistors
    • H01L29/7322—Vertical transistors having emitter-base and base-collector junctions leaving at the same surface of the body, e.g. planar transistor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05541—Structure
    • H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05556—Shape in side view
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]

Abstract

PURPOSE:To reduce the parasitic capacity of a semiconductor device and to improve switching speed, by constituting semiconductor regions directly beneath bonding pads as independent regions. CONSTITUTION:On an N-type epitaxial layer 22 on an N<+> type semiconductor substrate 21, a first P<+> type semiconductor layer 23a, a second P<+> type semiconductor layer 23b located around a cell assembly and a third P<+> type semiconductor layer 23c, which surrounds the layer 23b, are formed. A fourth P<+> type semiconductor layer 23d located directly beneath a bonding pad 29a and a fifth P<+> type semiconductor layer 23e located directly beneath a bonding pad 29b are formed in an independently isolated manner. Since the semiconductor layers 23d and 23e are isolated from the semiconductor layer 23b, the parasitic capacity between a source and a drain becomes extremely small, and the switching speed is strikingly improved.

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は一導電型の半導体基体に複数の半導体領域を形
成し、或る半導体領域に接続された電極取り出し金属膜
を半導体基体の主面上に絶縁膜を介して形成し、この電
極取り出し金属膜にワイヤ・導線をボンディングにより
接続するようにした半導体装置に関するものであり、と
くに寄生容量を減少せしるめることによってスイッチン
グスピードの向上を図った半導体装置に関するものであ
る。Detailed Description of the Invention (Industrial Application Field) The present invention forms a plurality of semiconductor regions on a semiconductor substrate of one conductivity type, and connects an electrode lead-out metal film connected to a certain semiconductor region to a main surface of the semiconductor substrate. This relates to a semiconductor device in which an insulating film is formed on top of the metal film, and wires and conductive wires are connected to this metal film by bonding.In particular, it improves switching speed by reducing parasitic capacitance. The present invention relates to a semiconductor device that achieves the following.

（従来の技術） 近年において、微細加工の技術向上により、素子の限界
近くまで微細化が駆使され、そのため、素子の寄生容量
が減少され、高速で高性能な半導体装置あるいは半導体
集積回路が出現してきている。しかしながら全てにおい
て微細化ができるのではなく、微細化が可能である部分
と、そうでない部分とがある。(Conventional technology) In recent years, improvements in microfabrication technology have allowed devices to be miniaturized to near their limits, resulting in the emergence of high-speed, high-performance semiconductor devices or semiconductor integrated circuits that reduce the parasitic capacitance of devices. ing. However, not everything can be miniaturized; there are some parts where miniaturization is possible and some parts where it is not.

特に大電力用トランジスタにおいては、電流容量が大き
いため１．電極取り出しワイヤ導線の太いものが使われ
、それにともなって、ワイヤ導線と接合されるボンディ
ング用パッドと呼ばれる広いＡｌ膜パターンが存在し、
大電力用素子はど、このボンディング用パッドは面積の
大きな領域が必要とされていた。一般的にボンディング
用パッド直下の半導体領域はバイポーラ型トランジスタ
ではベース領域、ＭＯ３型トランジスタにおいてはソー
ス領域と同じバイアスが印加される領域となっている。In particular, high-power transistors have a large current capacity, so 1. A thick electrode lead wire is used, and along with this, there is a wide Al film pattern called a bonding pad that is bonded to the wire conductor.
For high-power devices, this bonding pad requires a large area. Generally, the semiconductor region directly under the bonding pad is a region to which the same bias is applied as the base region in a bipolar transistor and the source region in an MO3 transistor.

第５図はバイポーラ型トランジスタを形成した従来の半
導体装置の構造を示すものであり、シリコンチップ上に
はベース領域とエミッタ領域に対する２つのボンディン
グ用バッドが形成されている。ｎ＋＋シリコン半導体基
板１上にｎ型シリコンエピタキシャル層２を成長させて
ｎオンｎ・構造のシリコン基体を構成している。エピタ
キシャル層２内にはベース領域として作用するｐ型半導
体層３を形成し、このｐ形半導体層内にエミッタ領域と
して作用するｎ゛型型厚導体層４形成している。エピタ
キシャル層２の主面上には絶縁膜５を形成し、この絶縁
膜にあけた開口５ａを経てｎ゛型型厚導体層４オーミッ
ク接続されたエミッタ１Ｍ電極膜６を絶縁膜５上に延在
させ、大面積のボンディング用パッド６ａを構成し、こ
こにワイヤ導線８をボンディングにより接続している。FIG. 5 shows the structure of a conventional semiconductor device in which a bipolar transistor is formed, in which two bonding pads for a base region and an emitter region are formed on a silicon chip. An n-type silicon epitaxial layer 2 is grown on an n++ silicon semiconductor substrate 1 to form an n-on-n structure silicon substrate. A p-type semiconductor layer 3 serving as a base region is formed within the epitaxial layer 2, and an n-type thick conductor layer 4 serving as an emitter region is formed within this p-type semiconductor layer. An insulating film 5 is formed on the main surface of the epitaxial layer 2, and an emitter 1M electrode film 6 ohmically connected to the n-type thick conductor layer 4 is extended onto the insulating film 5 through an opening 5a formed in the insulating film. A large-area bonding pad 6a is formed, and a wire conducting wire 8 is connected thereto by bonding.

また、絶縁膜５にあけた別の開口５ｂを経てｐ型半導体
層３にオーミック接続されたベースＡ１電極膜７も絶縁
膜５上に延在させ、ボンディング用パッド７ａを構成し
、ここにワイヤ導線９をボンディングにより接続してい
る。なお、第５図において、バイポーラトランジスタを
囲むようにｐ型のフィールドリミッティングリング１０
が形成されている。Further, the base A1 electrode film 7, which is ohmically connected to the p-type semiconductor layer 3 through another opening 5b made in the insulating film 5, is also extended on the insulating film 5 to form a bonding pad 7a, and a wire is connected to the base A1 electrode film 7. A conductive wire 9 is connected by bonding. In addition, in FIG. 5, a p-type field limiting ring 10 surrounds the bipolar transistor.
is formed.

従来の？ｌＯＳ型トランジスタは低耐圧、低電力デバイ
スと考えられていたが、最近の半導体製造技術あるいは
回路設計技術等の発展に伴い、高耐圧、大電力設計が可
能となり、現在ではパワーデバイスとしてその地位を確
保するに至っている。Traditional? The OS type transistor was thought to be a low-voltage, low-power device, but with recent developments in semiconductor manufacturing technology and circuit design technology, it has become possible to design high-voltage and high-power devices, and it has now taken its place as a power device. We have reached the point where it has been secured.

かかるパワーＭＯ３）ランジスタの代表的なものとして
、ＤＳＡ　（Ｄｉｆｆｕｓｉｏｎ　Ｓｅｌｆ−Ａｌｉｇ
ｎｍｅｎｔ）構造のものが有る。ＤＳＡ−ＭＯＳ　　）
ランジスタは、二重拡散によりチャンネル領域を自己整
合的に形成するもので、格子形のゲート多結晶シリコン
電極に囲まれた同一の拡散窓によりチャンネル領域を形
成するためのｐ形不純物拡散とソース領域を形成するた
めのｎ°形不純物拡散とをおこなっているのが特徴であ
る。A typical example of such a power MO3) transistor is DSA (Diffusion Self-Alig).
There are some with nment) structure. DSA-MOS)
A transistor has a channel region formed in a self-aligned manner through double diffusion, and the same diffusion window surrounded by a lattice-shaped gate polycrystalline silicon electrode is used to diffuse p-type impurities and source regions to form the channel region. The feature is that n° type impurity diffusion is performed to form .

第６図はＤＳＡ−ＭＯＳ　　）ランジスタを形成した従
来の半導体装置の構造を示すものであり、第７図（ａ）
はセル構造を、Ａｌ電極膜を除去して示す平面図であり
、第７図（ｂ）は第７図（ａ）のＡ−Ａ線に沿う断面図
である。ｎ゛゛半導体基板１１上に、これよりも低不純
物濃度のｎ形エピタキシャル層１２を形成したｎオンｎ
゛構造となっており、これらがドレイン領域を構成して
いる。ドレイン電極は図面に示していないが、半導体基
板１１の裏面に形成されている。エピタキシャル層１２
上にはゲート酸化膜１３を介してケート多結晶シリコン
膜１４が形成されており、この多結晶シリコン膜１４に
は開口が形成されており、所謂セルを構成している。Figure 6 shows the structure of a conventional semiconductor device in which a DSA-MOS transistor is formed, and Figure 7(a)
7 is a plan view showing the cell structure with the Al electrode film removed, and FIG. 7(b) is a sectional view taken along line A--A in FIG. 7(a). An n-on n-type epitaxial layer 12 with a lower impurity concentration than this is formed on an n-semiconductor substrate 11.
These structures form the drain region. Although the drain electrode is not shown in the drawing, it is formed on the back surface of the semiconductor substrate 11. epitaxial layer 12
A gate polycrystalline silicon film 14 is formed thereon via a gate oxide film 13, and an opening is formed in this polycrystalline silicon film 14 to form a so-called cell.

エピタキシャル層１２内にはｐ゛型型環導体層１５ｐ型
半導体層１６およびｎ゛型型温導体層１７形成されてい
る。チャンネル長はｐ型半導体層１６とｎ゛型型温導体
層１７の拡散の深さの差で決まるので、チャンネル長が
数ミクロン以下と極めて短いチャンネル領域が形成でき
る。ソース金属電極膜１８はｎ・型半導体層１７と、ｐ
型半導体層１６に接しているｐ゛型型環導体層１５の両
方にオーミック接続されている。またゲート電極金属膜
１９は多結晶シリコン膜１４に接続されている。これら
のソースおよびゲート電極金属膜１Ｂおよび１９は絶縁
膜２０上を延在させ、面積の広いボンディング用パッド
１８ａおよび１９ａを構成し、これらボンディング用パ
ッドにワイヤ導線２１および２２をそれぞれボンディン
グして接続している。In the epitaxial layer 12, a p-type ring conductor layer 15, a p-type semiconductor layer 16, and an n-type hot conductor layer 17 are formed. Since the channel length is determined by the difference in diffusion depth between the p-type semiconductor layer 16 and the n-type hot conductor layer 17, an extremely short channel region with a channel length of several microns or less can be formed. The source metal electrode film 18 includes the n-type semiconductor layer 17 and the p-type semiconductor layer 17.
It is ohmically connected to both of the p-type ring conductor layer 15 that is in contact with the p-type semiconductor layer 16. Further, the gate electrode metal film 19 is connected to the polycrystalline silicon film 14. These source and gate electrode metal films 1B and 19 extend on the insulating film 20 and constitute large-area bonding pads 18a and 19a, to which wire conductors 21 and 22 are bonded and connected, respectively. are doing.

ここでｐ＋型型厚導体層１５セル内に位置する第１ｐ＋
型半導体層１５ａと、セルが集合して或るセル集合領域
の周囲を囲むように位置する第２ｐ゛型半導体層１５ｂ
と、ソース−ドレイン間耐圧（Ｖｎｓｉ）を大きくする
ために、第２ｐ゛型半導体Ｊｌｉ１５ｂをさらに囲むよ
うに設けた１本又は２木のフィールドリミッティングリ
ングと呼ばれているリング状の第３ｐ゛型半導体層１５
ｃと、ソース領域とゲート領域に対するボンディング用
パッド１８ａおよび１９ａの直下に位置し、前記セル集
合領域を囲むように位置する第２ｐ゛型半導体層１５ｂ
と連続して形成されている第４ｐ”型半導体層１５ｄお
よび第５ｐ＋型半導体ＪＷ１５ｅとそれぞれ同一のプロ
セス工程にて一緒に形成されている。Here, the first p+ layer located within the p+ type thick conductor layer 15 cell
a second p type semiconductor layer 15a and a second p' type semiconductor layer 15b located so as to surround a certain cell gathering area where cells gather together.
In order to increase the source-drain breakdown voltage (Vnsi), a ring-shaped third pin called a field limiting ring of one or two trees is provided to further surround the second p type semiconductor Jli15b. type semiconductor layer 15
c, and a second p-type semiconductor layer 15b located directly below the bonding pads 18a and 19a for the source region and gate region and surrounding the cell gathering region.
The fourth p'' type semiconductor layer 15d and the fifth p+ type semiconductor JW15e are formed in the same process step.

ゲー・ト多結晶シリコン膜１３のパターンは格子状のも
のやストライプ状のものがあるが第７図（ａ）では格子
状のパターンを示している。ゲートソース間に正の電圧
を加えてチャンネルをオンさせると、電流は半導体基板
１１から縦方向に流れ、チャンネル領域を通ってソース
領域に流れ込む。したがって、この電流を取り出すため
、一般的には八２の広い面積を有するボンディング用パ
ッド１８ａが形成され、このボンディング用バッドかラ
ワイヤ導線２１を引き出している。ソース電極１８は、
セルと呼ばれるゲート多結晶シリコン膜１４に形成した
開口内に位置する第１ｐ”型半導体層１５ａと、セルが
集合されて或る集合体の周囲を取り囲んでいる第２ｐ゛
型半導体層１５ｂと、ボンディング用バッド１８ａの直
下の第４．第５半導体層１５ｄ、　１５ｅとに電気的に
接続されている。したがってゲート電極のボンディング
用パッド１９ａ直下の第５ｐ°型半導体層１５ｄもソー
ス領域と同じ電位を持つことになる。The pattern of the gate polycrystalline silicon film 13 may be a lattice pattern or a stripe pattern, and FIG. 7(a) shows a lattice pattern. When a positive voltage is applied between the gate and the source to turn on the channel, current flows vertically from the semiconductor substrate 11, passes through the channel region, and flows into the source region. Therefore, in order to extract this current, a bonding pad 18a having a large area is generally formed, and the raw wire conductor 21 is drawn out from this bonding pad. The source electrode 18 is
A first p'' type semiconductor layer 15a located in an opening formed in the gate polycrystalline silicon film 14 called a cell, a second p'' type semiconductor layer 15b surrounding a certain aggregate of cells, It is electrically connected to the fourth and fifth semiconductor layers 15d and 15e directly under the bonding pad 18a. Therefore, the fifth p° type semiconductor layer 15d directly under the bonding pad 19a of the gate electrode is also at the same potential as the source region. will have.

（発明が解決しようとする問題点） 上述した構成の半導体装置において、ＭＯＳトランジス
タのスイッチングスピードを向上させる一要因として、
ソース−ドレイン間の寄生容量を減少させることがある
。このソース−ドレイン間の寄生容量はソース領域の不
純物濃度を低く抑え、さらにまた限られたシリコンチッ
プ内に占めるソース領域の容量を極力小さく抑えること
も重要なことである。一方、プレーナ型の大電力、高耐
圧用トランジスタにおいては、或る一定の深さに不純物
拡散（バイポーラトランジスタではベース領域３を形成
するための拡散であり、ＭＯＳ　　）ランジスタではｐ
゛型型厚導体層１５形成するための拡散）を施さなけれ
ば高耐圧で安全動作領域の広いトランジスタは得られに
くい。当然のごと＜　、ＤＳＡ−ＭＯＳトランジスタに
おいては、ｐ“型半導体層１５を深く形成することはソ
ース領域の容積が大きくなることになる。しかも、ボン
ディング用パッド直下のｐ０型型半体層１５ｄ、　１５
ｅは他の領域に比較して広大な面積を有している。例え
ば直径３００μｍのワイヤ導線を用いる場合、７００　
Ｘ１５００μｍ２の面積を有するものとなる。このよう
に、従来の半導体装置においては、ボンディング用バッ
ドの直下に大きな容積を有しているとともに広大な面積
を有している半導体層が存在しており、この部分のソー
ス−ドレイン間又はソースエミッタ間の寄生容量は著し
く大きなものとなり、スイッチングスピードが低下する
欠点がある。(Problems to be Solved by the Invention) In the semiconductor device having the above-described configuration, one factor for improving the switching speed of the MOS transistor is as follows.
The parasitic capacitance between source and drain may be reduced. Regarding this parasitic capacitance between the source and drain, it is important to keep the impurity concentration of the source region low, and furthermore, to keep the capacitance of the source region occupying a limited silicon chip as small as possible. On the other hand, in planar type transistors for high power and high breakdown voltage, impurity is diffused to a certain depth (in bipolar transistors, this is diffusion to form the base region 3, and in MOS transistors, p
Unless diffusion (diffusion for forming the thick conductor layer 15) is performed, it is difficult to obtain a transistor with a high withstand voltage and a wide safe operating range. Naturally, in the DSA-MOS transistor, forming the p" type semiconductor layer 15 deeply increases the volume of the source region. Moreover, the p0 type half layer 15d directly under the bonding pad, 15
e has a large area compared to other regions. For example, when using a wire conductor with a diameter of 300 μm, 700 μm
It has an area of x1500 μm2. As described above, in conventional semiconductor devices, there is a semiconductor layer having a large volume and a vast area directly under the bonding pad, and the source-drain or source This has the disadvantage that the parasitic capacitance between emitters becomes significantly large, and the switching speed decreases.

本発明の目的は、ボンディング用パッド直下の半導体層
の寄生容量を減少せしめることによって高速で高性能の
半導体装置を提供しようとするものである。An object of the present invention is to provide a high-speed, high-performance semiconductor device by reducing the parasitic capacitance of a semiconductor layer directly below a bonding pad.

（問題点を解決するための手段） 本発明は一導電型の半導基体に形成した複数の半導体領
域を有し、或る半導体領域に接続された、ワイヤ導線に
よる電極取り出し金属膜を半導体基体主面上に絶縁膜を
介して形成した半導体装置において、上記電極取り出し
金属膜直下の前記半導体基体の主面に前記絶縁膜を介し
て、半導体基体によって周囲を囲まれた少なくとも１つ
の島状の反対導電型の半導体層を設けたことを特徴とす
るものである。(Means for Solving the Problems) The present invention has a plurality of semiconductor regions formed on a semiconductor substrate of one conductivity type, and an electrode lead-out metal film connected to a certain semiconductor region by a wire conductor is connected to the semiconductor substrate. In a semiconductor device formed on a main surface with an insulating film interposed therebetween, at least one island-like structure surrounded by the semiconductor substrate is formed on the main surface of the semiconductor substrate directly under the electrode lead-out metal film with the insulating film interposed therebetween. It is characterized in that semiconductor layers of opposite conductivity types are provided.

（作　　用） 本発明においては、ボンディング用バットである電極取
り出し金属膜直下に、この金属膜と電気的に接続されて
いない島状の半導体層を設けたため、この島状半導体層
は最早や寄生容量を構成しなくなり、スイッチングスピ
ードを向上することができる。(Function) In the present invention, an island-shaped semiconductor layer that is not electrically connected to the metal film is provided directly under the metal film for taking out the electrode, which is the bonding butt, so that the island-shaped semiconductor layer no longer becomes parasitic. This eliminates the need for capacitance and improves switching speed.

（実施例） 第１図（ａ）および（ｂ）は本発明の半導体装置の第１
実施例を示すものであり、ＤＳＡ−ＭＯＳ　　）ランジ
スタを形成したものである。ｎ゛゛半導体基板２１上に
ｎ型エピタキシャル層２２を形成してｎオンｎ゛構造の
シリコン基体を構成する。エピタキシャル層２２には、
選択的にセル内に位置し、ソースＡｌ電極とのオーミッ
クコンタクト抵抗を改善するための第１ｐ”型半導体層
２３ａと、セル集合体の周囲に位置する第２ｐ”型半導
体層２３ｂと、この第２ｐ゛型半導体層の周囲をリング
状に囲む第３ｐ。(Example) FIGS. 1(a) and (b) show the first example of the semiconductor device of the present invention.
This shows an example in which a DSA-MOS transistor is formed. An n-type epitaxial layer 22 is formed on an n-type semiconductor substrate 21 to form a silicon substrate having an n-on n-type structure. The epitaxial layer 22 includes:
A first p'' type semiconductor layer 23a selectively located within the cell to improve the ohmic contact resistance with the source Al electrode, a second p'' type semiconductor layer 23b located around the cell assembly, and this second p'' type semiconductor layer 23b located around the cell assembly. A 3rd p layer surrounds the 2p type semiconductor layer in a ring shape.

型半導体層２３ｃと、ボンディング用パッド直下の第４
および第５のｐ゛型型厚導体層２３ｄよび２３ｅとを形
成する。従来の半導体装置においては、第４および第５
のｐ゛型型厚導体層２３ｄよび２３ｅを、セル集合体の
周囲に位置する第２ｐ・型半導体層２３ｂと連続して形
成していたが本発明では第２ｐ”型半導体層２３ｂとは
独立して形成する。勿論、製造工程上は、第４および第
５ｐ”型半導体層２３ｄおよび２３ｅは第２ｐ°型半導
体層２３ｂと同一工程で形成することができる。すなわ
ち、本発明においては、ゲートボンディング用パッドの
直下に位置する第４ｐ”型半導体層２３ｄと、ソースボ
ンディング用バット直下に位置する第５ｐ”型半導体層
２３ｅは、ｎ型エピタキシャル層２２によって島状に独
立分離して形成されている。type semiconductor layer 23c and the fourth layer directly under the bonding pad.
Then, fifth p-type thick conductor layers 23d and 23e are formed. In conventional semiconductor devices, the fourth and fifth
The p'' type thick conductor layers 23d and 23e were formed continuously with the second p'' type semiconductor layer 23b located around the cell assembly, but in the present invention, they are formed independently of the second p'' type semiconductor layer 23b. Of course, in terms of the manufacturing process, the fourth and fifth p'' type semiconductor layers 23d and 23e can be formed in the same process as the second p° type semiconductor layer 23b. That is, in the present invention, the fourth p'' type semiconductor layer 23d located directly under the gate bonding pad and the fifth p'' type semiconductor layer 23e located directly under the source bonding pad are island-shaped by the n type epitaxial layer 22. It is formed independently and separately.

次にゲート用絶縁膜２４を約１０００人の厚さに形成し
た後、ゲート電極材料となる多結晶シリコン膜２５を約
６０００人の厚さに選択的に形成する。続いてゲート多
結晶シリコン膜２５をマスクとしてボロンイオン注入を
行い、チャンネル領域を構成するｐ型半導体層２６を形
成する。次にリンイオン注入を行い、ソース領域を構成
するｎ゛型型厚導体層２７形成した後、ＣＶＤ法にてシ
リコン酸化膜２８を形成する。続いてシリコン酸化膜２
日に電極取り出し用開口を形成した後＾ｌ電極膜２９を
約４μｍの厚さに選択的に形成する。この際、Ａｌ＠極
膜２９をシリコン酸化膜２８上に選択的に形成するとと
もにボンディング用パッド２９ａおよび２９ｂを形成す
る。Next, after forming the gate insulating film 24 to a thickness of about 1,000 wafers, a polycrystalline silicon film 25 serving as a gate electrode material is selectively formed to a thickness of about 6,000 wafers. Subsequently, boron ions are implanted using the gate polycrystalline silicon film 25 as a mask to form a p-type semiconductor layer 26 constituting a channel region. Next, phosphorus ions are implanted to form an n-type thick conductor layer 27 constituting a source region, and then a silicon oxide film 28 is formed by CVD. Next, silicon oxide film 2
After forming an opening for taking out the electrode, an electrode film 29 is selectively formed to a thickness of about 4 μm. At this time, an Al@ electrode film 29 is selectively formed on the silicon oxide film 28, and bonding pads 29a and 29b are formed.

ボンディング用パッド２９ａはゲート多結晶シリコン膜
２５に接続されており、ここにはゲートワイヤ導線３０
をボンディングする。また、ボンディング用パッド２９
ｂはｎ゛型型厚導体層２７よびｐ型半導体層２６の双方
に接続されており、ここにはソースワイヤ導線３１がボ
ンディングされている。The bonding pad 29a is connected to the gate polycrystalline silicon film 25, and a gate wire conducting wire 30 is connected thereto.
Bonding. In addition, the bonding pad 29
b is connected to both the n-type thick conductor layer 27 and the p-type semiconductor layer 26, and a source wire conductor 31 is bonded thereto.

上述した本発明の半導体装置においては、ボンディング
用バッド２９ａおよび２９ｂの直下に位置する第４およ
び第５のｐ１１型半導層２３ｄおよび２３ｅは第２ｐ”
型半導体層２３ｂから分離して島状に形成されているの
で、ソースドレイン間の寄生容量はきわめて小さくなり
、スイッチングスピードは著しく向上する。In the semiconductor device of the present invention described above, the fourth and fifth p11 type semiconductor layers 23d and 23e located directly under the bonding pads 29a and 29b are the second p''
Since it is separated from the type semiconductor layer 23b and formed into an island shape, the parasitic capacitance between the source and drain becomes extremely small, and the switching speed is significantly improved.

第２図（ａ）および（ｂ）は本発明の半導体装置の第２
実施例を示すものである。本例でも前例と同様にシリコ
ンチップ内にＤＳＡ−ＭＯＳ　　）ランジスタを構成し
たものであり、前例と同じ部分には同一符号を付けて示
し、その説明は省略する。本例ではゲートボンディング
用パッド２９ａの直下の第４ｐ＋型半導体層を複数個の
独立した島状の半導体層２３ｄ　＋　。FIGS. 2(a) and 2(b) show the second structure of the semiconductor device of the present invention.
This shows an example. In this example as well, a DSA-MOS (MOS) transistor is constructed in a silicon chip as in the previous example, and the same parts as in the previous example are denoted by the same reference numerals, and the explanation thereof will be omitted. In this example, the fourth p+ type semiconductor layer directly under the gate bonding pad 29a is formed into a plurality of independent island-shaped semiconductor layers 23d + .

２３ａ　ｔを以て構成するとともにソースボンディング
用パッド２９ｂ直下に位置する第５ｐ”半導体層も複数
の独立した半導体層２３ｅ、、２３ｅ＝を以て構成する
。すなわち、第２図（ｂ）に示すように、一方の半導体
層２３ｄ　＋　、２３ｅ　＋をリング状に形成し、その
内部に他方の半導体ＷＡ２３ｄｔ、２３ｅｔを形成する
。23a to 23t, and the fifth p'' semiconductor layer located directly under the source bonding pad 29b is also composed of a plurality of independent semiconductor layers 23e, 23e=. That is, as shown in FIG. 2(b), one The semiconductor layers 23d + and 23e + are formed in a ring shape, and the other semiconductors WA 23dt and 23et are formed inside the rings.

ソース電極に正、ドレイン電極に負の電圧を印加すると
、第２ｐ＋型半導体層２３ｂがら空乏層が伸びフィール
ドリミッティングリングと呼ばれるｐ゛゛半導体層へ到
達する。同時に第２および第３ｐ“型半導体層２３ｂお
よび２３ｃからボンディング用バッド２９ａ　、　２９
ｂ直下の半導体１２３ｄ、、２３ｅ＋へ空乏層が到達す
る。さらに電圧を高（して行くと、ｐ゛型型厚導体層２
３ａ＋および２３ｅ、からその内側のｐ゛型型温導体層
２３ｄ２よび２３ｅ２へと次々に空乏層が伸びて行く。When a positive voltage is applied to the source electrode and a negative voltage is applied to the drain electrode, the depletion layer extends from the second p+ type semiconductor layer 23b and reaches a p゛゛ semiconductor layer called a field limiting ring. At the same time, bonding pads 29a, 29 are formed from the second and third p" type semiconductor layers 23b and 23c.
The depletion layer reaches the semiconductors 123d, , 23e+ directly below b. When the voltage is further increased (as the voltage increases, the p-type thick conductor layer 2
Depletion layers extend one after another from 3a+ and 23e to the inner p' type hot conductor layers 23d2 and 23e2.

このようにして、ボンディング用パッド２９ａ、　２９
ｂ直下のｐ°型型厚導体層２３ｄｌ、２３ｄ　ｔおよび
２３ｅｌ、２３ｅｚはフィールドリミッティングリング
と同じように作用して空乏層を広げ、ソース〜　ドレイ
ン間の耐圧を大きくし得るように構成されている。勿論
、本実施例においても、ボンディング用バッド２９ａお
よび２９ｂ直下のｐ゛型型半体体層２３ｄ＋２３ｄｔお
よび２３ｅ　、　、　２３ｅ、は第２ｐ”型半導体１ｉ
２３ｂとは独立して形成されているため、ソース−ドレ
イン間の寄生容量は小さく、スイッチングスピードは向
上している。In this way, the bonding pads 29a, 29
The p° type thick conductor layers 23dl, 23dt, 23el, and 23ez directly under b are configured to act in the same way as a field limiting ring to widen the depletion layer and increase the withstand voltage between the source and drain. There is. Of course, in this embodiment as well, the p'' type half body layers 23d+23dt and 23e, 23e directly under the bonding pads 29a and 29b are the second p'' type semiconductor 1i.
23b, the parasitic capacitance between the source and drain is small and the switching speed is improved.

第３図は本発明の半導体装置の第３の実施例を示すもの
であり、本例ではバイ゛ポーラトランジスタをシリコン
チップに形成したものである。ｎ４型半導体基板４１上
にｎ型エピキタシャルＮ４２を成長させ、このエピタキ
シャル層にはベース領域を構成するｐ型半導体層４３お
よびエミ・ツタ領域を構成するｎ°型型厚導体層４４形
成するとともにフィールドリミッティングリング５０を
形成する。エピタキシャル層４２の表面には絶縁膜４５
を形成し、この絶縁膜上にエミッタ電極金属膜４６と、
ベース電極金属膜４７とを形成し、これら金属膜を絶縁
膜４５にあけた開口４５ａおよび４５ｂを経てそれぞれ
ｐ型半導体層４３およびｎ゛型型厚導体層４４オーミッ
ク接続する。またこれら金属電極膜４６および４７は絶
縁膜４５上を延在させエミンタボンディング用パッド４
６ａおよびベースボンディング用パッド４７ａを形成し
、これらボンディング用パッドにワイヤ導線４８および
４９をボンディングする。本発明においては、ボンディ
ング用バンド４６ａおよび４７ａ直下に位置するｐ型半
導体層５１および５２をｐ型半導体層４３から独立した
島領域として構成する。したがってこれらのｐ型半導体
１ｉ５１および５２はボンディング用バット４６ａおよ
び４７ａに電気的に接続されないので、寄生容量は小さ
くなり、スイッチングスピードが高速となる。FIG. 3 shows a third embodiment of the semiconductor device of the present invention, in which a bipolar transistor is formed on a silicon chip. An n-type epitaxial N42 is grown on an n4-type semiconductor substrate 41, and in this epitaxial layer, a p-type semiconductor layer 43 constituting a base region and an n°-type thick conductor layer 44 constituting an emitter/vine region are formed. A limiting ring 50 is formed. An insulating film 45 is formed on the surface of the epitaxial layer 42.
is formed, and an emitter electrode metal film 46 is formed on this insulating film,
A base electrode metal film 47 is formed, and these metal films are ohmically connected to the p-type semiconductor layer 43 and the n-type thick conductor layer 44 through openings 45a and 45b formed in the insulating film 45, respectively. Further, these metal electrode films 46 and 47 are extended on the insulating film 45 to form the emitter bonding pad 4.
6a and a base bonding pad 47a are formed, and wire conductors 48 and 49 are bonded to these bonding pads. In the present invention, p-type semiconductor layers 51 and 52 located directly under bonding bands 46a and 47a are configured as island regions independent from p-type semiconductor layer 43. Therefore, since these p-type semiconductors 1i51 and 52 are not electrically connected to the bonding bats 46a and 47a, the parasitic capacitance is reduced and the switching speed is increased.

第４図は本発明の半導体装置の第４の実施例を示すもの
であり、第３図に示した部分と同じ部分には同一符号を
付けて示し、その説明は省略する。FIG. 4 shows a fourth embodiment of the semiconductor device of the present invention, and the same parts as those shown in FIG. 3 are denoted by the same reference numerals, and the explanation thereof will be omitted.

本例においてはエミッタボンディング用パッド４６ａ直
下にそれぞれ２個の独立したｐ型半導体層　５１　ａ。In this example, two independent p-type semiconductor layers 51a are provided directly below the emitter bonding pad 46a.

５１ｂおよび５２ａ　、　５２ｂを形成する。すなわち
、一方のｐ型半導体層５１ａ、５２ａをリング状に構成
し、その内部に他方のｐ型半導体層５１ｂ、５２ｂを構
成する。51b and 52a, 52b are formed. That is, one p-type semiconductor layer 51a, 52a is formed into a ring shape, and the other p-type semiconductor layer 51b, 52b is formed inside the ring-shape.

本例でも、寄生容量を小さくすることができるとともに
ベース−コレクタ間の耐圧を高くすることができる。In this example as well, the parasitic capacitance can be reduced and the withstand voltage between the base and the collector can be increased.

本発明は上述した実施例に限定されるものではなく、幾
多の変更や変形が可能である。本発明は上述したＭＩＳ
半導体装置およびバイポーラ型半導体装置に限定される
ものではなく、例えば静電誘導型半導体装置等のボンデ
ィング用パッドを有する半導体装置にも適用することが
できる。また、個別半導体装置は勿論のこと、高周波数
トランジスタ、大電力トランジスタ、高耐圧トランジス
タ、低耐圧トランジスタ等を共存させた複合集積回路に
も適用可能である。さらに、上述した実施例において、
ｐ型とｎ型とを逆とすることもできる。The present invention is not limited to the embodiments described above, and numerous changes and modifications are possible. The present invention is based on the MIS described above.
The present invention is not limited to semiconductor devices and bipolar type semiconductor devices, but can also be applied to semiconductor devices having bonding pads, such as electrostatic induction type semiconductor devices. Furthermore, it is applicable not only to individual semiconductor devices but also to composite integrated circuits in which high-frequency transistors, high-power transistors, high-voltage transistors, low-voltage transistors, etc. coexist. Furthermore, in the embodiments described above,
The p-type and n-type can also be reversed.

さらにまた、ｎ型エピタキシャル層は引き上げ法によっ
て形成されたｎ型半導体層でもよい。Furthermore, the n-type epitaxial layer may be an n-type semiconductor layer formed by a pulling method.

（発明の効果） 本発明によれば、ボンディング用パッド直下の広大な容
積を持つ半導体領域をソース領域又はベース領域から独
立分離した島状の領域として構成したため、寄生容量を
小さくすることができ、したがってスイッチングスピー
ドを向上することができる。また、島状の領域を複数個
設け、これらの間を空乏層が拡がり易くすることによっ
てソース−ドレイン間またはベース−コレクタ間の耐圧
を大きくすることができる。(Effects of the Invention) According to the present invention, since the semiconductor region having a vast volume directly under the bonding pad is configured as an island-like region independently separated from the source region or the base region, parasitic capacitance can be reduced. Therefore, switching speed can be improved. Further, by providing a plurality of island-shaped regions and making it easier for the depletion layer to spread between these regions, the withstand voltage between the source and the drain or between the base and the collector can be increased.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）および（ｂ）は本発明の半導体装置の第１
実施例の構成を示す断面図および平面図、第２図（ａ）
および（ｂ）は本発明の半導体装置の第２実施例の構成
を示す断面図および平面図、゛第３図は本発明の半導体
装置の第３実施例の構成を示す断面図、 第４図は本発明の半導体装置の第４実施例の構成を示す
断面図、 第５図は従来の半導体装置の一例の構成を示す断面図、 第６図は従来の半導体装置の他の例の構成を示す断面図
、 第７図（ａ）および（ｂ）は同じくその一部分の構成を
示す平面図および断面図である。 ２１−ｎ”型半導体基板、　２２−ｎ型エピキシャル層
２３ａ　−第１ｐ＋型半導体層 ２３ｂ　−・第２９”型半導体層 ２３ｃｍ・第３ｐ９型半導体層 ２３ｄ　−第４ｐ＋型半導体層 ２３ｅ−・・第５ｐ゛型半導体層 ２４−・ゲート絶縁膜　　　２５−多結晶シリコン膜２
６・−ｐ型半導体層　　　２７−・ｎ°型型半体体層２
８・絶縁膜　　　　　　２！１−電極金属膜２９ａ、２
９ｂ・−・ボンディング用パッド３０．３１−　ワイヤ
導線 ２３ｄ＋、２３ｄｔ　−第４ｐ”型半導体層２３ｅ＋、
２３ｅｚ　−第５ｐ”型半導体層４ｔ−ｎ＋型半導体基
板　４２−・ｎ型エピキシャル層４３・−・ｐ型ベース
領域　　４４−・ｎ゛型エミッタ領域４５−絶縁膜 ４６ａ、４７ａ　−ボンディング用パッド４８．４９−
ｍ−・ワイヤ導線　　５１．５２−島状半導体層５１ａ
、５１ｂ、５２ａ、５２ｂ　−島状半導体層特許出願人
　　ティーディーケイ株式会社代理人弁理士　　杉　　
村　　暁　　秀同　　　弁理士　　杉　　　村　　　興
　　　作第１図 （ｂ） ２３ｄ　、　２３ｅFIGS. 1(a) and 1(b) show the first part of the semiconductor device of the present invention.
Cross-sectional view and plan view showing the configuration of the embodiment, FIG. 2(a)
and (b) are a cross-sectional view and a plan view showing the structure of a second embodiment of the semiconductor device of the present invention, ゛FIG. 3 is a cross-sectional view showing the structure of a third embodiment of the semiconductor device of the present invention, and FIG. 5 is a cross-sectional view showing the structure of an example of a conventional semiconductor device; FIG. 6 is a cross-sectional view showing the structure of another example of the conventional semiconductor device. FIGS. 7(a) and 7(b) are a plan view and a sectional view showing the structure of a portion thereof. 21 - n" type semiconductor substrate, 22 - n type epitaxial layer 23a - first p+ type semiconductor layer 23b - 29" type semiconductor layer 23cm, third p9 type semiconductor layer 23d - fourth p + type semiconductor layer 23e -... fifth p゛-type semiconductor layer 24--gate insulating film 25-polycrystalline silicon film 2
6.-p type semiconductor layer 27-.n° type half body layer 2
8. Insulating film 2!1- Electrode metal film 29a, 2
9b - Bonding pad 30.31- Wire conductor 23d+, 23dt - Fourth p'' type semiconductor layer 23e+,
23ez - fifth p'' type semiconductor layer 4t - n+ type semiconductor substrate 42 - n type epitaxial layer 43 - p type base region 44 - n' type emitter region 45 - insulating film 46a, 47a - bonding pad 48. 49-
m--wire conductor 51.52-island semiconductor layer 51a
, 51b, 52a, 52b - Island-shaped semiconductor layer patent applicant TDC Co., Ltd. Representative Patent Attorney Sugi
Illustration 1 (b) 23d, 23e by Hidetoshi Mura, Patent Attorney, and Oki Sugimura

Claims (1)

【特許請求の範囲】[Claims] １、一導電型の半導体基体に形成した複数の半導体領域
を有し、或る半導体領域に接続された、ワイヤ導線によ
る電極取り出し金属膜を半導体基体主面上に絶縁膜を介
して形成した半導体装置において、上記電極取り出し金
属膜直下の前記半導体基体の主面に、前記絶縁膜を介し
て、半導体基体によって周囲を囲まれた少なくとも１つ
の島状の反対導電型の半導体層を設けたことを特徴とす
る半導体装置。1. A semiconductor having a plurality of semiconductor regions formed on a semiconductor substrate of one conductivity type, with a metal film connected to a certain semiconductor region and an electrode taken out by a wire conductor formed on the main surface of the semiconductor substrate via an insulating film. In the device, at least one island-shaped semiconductor layer of an opposite conductivity type surrounded by the semiconductor substrate is provided on the main surface of the semiconductor substrate directly under the electrode extraction metal film, with the insulating film interposed therebetween. Characteristic semiconductor devices.
JP60106847A 1985-05-21 1985-05-21 Semiconductor device Pending JPS61265833A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60106847A JPS61265833A (en) 1985-05-21 1985-05-21 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60106847A JPS61265833A (en) 1985-05-21 1985-05-21 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS61265833A true JPS61265833A (en) 1986-11-25

Family

ID=14444032

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60106847A Pending JPS61265833A (en) 1985-05-21 1985-05-21 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS61265833A (en)

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