JPH11243200A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve reverse diode characteristics so as to realize a high withstand voltage MOS-type bipolar transistor of a monolithic structure by a method, wherein the region between a ring-shaped diffused region serving as a current route of a diode and a channel stopper region is set higher in impurity surface concentration than a low-concentration layer. SOLUTION: An N<+> diffused layer 10 is locally formed between a guard ring P<+> layer 205 on the current path IF of a reverse diode 400 and a P<+> layer 204 under a gate and between the guard ring P<+> layer 205 and an N<++> diffused layer 212 respectively. The N<+> diffused layer 10 is set at about 4E15 cm<-3> or less in concentration when a low concentration layer 202 is 3E14 cm<-3> or so in impurity concentration. In this way, the surface concentration of the current path IF of a reverse diode is set higher than a bulk concentration, whereby the resistance of anode-cathode can be lessened, and the reverse diode can be improved in characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a MOS type bipolar transistor (for example, IGB) mainly used for electric power.
T).

[0002]

2. Description of the Related Art A MOS type bipolar transistor (hereinafter referred to as IGBT) is mainly used under an inductive load, but has a structure without a built-in reverse diode. It is known that it is easily broken by a reverse bias such as a junction.

As a countermeasure, usually, a reverse diode chip called a freewheel diode (hereinafter referred to as a reverse diode), which is another chip, is incorporated in a package on which the IGBT is mounted.

However, the use of a two-chip IGBT and a reverse diode includes disadvantages such as a decrease in the work index and an increase in cost, and an increase in the size of the outer shape. The development of the built-in IGBT with a built-in reverse diode is active.

As the IGBT with a built-in reverse diode, for example, an anode short structure and a lateral diode structure (hereinafter, referred to as a lateral structure) are generally known. The anode short structure has a high technical difficulty because it complicates the structure and increases the number of steps. On the contrary,
The lateral structure has high versatility because the P-base region can be used as the anode region of the reverse diode and the N + channel stopper region can be used as the cathode region of the reverse diode, and the reverse diode can be built in without impairing the IGBT characteristics.

However, the lateral structure has a high versatility because of its simple structure. However, since the current path of the reverse diode is in the horizontal direction (see IF in FIG. 6 described later), the flat structure without the bulk diffusion layer is used. It is necessary to secure an area and reduce the current path. For this reason, the termination structure of the IGBT chip is generally changed from a conventional guard ring structure to a clamp diode built-in termination structure capable of securing a flat area and reducing a current path.

The terminating structure with a built-in clamp diode is a structure in which a clamp diode in which a bidirectional Zener diode is connected in a pair between a gate electrode and a collector electrode of an IGBT is built in. This is a termination structure that is incorporated in the termination of the IGBT and extends the bulk depletion layer by the surface potential of the clamp diode.

FIG. 3 is a plan view of a conventional IGBT chip with a built-in reverse diode (lateral structure), which adopts the above-mentioned clamp diode built-in type as its termination structure. The figure shows the final planar shape of the passivated chip, and the boundaries and the steps where the steps and colors differ on the surface are shown.

In the figure, reference numeral 101 denotes a clamp diode, and reference numerals 111 and 112 denote gate protection diodes. Reference numeral 121 denotes an opening of the passivation film,
The aluminum electrode (cathode electrode of the reverse diode) 130 in the region 122 is drawn and exposed to the opening 121, and at the position of the opening 121, the aluminum electrode 130 is connected to the collector electrode C of the IGBT. An aluminum wire (450 in FIG. 5 to be described later) is bonded in order to make connection to the substrate.

FIG. 4 shows an IG having the lateral structure shown in FIG.
It is a circuit diagram of BT.

This IGBT has an emitter E and a collector C
Are connected to each other, and the clamp diode 101 is connected between the collector C and the gate G. Further, a gate protection diode 111 is connected between the gate G and the emitter E.

FIG. 5 shows a lateral structure IGB shown in FIG.
FIG. 3 is a plan view before forming a gate insulating film 302 of a T chip.
FIG. 5 conceptually shows a state in which the aluminum electrode 130 serving as the cathode electrode of the above-described reverse diode 400 is joined to the collector electrode C of the IGBT via an aluminum wire 450. Diode 400
Is indicated by a dashed arrow.

FIG. 6 is a sectional view taken along the line AA ′ of the IGBT chip shown in FIGS.

In FIG. 1, reference numeral 201 denotes a P + sub-substrate. A collector electrode C is formed on the back surface of the P + sub-substrate 201, and an N- epitaxial layer 202 is laminated on the front surface thereof. On the main surface side of the N− epitaxial layer 202, the P + diffusion layer 20 under the ring-shaped gate pad is provided.
4 and the guard ring P + diffusion layer 205
Formed sequentially from the GBT region 300 to the chip peripheral edge, an N ++ diffusion layer 212 is formed at the chip peripheral edge.

In IGBT region 300, a P ++ diffusion layer 209 is formed in each P base layer 206 locally formed on the main surface side of N- epitaxial layer 202, and a predetermined P
This is a structure in which an N ++ diffusion layer 211 is formed in a ++ diffusion layer 209. Further, the P + diffusion layer 204 under the gate pad
P ++ in the inside and guard ring P + diffusion layer 205 respectively.
Diffusion layers 208 and 207 are formed.

In the figure, reference numeral 101a denotes a polysilicon film of a Zener diode constituting the clamp diode 101, 301 denotes an oxide film, 302 denotes a gate oxide film, and 3 denotes a gate oxide film.
04 is a gate poly electrode, and 305 is an interlayer insulating film. 311 is an Al emitter electrode, 312 is a gate electrode,
130 is a cathode electrode of the reverse diode 400.

The IGBT chip having such a lateral structure is
The P + diffusion layer under the gate pad serves as an anode region of the reverse diode 400, and the N ++ diffusion layer 212 serves as a cathode region. A current path IF is formed in the direction diode 400.

[0018]

However, the above-described conventional IGBT chip having a lateral structure has the following problems.

As described above, this lateral structure has a structure capable of securing a flat region and reducing the current path. However, the higher the breakdown voltage system (in general, the higher the breakdown voltage of the IGBT is, the higher the breakdown voltage), the more the lateral structure becomes. The number of clamp diodes 101 in series increases, and the anode region immediately below (the P + layer 20 under the gate pad)
4) and the cathode region (N @ + diffusion layer) has a long distance, which causes a problem of deteriorating the IF-VF characteristic of the reverse diode 400. SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned conventional problems, and an object of the present invention is to provide a semiconductor device in a IGBT having a lateral structure in which characteristics of a reverse diode are improved.

[0020]

According to a first aspect of the present invention, a semiconductor substrate of a high-concentration first conductivity type and a second conductivity type formed on a main surface of the semiconductor substrate are provided. A low-concentration layer, a base region composed of a low-concentration impurity layer of the first conductivity type partially provided on the upper surface of the low-concentration layer, and a second conductivity type partially provided on the surface of the base region. Forming a channel region with a source region made of a high-concentration impurity layer, and a ring-shaped diffusion region made of a first-conductivity-type high-concentration impurity layer formed on an upper surface of the low-concentration layer; A semiconductor device including a channel stopper region formed of a second conductive type high-concentration impurity layer on the outer periphery, a diode having the ring-shaped diffusion region as an anode region, and the channel stopper region as a cathode region; An impurity surface concentration between the ring-shaped diffusion region is the energizing path and the channel stopper region, in that said set higher than the low concentration layer.

According to the first aspect, the resistance between the anode region and the cathode region, which are the current supply paths of the diode, is reduced.

According to a second aspect of the present invention, in the first aspect, when the impurity concentration of the low-concentration layer is about 3E14 cm ³ , the ring-shaped diffusion region, which is a conduction path of the diode, and The point is that the impurity surface concentration between the impurity and the channel stopper region is set to about 4E15 cm ³ or less.

According to the second invention, a general 500
In a V-based device, it is possible to reduce the resistance between the anode region and the cathode region, which are the conduction paths of the diode, without lowering the bulk breakdown voltage.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a semiconductor device according to the present invention will be described.

FIG. 1 is a plan view of a lateral structure IGBT chip according to an embodiment of the semiconductor device of the present invention before a gate insulating film is formed, and corresponds to FIG. 5 described above. That is, in the lateral structure IGBT chip of FIG. 3 showing the final planar shape of the passivated chip, the planar structure before the formation of the gate insulating film 302 of the IGBT in this embodiment is shown.

Similar to FIG. 5, FIG. 1 conceptually shows a state in which the aluminum electrode 130 serving as the cathode electrode of the above-described reverse diode is joined to the collector electrode of the IGBT chip via an aluminum wire 450. In addition, the current path IF of the reverse diode 400 is indicated by a broken arrow.

FIG. 2 is a diagram showing the B of the IGBT chip shown in FIG.
FIG. 14 is a sectional view taken along the line B-B '.

The feature of this embodiment is that the guard ring P + layer 205 and the P + layer 204 under the gate pad on the current path IF of the reverse diode 400 in the conventional lateral IGBT chip shown in FIGS. And the N + diffusion layer 10 is locally formed between the guard ring P + layer 205 and the N ++ diffusion layer 212.

In the channel formation of the IGBT chip, the emitter region is formed in the P base layer 206, and the surface of the P base layer 206 is depleted by the voltage applied to the gate electrode 312 formed via the insulating film 305. , The emitter region and the N-epi layer 202.
The N ++ diffusion layer 212 is formed as a channel stopper region.

Next, the manufacturing process of the IGBT of this embodiment will be described.

First, an N- epi layer 202 is formed on a P + sub-substrate 201 by epitaxial growth, and the N + diffusion layer 10 which is a feature of the present invention is provided at the predetermined position on the main surface side of the N- epi layer 202. To form

The higher the impurity concentration of the N + diffusion layer 10 is, the more the reverse diode IF-VF characteristic can be improved. However, the presence of the highly doped N suppresses the depletion and the bulk between the collector and the emitter. Since there is a trade-off relationship of lowering the breakdown voltage, selection of the concentration of the N + diffusion layer 10 is an important point. Usually, if it is 500V system,
The impurity concentration of the N− epi layer 202 is set to about 3E14 cm ³ , and the concentration of the N + diffusion layer 10 is set to about 4E15 cm ³ or less. With this concentration setting, the IF-VF characteristics can be improved without lowering the bulk breakdown voltage.

Next, an oxide film is formed on the entire surface of the N-epi layer 202, and is patterned to form an oxide film 301. Using this oxide film 301 as a mask, a P + layer 204 under the gate pad and a guard ring P + layer 205 are simultaneously formed. At this time, a step 301a of the oxide film is formed.

Subsequently, in order to form a P base layer 206,
After forming a resist pattern on the surface of the wafer, ionized impurities (for example, B ⁺ ) are accelerated to high energy and implanted into the surface of the wafer. Then, if the resist pattern is removed, the P base layer 206 becomes the N- epi layer 20.
2 are formed.

Then, in the predetermined P base layer 206, N ++
A diffusion layer 211 is formed, and an N ++ diffusion layer 212 serving as a cathode region of the reverse diode 400 is formed at the outer peripheral end of the chip, and a P ++ diffusion layer 209 is also formed in the P base layer 206. . These diffusion layers are formed by forming a resist pattern on the surface of the N-epi layer 202 and providing respective diffusion windows.

Next, a gate insulating film (SiO 2) 302 and a polysilicon film are sequentially formed on the entire surface of the N-epi layer 202. The gate insulating film 302 is formed by heating the entire wafer in an oxidizing atmosphere to, for example, about 1000 ° C. This polysilicon film is used for the gate poly electrode 304 in the IGBT region 300 and for the poly electrode 101a of the Zener diode constituting the clamp diode 101. For example, the polysilicon film is formed by a low pressure CVD method (600 to 650 ° C.) by a thermal decomposition reaction of SiH 4. , On the entire surface of the gate insulating film 302. The polysilicon film and the gate insulating film are selectively etched using a photo-etching technique to form an opening for a contact hole.

After covering the entire surface of the wafer in this state with an insulating interlayer film 305 of, for example, a phosphorus glass film (PSG), the insulating interlayer film 305 is flattened by an etch-back method or the like.
Further, the insulating interlayer film 305 is selectively etched using a photoetching technique to form a contact hole. Thereafter, Al is deposited and patterned by etching to form an emitter electrode 311 and a gate electrode 3.
12 and the cathode electrode 130, and P +
By forming the drain electrode D on the back surface of the sub-substrate 201, an IGBT chip having a structure as shown in FIG. 2 is obtained. Note that a passivation film is provided on the chip on which these electrodes are formed (not shown).

According to the IGBT chip of the present embodiment, in the IGBT and the IGBT with a built-in reverse diode having a lateral structure in which the diode is integrated into one chip, the current path of the reverse diode (the anode By making the surface concentration of the IF (between the cathodes) higher than the bulk (N-epi layer 202) concentration, the resistance between the anode and the cathode is reduced, so that the IF-VF characteristics are improved.

[0039]

As described above in detail, according to the first aspect, the impurity surface concentration between the ring-shaped diffusion region and the channel stopper region, which are the current paths of the diode, can be reduced.
Since it was set higher than the low concentration layer, the IF-V
F characteristics can be improved. This makes it possible to realize, for example, a monolithic high-voltage IGBT.

According to the second invention, in the first invention, when the impurity concentration of the low-concentration layer is about 3E14 cm ³ , the ring-shaped diffusion region and the channel stopper region, which are the conduction paths of the diode, The impurity surface concentration during
4E15 cm Cm ³ or less, so a general 50
In a 0 V system device, the IF-VF characteristics of the diode can be improved without lowering the bulk breakdown voltage.

[Brief description of the drawings]

FIG. 1 is a plan view of a lateral structure IGBT chip according to an embodiment of a semiconductor device of the present invention before a gate insulating film is formed.

FIG. 2 is a cross-sectional view of the IGBT chip shown in FIG.

FIG. 3 is a plan view of a conventional IGBT chip with a built-in reverse diode (lateral structure).

FIG. 4 is a circuit diagram of the IGBT having the lateral structure shown in FIG.

FIG. 5 is a plan view of the lateral structure IGBT chip shown in FIG. 3 before a gate insulating film 302 is formed.

FIG. 6 is a cross-sectional view of the IGBT chip shown in FIGS. 3 and 5;
It is A 'sectional drawing.

[Explanation of symbols]

 101 Clamp diode 101a Polysilicon film 130 Cathode electrode of reverse diode 201 P + Sub-substrate 202 N-epitaxial layer 204 P + diffusion layer under gate pad 205 Guard ring P + diffusion layer 206 P base layer 207, 208, 209 P + + Diffusion layer 211,212 N ++ diffusion layer 300 IGBT region 301 oxide film 302 gate oxide film 304 gate poly electrode 305 interlayer insulating film 311 Al emitter electrode 312 gate electrode 400 reverse diode

Claims (2)

[Claims] A high-concentration first-conductivity-type semiconductor substrate; a second-conductivity-type low-concentration layer formed on a main surface of the semiconductor substrate;
A base region composed of a first conductivity type low concentration impurity layer partially provided on the upper surface of the low concentration layer and a second conductivity type high concentration impurity layer partially provided on the surface of the base region A ring region formed of a high-concentration impurity layer of a first conductivity type formed on an upper surface of the low-concentration layer; and a second conductivity type formed on the outer periphery of the ring-shaped diffusion region. A channel stopper region comprising a high-concentration impurity layer, wherein the ring-shaped diffusion region is an anode region, and the channel stopper region is a cathode region. A semiconductor device, wherein the impurity surface concentration between the diffusion region and the channel stopper region is set higher than that of the low concentration layer. 2. The low-concentration layer has an impurity concentration of 3E14 cores.
If it is m ³ approximately, the claims, characterized in that the impurity surface concentration between the ring-shaped diffusion region is a current path of the diode and the channel stopper region, was set below about 4E15 co Cm ³ 2. The semiconductor device according to 1.