CA1056070A - Method of making an ic structure having both power and signal components - Google Patents
Method of making an ic structure having both power and signal componentsInfo
- Publication number
- CA1056070A CA1056070A CA245,432A CA245432A CA1056070A CA 1056070 A CA1056070 A CA 1056070A CA 245432 A CA245432 A CA 245432A CA 1056070 A CA1056070 A CA 1056070A
- Authority
- CA
- Canada
- Prior art keywords
- region
- signal
- power
- epitaxial layer
- conductivity type
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000004519 manufacturing process Methods 0.000 title description 5
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 7
- 238000002955 isolation Methods 0.000 claims abstract description 6
- 239000012535 impurity Substances 0.000 claims description 4
- 238000009792 diffusion process Methods 0.000 description 12
- 230000015556 catabolic process Effects 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/082—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
- H01L27/0823—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only including vertical bipolar transistors only
- H01L27/0825—Combination of vertical direct transistors of the same conductivity type having different characteristics,(e.g. Darlington transistors)
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0821—Collector regions of bipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
An integrated circuit and method in which optimized power and signal components are incorporated into a mono-lithic structure. A suitable semiconductor substrate has an epitaxial layer of one conductivity type and having a relatively high resistivity formed thereon. Isolation means extend through the epitaxial layer and separate it into at least a signal transistor region and a power transistor region. A diffused pocket region is formed in the signal transistor region of the same conductivity type as the epitaxial layer but doped so as to provide a region of relatively low resistivity. A power transistor is formed in the relatively high resistivity power transistor region and a signal transistor is formed in the relatively low resistivity diffused pocket region.
An integrated circuit and method in which optimized power and signal components are incorporated into a mono-lithic structure. A suitable semiconductor substrate has an epitaxial layer of one conductivity type and having a relatively high resistivity formed thereon. Isolation means extend through the epitaxial layer and separate it into at least a signal transistor region and a power transistor region. A diffused pocket region is formed in the signal transistor region of the same conductivity type as the epitaxial layer but doped so as to provide a region of relatively low resistivity. A power transistor is formed in the relatively high resistivity power transistor region and a signal transistor is formed in the relatively low resistivity diffused pocket region.
Description
This invention pertains to an integrated circuit in-cluding both power and signal components in a monolithic structure, and a method for making the same As is known, fabrication of signal components and fabrication of power components in an integrated circuit environment entail differing considerations. That is, it is not po~sible to utilize a single semiconductor substrate having uniform characteristics and form~ with nothing further, optimized power and signal components therein. There have been previous approaches to fabrication of power and signal components on the same semiconductor chip. These have, however, involved additional proce~sing steps and are usually costly or difficult to control and constitute significant deparatures from standard indu~try production techniques One example of such a prior art arrangement is given in "Technology for Monolithic High-Power Integrated Circuits Using Polycrystalline Si for Collector and Isola-tion Wall8" by I. Kobayashi in IEEE TRANSACTIONS OU ELECTRO~
-DEVICES, Vol ED20, #4, April 1973, pp. 399-404.
It i~ an object of this invention to provide an in-tegrated circuit and method incorporating both power and signal components on the same semiconductor chip and utilizing simplified process ~tepq common to existing technology.
It is a specific object of this invention to provide such an integrated circuit and method for incorporating on the same s~miconductor chip high voltage breakdown power devices o~ low to medium gain and low voltage breakdown devices of higher gain.
Briefly, in accordance with one embodiment of the invention, an epitaxial layer of relatively high resiætivity is formed on a semiconductor substrate. Isolation regions - 1 _ ~ . -- . .
1~ S ~ ~l RD_7087 extend through the epitaxial layer and separate it into at least one power transistor region and at least one signal transistor region. A diffused pocket region of the same conductivity type as the epitaxial layer but having a significantly lower resistivity is formed in the signal transistor region of the epitaxial layer. Thereafter, a power transistor is formed in the power transistor region and a signal transistor is formed in the diffused pocXet region FIGURES 1 through 7 are diagrammatic cross-sections illustrating sequential steps in the formation of an in-tegrated circuit in accordance with this invention.
Turning now to the drawings, in accord with the invention, a semiconductor substrate 11 is provided of a first con-ductivity typejj i.e., p-type in this example. Diffusions of an n-type conductivity type material can be made to form the n-type regions 12 and 13, which are utilized to form buried layers for the final structure, in a manner known to those skilled in this art. ~hereafter, and as specifically illustrated in FIGURE 2, an epitaxial layer 14 of n- is grown on top of the semiconductor substrate 11. During this epitaxial growth, the n-type region~ 12 and 13 diffuse partially into the epitaxial layer, as shown in FIGURE 2 Thereafter~ and as particularly shown in FIGURE 3, isolation regions 16, 17 and 18 are formed by p-type diffusions through the epitaxial layer 14 These isolation means define at least one power device region generally indicated by reference numeral 19 and at least one signal transistor region generally indicated by reference numeral 20 These power and signal tran~istor regions 19 and 20 are illustrated in cross section in Figure 3, but in planar extent may, of course, be circular, square~ rectangular, etc., as desired.
Throughout this discussion and in the drawings, the conventional photolithographic masking and etching tech-nique6 and steps are omitted both from the drawings and from the discussion of same. These techni~ues and steps are conventional and well known to those skilled in this art The epitaxial layer 14 i8 formed to have a relatively high resistivity~ i.e. greater than 5 ohm-cm and in accord-ance with a specific example has a resistivity of 20 ohm-cm Thi~ high resi~tivity epitaxial material in the power device region is left as is. However, in the signal tran-sistor region 20 an additional n-type diffusion is made to ;., "" ~, .
form a diffused pocket region 21, as shown in Figure 4.
Thi~ ~elective enhancement doping is carried out with an impurity concentration such that the resulting diffused pocket region 21 will have a relatively low resistivity, i e less than 1 ohm-cm, and in accordance with a ~pecific example 0.6 ohm_cm. As shown in Figure 4, the diffusion pocket region 21 extends only partially down through the epitaxial layer 14. Depending upon specific applications, if high currents are required for the signal transistor and a low ~aturation voltage is desired, then conversion of the entire thicknes~ of the epitaxial layer in the signal tran-sistor region 20 to the lower resi~t~vity might be more desirable As a practical matter these deep diffusions must be weighted against the required low surface concentrations and reasonable diffusion times.
In forming the diffused pocket region 21, the surface ~ -concentration and the diffusion time can be controlled~ as known to tho~e skilled in this art, to vary the degree to which the resistivity is lowered in the diffused pocket region 21. By way of a specific example, 20 ohm-cm ~7~
epitaxial material can be converted to an average resistivity of o.6 ohm_cm by an appropriate diffusion. Practical con-~traints are the desire to keep the remaining process steps identical, yet obtain both power and signal devices with desired optimized characteristics ~
The surface concentration of the diffused pocket ~-region 21 must be low enough to allow a conver~ion to a p-type ba~e region by a normal base diffusion. Figure 5 shows the next step in the process, which is formation of the base regions in both the power transistor region and in the signal transistor region, i.e , in diffused pocket region 21 ~here i~ thus formed the base region 22 for the power transistor and the base region 23 for the signal transistor. As ~hown in Figure 5, a more shallow base depth occurs in the diffused pocket region 21 due to the higher impurity concentration. Depending upon the parti-cular characteristics desired, if the more shallow ba~e depth which occurs from simultaneous formation of the ~ignal transistor ba~e with the power transistor base region i8 not atisfactory, two separate base diffusions can al-ternatively be performed This, of course, ha~ the dis_ advantage of reqyiring an extra processing step. With the resistivitie~ in accordance with the ~pecific example (20 ohm_cm for the epitaxial layer with the diffused pocket region having a resistivity of o.6 ohm-cm) a base width of from 4 to 5 microns results for the power transistor ~ase 22 and a base width of from 2 to 3 microns for the signal transistor base region 23 Thereafter, and as shown in Figure 6, emitter regions 2i and 25 are formed by an appropriate n-type impurity diffusion And, a~ ~hown in Figure 7, deep collector con-tacts or '`sinkers" 26 and 27 are formed extending down to l(~S~D ~
and making contact with the buried layers 12 and 13.
The resulting structure, a~ shown schematically in Figure 7, is a monolithic integrated circuit having a power transistor formed in relatively high resistivity epitaxtal material and having emitter, base, and collector terminals Ep, Bp and Cp; and a signal transistor formed in a relatively low resistivity diffused pocket region and having emitter base and collector terminals designated Es, and Bs and Cs In accordance with the invention a relatively thick epitaxial layer 14 is utilized and a relatively deep base diffusion 22 i8 provided to avoid electric field breaX-down due to curvature and achieve a power device having a high breakdown voltage, on the order of for example 500 volt~ By ~elective enhancement of the resistivity by additional doping forming the diffused pocket region 21 in the signal transistor region, however, a high gain signal transistor can be simultaneously fabricated with the power transistor, and in accordance with this specific example has a breakdown voltage on the order of 60 volts While this invention has been described with respect to a preferred embodiments, it should be obvious to those ~ -~killed in th$~ art that modifications may be made to the particularly described embodiment without departing from the true spirit and scope of the invention
-DEVICES, Vol ED20, #4, April 1973, pp. 399-404.
It i~ an object of this invention to provide an in-tegrated circuit and method incorporating both power and signal components on the same semiconductor chip and utilizing simplified process ~tepq common to existing technology.
It is a specific object of this invention to provide such an integrated circuit and method for incorporating on the same s~miconductor chip high voltage breakdown power devices o~ low to medium gain and low voltage breakdown devices of higher gain.
Briefly, in accordance with one embodiment of the invention, an epitaxial layer of relatively high resiætivity is formed on a semiconductor substrate. Isolation regions - 1 _ ~ . -- . .
1~ S ~ ~l RD_7087 extend through the epitaxial layer and separate it into at least one power transistor region and at least one signal transistor region. A diffused pocket region of the same conductivity type as the epitaxial layer but having a significantly lower resistivity is formed in the signal transistor region of the epitaxial layer. Thereafter, a power transistor is formed in the power transistor region and a signal transistor is formed in the diffused pocXet region FIGURES 1 through 7 are diagrammatic cross-sections illustrating sequential steps in the formation of an in-tegrated circuit in accordance with this invention.
Turning now to the drawings, in accord with the invention, a semiconductor substrate 11 is provided of a first con-ductivity typejj i.e., p-type in this example. Diffusions of an n-type conductivity type material can be made to form the n-type regions 12 and 13, which are utilized to form buried layers for the final structure, in a manner known to those skilled in this art. ~hereafter, and as specifically illustrated in FIGURE 2, an epitaxial layer 14 of n- is grown on top of the semiconductor substrate 11. During this epitaxial growth, the n-type region~ 12 and 13 diffuse partially into the epitaxial layer, as shown in FIGURE 2 Thereafter~ and as particularly shown in FIGURE 3, isolation regions 16, 17 and 18 are formed by p-type diffusions through the epitaxial layer 14 These isolation means define at least one power device region generally indicated by reference numeral 19 and at least one signal transistor region generally indicated by reference numeral 20 These power and signal tran~istor regions 19 and 20 are illustrated in cross section in Figure 3, but in planar extent may, of course, be circular, square~ rectangular, etc., as desired.
Throughout this discussion and in the drawings, the conventional photolithographic masking and etching tech-nique6 and steps are omitted both from the drawings and from the discussion of same. These techni~ues and steps are conventional and well known to those skilled in this art The epitaxial layer 14 i8 formed to have a relatively high resistivity~ i.e. greater than 5 ohm-cm and in accord-ance with a specific example has a resistivity of 20 ohm-cm Thi~ high resi~tivity epitaxial material in the power device region is left as is. However, in the signal tran-sistor region 20 an additional n-type diffusion is made to ;., "" ~, .
form a diffused pocket region 21, as shown in Figure 4.
Thi~ ~elective enhancement doping is carried out with an impurity concentration such that the resulting diffused pocket region 21 will have a relatively low resistivity, i e less than 1 ohm-cm, and in accordance with a ~pecific example 0.6 ohm_cm. As shown in Figure 4, the diffusion pocket region 21 extends only partially down through the epitaxial layer 14. Depending upon specific applications, if high currents are required for the signal transistor and a low ~aturation voltage is desired, then conversion of the entire thicknes~ of the epitaxial layer in the signal tran-sistor region 20 to the lower resi~t~vity might be more desirable As a practical matter these deep diffusions must be weighted against the required low surface concentrations and reasonable diffusion times.
In forming the diffused pocket region 21, the surface ~ -concentration and the diffusion time can be controlled~ as known to tho~e skilled in this art, to vary the degree to which the resistivity is lowered in the diffused pocket region 21. By way of a specific example, 20 ohm-cm ~7~
epitaxial material can be converted to an average resistivity of o.6 ohm_cm by an appropriate diffusion. Practical con-~traints are the desire to keep the remaining process steps identical, yet obtain both power and signal devices with desired optimized characteristics ~
The surface concentration of the diffused pocket ~-region 21 must be low enough to allow a conver~ion to a p-type ba~e region by a normal base diffusion. Figure 5 shows the next step in the process, which is formation of the base regions in both the power transistor region and in the signal transistor region, i.e , in diffused pocket region 21 ~here i~ thus formed the base region 22 for the power transistor and the base region 23 for the signal transistor. As ~hown in Figure 5, a more shallow base depth occurs in the diffused pocket region 21 due to the higher impurity concentration. Depending upon the parti-cular characteristics desired, if the more shallow ba~e depth which occurs from simultaneous formation of the ~ignal transistor ba~e with the power transistor base region i8 not atisfactory, two separate base diffusions can al-ternatively be performed This, of course, ha~ the dis_ advantage of reqyiring an extra processing step. With the resistivitie~ in accordance with the ~pecific example (20 ohm_cm for the epitaxial layer with the diffused pocket region having a resistivity of o.6 ohm-cm) a base width of from 4 to 5 microns results for the power transistor ~ase 22 and a base width of from 2 to 3 microns for the signal transistor base region 23 Thereafter, and as shown in Figure 6, emitter regions 2i and 25 are formed by an appropriate n-type impurity diffusion And, a~ ~hown in Figure 7, deep collector con-tacts or '`sinkers" 26 and 27 are formed extending down to l(~S~D ~
and making contact with the buried layers 12 and 13.
The resulting structure, a~ shown schematically in Figure 7, is a monolithic integrated circuit having a power transistor formed in relatively high resistivity epitaxtal material and having emitter, base, and collector terminals Ep, Bp and Cp; and a signal transistor formed in a relatively low resistivity diffused pocket region and having emitter base and collector terminals designated Es, and Bs and Cs In accordance with the invention a relatively thick epitaxial layer 14 is utilized and a relatively deep base diffusion 22 i8 provided to avoid electric field breaX-down due to curvature and achieve a power device having a high breakdown voltage, on the order of for example 500 volt~ By ~elective enhancement of the resistivity by additional doping forming the diffused pocket region 21 in the signal transistor region, however, a high gain signal transistor can be simultaneously fabricated with the power transistor, and in accordance with this specific example has a breakdown voltage on the order of 60 volts While this invention has been described with respect to a preferred embodiments, it should be obvious to those ~ -~killed in th$~ art that modifications may be made to the particularly described embodiment without departing from the true spirit and scope of the invention
Claims (3)
1. A method of forming an integrated circuit including the steps of providing a semiconductor substrate of a first conductivity type, growing an epitaxial layer of a second conductivity type and having a relatively high resistivity on the substrate, forming isolation regions of the first conductivity type extending through the epitaxial layer and separating it into at least a signal transistor region and at least a power transistor region, forming a diffused pocket region having a relatively low resistivity in the signal transistor region, forming a power transistor in the power transistor region and a signal transistor in the signal transistor region.
2. A method in accordance with claim 1, wherein the epitaxial region is grown to have a resistivity greater than 5 ohm-cm and the diffused pocket region is formed by diffusing impurities of the second conductivity type into the signal transistor region to form the diffused pocket region with a resulting relatively low resistivity less than 1 ohm-cm.
3. A method in accordance with claim 1, wherein the at least one power transistor and the at least one signal transistor are simultaneously formed by simultaneously diffusing the base regions thereof, the emitter regions thereof, and the collector contacts thereof.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US55295475A | 1975-02-25 | 1975-02-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1056070A true CA1056070A (en) | 1979-06-05 |
Family
ID=24207513
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA245,432A Expired CA1056070A (en) | 1975-02-25 | 1976-02-10 | Method of making an ic structure having both power and signal components |
Country Status (5)
| Country | Link |
|---|---|
| JP (1) | JPS51109781A (en) |
| CA (1) | CA1056070A (en) |
| DE (2) | DE2607089A1 (en) |
| GB (1) | GB1534338A (en) |
| NL (1) | NL7601900A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4047220A (en) * | 1975-12-24 | 1977-09-06 | General Electric Company | Bipolar transistor structure having low saturation resistance |
| US4207326A (en) * | 1979-05-21 | 1980-06-10 | Cilag-Chemie A.G. | Antimicrobial quaternary pyrazole derivatives |
| KR100256169B1 (en) * | 1996-01-16 | 2000-05-15 | 다니구찌 이찌로오, 기타오카 다카시 | Semiconductor device and method for manufacturing the same |
| US6566217B1 (en) | 1996-01-16 | 2003-05-20 | Mitsubishi Denki Kabushiki Kaisha | Manufacturing process for semiconductor device |
-
1976
- 1976-02-10 CA CA245,432A patent/CA1056070A/en not_active Expired
- 1976-02-11 GB GB529676A patent/GB1534338A/en not_active Expired
- 1976-02-21 DE DE19762607089 patent/DE2607089A1/en active Pending
- 1976-02-21 DE DE19767605242 patent/DE7605242U1/en not_active Expired
- 1976-02-24 NL NL7601900A patent/NL7601900A/en not_active Application Discontinuation
- 1976-02-24 JP JP51018539A patent/JPS51109781A/ja active Pending
Also Published As
| Publication number | Publication date |
|---|---|
| GB1534338A (en) | 1978-12-06 |
| NL7601900A (en) | 1976-08-27 |
| DE2607089A1 (en) | 1976-09-16 |
| DE7605242U1 (en) | 1976-09-02 |
| JPS51109781A (en) | 1976-09-28 |
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