EP0244452A1 - Subcollector for bipolar transistors - Google Patents

Subcollector for bipolar transistors

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Publication number
EP0244452A1
EP0244452A1 EP19860906377 EP86906377A EP0244452A1 EP 0244452 A1 EP0244452 A1 EP 0244452A1 EP 19860906377 EP19860906377 EP 19860906377 EP 86906377 A EP86906377 A EP 86906377A EP 0244452 A1 EP0244452 A1 EP 0244452A1
Authority
EP
European Patent Office
Prior art keywords
silicon
layer
substrate
cobalt
collector
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19860906377
Other languages
German (de)
French (fr)
Inventor
Raymond Edward Oakley
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Plessey Overseas Ltd
Original Assignee
Plessey Overseas Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Plessey Overseas Ltd filed Critical Plessey Overseas Ltd
Publication of EP0244452A1 publication Critical patent/EP0244452A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/761—PN junctions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02491—Conductive materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/66272—Silicon vertical transistors

Definitions

  • This invention relates to bipolar transistors and to integrated circuits incorporating such transistors.
  • the series resistance of the collectors of NPN' transistors has hitherto been kept to a relatively low value by providing in one or more selected regions beneath an epitaxially grown N-type layer a heavily doped N+ layer (i.e. so-called buried N+ layer) which acts as a collector shunt.
  • a heavily doped N+ layer i.e. so-called buried N+ layer
  • the shunt layer will already be doped to the maximum level so that lower resistance can only be achieved by increased thickness.
  • a method of fabricating bipolar transistors which enables both the capacitance and resistance associated with the transistor collector to be kept to low values and which comprises the steps of producing on a silicon substrate of one conductivity type silicon, a collector shunt of cobalt disilicide or of any other material having a good lattice match to silicon and compatible with conventional silicon integrated circuit processes, subsequently growing epitaxially on to said collector shunt and substrate a layer of opposite type conductivity silicon and subsequently forming by conventional techniques the base, emitter and collector regions of the transistor in the epitaxially grown layer of silicon.
  • cobalt may be deposited on to the aforesaid silicon substrate through an opening provided in a preferably grown silicon dioxide mask layer after which the substrate may be heat treated to form a region of cobalt disilicide. Any excess cobalt on the oxide mask and the mask itself may then be removed before silicon of opposite type conductivity is grown epitaxially on to the cobalt disilicide defining what will be the collector shunt.
  • a layer of cobalt material is deposited directly on to the silicon substrate of one type conductivity.
  • the layer of cobalt is then removed, as by etching, apart from the region where the collector shunt is to be formed and the substrate with the shunt thereon may then be heat treated to produce the cobalt disilicide region.
  • a layer of opposite type conductivity silicon is then grown epitaxially on to the cobalt disilicide shunt and substrate.
  • Figure 1 is a diagrammatic cross-sectional view of a known construction of bipolar transistor
  • Figure 2 is a view corresponding to that of Figure 1 of a bipolar transistor constructed in accordance with the present invention.
  • FIGS 3 and 4 illustrate the steps of alternative processes for fabricating the transistor of Figure 2.
  • this shows a known form of NPN bipolar transistor which comprises a silicon substrate 1 of P-type conductivity having a buried N+ collector shunt region 2, to be described later, on which is epitaxially grown a layer of silicon 3 of N-type conductivity.
  • the silicon layer 3 has formed thereon by diffusion a base region 4 of P-type conductivity and emitter and collector regions 5 and 6, respectively, of N-type conductivity material.
  • the resistance and capacitance associated with the collector and represented by the series resistance R and sidewall capacitance C impose a limitation on the speed of operation and power performance of the transistor and any integrated circuits embodying such transistors.
  • the collector series resistance R is kept relatively low by providing the heavily doped buried N+ layer beneath the epitaxy so that the layer acts as a collector shunt.
  • the layer is already doped to the maximum so that a lower resistance can only be achieved by increased thickness of the layer.
  • the increase in thickness produces an increase in the sidewall capacitance C which is the dominant component of collector capacitance at the dimensions used in present day integrated circuits.
  • FIG. 2 of t drawings shows a bipolar transistor constructed in accordance with the present invention.
  • a silicon substrate 7 of P-type conductivity has a relatively thin region 8 of cobalt disilicide provided thereon on which is grown an epitaxial layer of silicon 9 of N-type conductivity.
  • a base 10 of P-type conductivity and emitter 11 and collector 12 of N-type conductivity are formed in the epitaxially grown layer of silicon 9.
  • the cobalt disilicide 8 which replaces the heavily doped buried N+ type collector shunt 2 of Figure 1 transistor has a relatively low resistance and capacitance compared to the shunt of Figure 1. It is envisaged that shunts of material other than cobalt disilicide could be provided without departing from the spirit of the invention - the material concerned meeting the requirement of low bulk resistivity and compatibility with SIC processes and the growth thereon of epitaxial layers of silicon.
  • a mask of silicon dioxide 13 is grown on to a substrate 14 of silicon of P-type conductivity with an opening 15 being cut away or otherwise provided for forming the collector shunt.
  • a layer of cobalt 16 is then deposited, as by sputtering, on to the exposed substrate 14 within the opening 15 and the peripheral region of the oxide mask 13 as" shown in Figure 3(b).
  • a layer 19 of cobalt is deposited as by sputtering on to a P-type conductivity silicon layer 20. Part of the cobalt is removed as by etching to leave an upstanding region 21 as shown in Figure 4(b).
  • the silicon substrate and cobalt attachment is then heated to a relatively high temperature (e.g. 700°C) to cause the cobalt and silicon to combine to form a region 22 of cobalt disilicide as shown in Figure 4(c).
  • a relatively high temperature e.g. 700°C
  • a layer 23 of silicon of N-type conductivity is grown epitaxially on to the substrate to leave the collector shunt region 22 enclosed within the silicon structure. Thereafter the base 10, emitter 11 and collector 12 of the transistor of Figure 2 will be provided by dopant diffusion as in well-known SIC processes.
  • a relatively large substrate of P-type conductivity may be provided with a layer of cobalt disilicide over one entire surface on to which a layer of N-type conductivity is grown epitaxially.
  • N-type silicon with their own individual collector shunts (cobalt disilicide) are provided. " The isolated regions may then be provided with base, emitter and collector regions as in the embodiments already described, thereby defining a plurality of isolated bi-polar transistors. The grooves or trenches may if desired be filled with suitable dielectric material.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

Procédé de fabrication de transistors bipolaires consistant à produire sur un substrat en silicium d'un type déterminé de conductivité une dérivation de collecteur (22) en bisiliciure de cobalt ou tout autre matériau présentant une bonne correspondance avec le réseau cristallin du silicium et compatible avec les procédés conventionnels de production de circuits intégrés en silicium, à provoquer par la suite sur la dérivation du collecteur et sur le substrat la croissance épitaxiale d'une couche (18) en silicium présentant une conductivité de type opposé et à former ensuite par des techniques conventionnelles les régions de base (10), d'émetteur (11) et de collecteur (8, 12) du transistor dans la couche de silicium obtenue par croissance épitaxiale.Method for manufacturing bipolar transistors consisting in producing on a silicon substrate of a determined type of conductivity a collector bypass (22) made of cobalt bisilicide or any other material having a good correspondence with the crystal lattice of silicon and compatible with conventional processes for the production of integrated silicon circuits, to subsequently cause the epitaxial growth of a silicon layer (18) having an opposite type conductivity on the collector branch and on the substrate and then to form by conventional techniques the base (10), emitter (11) and collector (8, 12) regions of the transistor in the silicon layer obtained by epitaxial growth.

Description

Subcollector for bipolar transistors.
This invention relates to bipolar transistors and to integrated circuits incorporating such transistors.
The speed of operation and power performance of bipolar transistors and integrated circuits embodying such transistors are limited by the electrical capacitance and electrical resistance associated with the usual collectors of the transistors.
With a view to reducing the aforesaid electrical capacitance and resistance thereby to achieve an improvement in the speed and power performance of the transistors the series resistance of the collectors of NPN' transistors has hitherto been kept to a relatively low value by providing in one or more selected regions beneath an epitaxially grown N-type layer a heavily doped N+ layer (i.e. so-called buried N+ layer) which acts as a collector shunt. However- there is an inevitable compromise between the resistance and capacitance of the shunt layer. The shunt layer will already be doped to the maximum level so that lower resistance can only be achieved by increased thickness. Any increase in thickness, however, produces an increase in the so-called sidewall capacitance which is the dominant component of collector capacitance at the dimensions used in present day integrated circuits. According to J:he present invention there is provided a method of fabricating bipolar transistors which enables both the capacitance and resistance associated with the transistor collector to be kept to low values and which comprises the steps of producing on a silicon substrate of one conductivity type silicon, a collector shunt of cobalt disilicide or of any other material having a good lattice match to silicon and compatible with conventional silicon integrated circuit processes, subsequently growing epitaxially on to said collector shunt and substrate a layer of opposite type conductivity silicon and subsequently forming by conventional techniques the base, emitter and collector regions of the transistor in the epitaxially grown layer of silicon. In carrying out the present invention cobalt may be deposited on to the aforesaid silicon substrate through an opening provided in a preferably grown silicon dioxide mask layer after which the substrate may be heat treated to form a region of cobalt disilicide. Any excess cobalt on the oxide mask and the mask itself may then be removed before silicon of opposite type conductivity is grown epitaxially on to the cobalt disilicide defining what will be the collector shunt.
In an alternative method of carrying out the method according to the present invention a layer of cobalt material is deposited directly on to the silicon substrate of one type conductivity. The layer of cobalt is then removed, as by etching, apart from the region where the collector shunt is to be formed and the substrate with the shunt thereon may then be heat treated to produce the cobalt disilicide region. A layer of opposite type conductivity silicon is then grown epitaxially on to the cobalt disilicide shunt and substrate.
By way of example the present invention will now be described with reference to the accompanying drawings in which:
Figure 1 is a diagrammatic cross-sectional view of a known construction of bipolar transistor;
Figure 2 is a view corresponding to that of Figure 1 of a bipolar transistor constructed in accordance with the present invention; and,
Figures 3 and 4 illustrate the steps of alternative processes for fabricating the transistor of Figure 2.
Referring to Figure 1, this shows a known form of NPN bipolar transistor which comprises a silicon substrate 1 of P-type conductivity having a buried N+ collector shunt region 2, to be described later, on which is epitaxially grown a layer of silicon 3 of N-type conductivity. The silicon layer 3 has formed thereon by diffusion a base region 4 of P-type conductivity and emitter and collector regions 5 and 6, respectively, of N-type conductivity material.
* In bipolar transistors the resistance and capacitance associated with the collector and represented by the series resistance R and sidewall capacitance C impose a limitation on the speed of operation and power performance of the transistor and any integrated circuits embodying such transistors. In the transistor shown in Figure 1 the collector series resistance R is kept relatively low by providing the heavily doped buried N+ layer beneath the epitaxy so that the layer acts as a collector shunt. There is an inevitable compromise between the resistance R and the capacitance C of the N+ layer. The layer is already doped to the maximum so that a lower resistance can only be achieved by increased thickness of the layer. Unfortunately, the increase in thickness produces an increase in the sidewall capacitance C which is the dominant component of collector capacitance at the dimensions used in present day integrated circuits. This problem is alleviated in accordance with the invention by providing as the collector shunt a material which has a very low bulk resistivity and which is compatible with silicon integrated circuit processes and on which epitaxial silicon can be grown. Referring now to Figure 2 of t drawings, this shows a bipolar transistor constructed in accordance with the present invention. In this Figure a silicon substrate 7 of P-type conductivity has a relatively thin region 8 of cobalt disilicide provided thereon on which is grown an epitaxial layer of silicon 9 of N-type conductivity. By known diffusion steps a base 10 of P-type conductivity and emitter 11 and collector 12 of N-type conductivity are formed in the epitaxially grown layer of silicon 9.
The cobalt disilicide 8 which replaces the heavily doped buried N+ type collector shunt 2 of Figure 1 transistor has a relatively low resistance and capacitance compared to the shunt of Figure 1. It is envisaged that shunts of material other than cobalt disilicide could be provided without departing from the spirit of the invention - the material concerned meeting the requirement of low bulk resistivity and compatibility with SIC processes and the growth thereon of epitaxial layers of silicon.
As regards the fabrication of the transistor of Figure 2 reference will now be made to Figure 3 of the drawings illustrating one sequence of steps involved in the fabrication process.
As shown in Figure 3(a) a mask of silicon dioxide 13 is grown on to a substrate 14 of silicon of P-type conductivity with an opening 15 being cut away or otherwise provided for forming the collector shunt. A layer of cobalt 16 is then deposited, as by sputtering, on to the exposed substrate 14 within the opening 15 and the peripheral region of the oxide mask 13 as" shown in Figure 3(b).
During heat treatment which follows the cobalt and the silicon of the substrate within the mask opening 15 combine to form a region of cobalt disilicide as illustrated at 17 in Figure 3(c). The oxide mask material and the excess cobalt is then removed to leave the configuration shown in Figure 3(d) after which a layer 18 of silicon of N-type conductivity is grown on to the substrate and cobalt disilicide as shown in Figure 3(e). Thereafter the base 10, emitter 11 and collector 12 of the Figure 2 transistor will be formed by diffusion of dopants into the upper surface of the grown layer of silicon 18 in accordance with well-known techniques.
Referring now to Figure 4 of the drawings, this shows the steps in an alternative process for producing the transistor of Figure 2.
In the first step as shown in Figure 4(a) a layer 19 of cobalt is deposited as by sputtering on to a P-type conductivity silicon layer 20. Part of the cobalt is removed as by etching to leave an upstanding region 21 as shown in Figure 4(b).
The silicon substrate and cobalt attachment is then heated to a relatively high temperature (e.g. 700°C) to cause the cobalt and silicon to combine to form a region 22 of cobalt disilicide as shown in Figure 4(c).
As shown in Figure 4(d) a layer 23 of silicon of N-type conductivity is grown epitaxially on to the substrate to leave the collector shunt region 22 enclosed within the silicon structure. Thereafter the base 10, emitter 11 and collector 12 of the transistor of Figure 2 will be provided by dopant diffusion as in well-known SIC processes.
In a further embodiment of the present invention a relatively large substrate of P-type conductivity may be provided with a layer of cobalt disilicide over one entire surface on to which a layer of N-type conductivity is grown epitaxially. By cutting appropriately positioned deep grooves or trenches through the layer of N-type silicon and cobalt disilicide and extending into the substrate, isolated regions of the epitaxially grown
N-type silicon with their own individual collector shunts (cobalt disilicide) are provided." The isolated regions may then be provided with base, emitter and collector regions as in the embodiments already described, thereby defining a plurality of isolated bi-polar transistors. The grooves or trenches may if desired be filled with suitable dielectric material.

Claims

- 9 -CLAIMS :
1. A method of fabricating bipolar transistors comprising the steps of producing on a silicon substrate of one conductivity type silicon, a collector shunt of cobalt disilicide or of any other material having a good lattice match to silicon and compatible with conventional silicon integrated circuit processes, subsequently growing epitaxially on to said collector shunt and substrate a layer of opposite type conductivity silicon and subsequently forming by conventional techniques the base, emitter and collector regions of the transistor in the epitaxially grown layer of silicon.
2. A method of fabricating bipolar transistors as claimed in claim 1, in which cobalt is deposited on to the silicon substrate through an opening provided in a preferably grown silicon dioxide mask layer after which the substrate is heat treated to form a region of cobalt disilicide
3. A method of fabricating bipolar transistors as claimed in claim 2, in which any excess cobalt on the oxide mask and the mask itself is removed before silicon of opposite type conductivity is grown epitaxially on to the cobalt disilicide to define the collector shunt.
4. A method of fabricating bipolar transistors as claimed in claim 1, in which a layer of cobalt material is deposited directly on to the silicon substrate of one type conductivity after which the layer of cobalt is removed, as by etching, apart from the region where the collector shunt is to be formed and the substrate with the shunt thereon is then heat treated to produce the cobalt disilicide region after which a layer of opposite type conductivity silicon is grown epitaxially on to the cobalt disilicide shunt and substrate.
5. A method of fabricating bipolar transistors as claimed in claim 1, in which a relatively large substrate of P-type conductivity is provided with a layer of cobalt disilicide over one entire surface on to which a layer of N-type conductivity is grown epitaxially, in which deep grooves or trenches are cut through the layer of N-type silicon and cobalt disilicide at appropriate positions so that the grooves extend into the substrate whereby a plurality of isolated regions of the epitaxially grown N-type silicon having their own individual collector shunts of cobalt disilicide are provided, and in which the isolated regions are provided with base, emitter and collector regions in order to define a plurality of isolated bi-polar transistors.
6. Bipolar transistors fabricated by the method according to any of claims 1 to 5.
EP19860906377 1985-10-19 1986-10-20 Subcollector for bipolar transistors Withdrawn EP0244452A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB08525848A GB2181889A (en) 1985-10-19 1985-10-19 Improvements relating to bipolar transistors
GB8525848 1985-10-19

Publications (1)

Publication Number Publication Date
EP0244452A1 true EP0244452A1 (en) 1987-11-11

Family

ID=10586959

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19860906377 Withdrawn EP0244452A1 (en) 1985-10-19 1986-10-20 Subcollector for bipolar transistors

Country Status (3)

Country Link
EP (1) EP0244452A1 (en)
GB (1) GB2181889A (en)
WO (1) WO1987002510A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5256896A (en) * 1991-08-30 1993-10-26 International Business Machines Corporation Polysilicon-collector-on-insulator polysilicon-emitter bipolar transistor

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167346A (en) * 1980-05-27 1981-12-23 Nec Corp Manufacture of semiconductor device
JPS58166739A (en) * 1982-03-29 1983-10-01 Hitachi Ltd Semiconductor device and its manufacture
JPS59165455A (en) * 1983-03-10 1984-09-18 Toshiba Corp Semiconductor device
JPS59181636A (en) * 1983-03-31 1984-10-16 Fujitsu Ltd Semiconductor device
JPS6072242A (en) * 1983-09-28 1985-04-24 Fujitsu Ltd Manufacture of semiconductor device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8702510A1 *

Also Published As

Publication number Publication date
GB2181889A (en) 1987-04-29
WO1987002510A1 (en) 1987-04-23
GB8525848D0 (en) 1985-11-20

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