JPS5840337B2 - Manufacturing method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor integrated circuit with dielectric isolation.

In semiconductor integrated circuits, in order to electrically insulate between circuit elements, a PN junction isolation method is normally used in which the walls of the PN junction are kept in a reverse bias state. In some cases, a dielectric isolation method using an insulator such as a silicon dioxide film is used for the purpose of reducing the noise.

Conventional semiconductor integrated circuits with dielectric isolation
As shown in the figure, a plurality of single crystal semiconductor regions 1, 1' (
Also known as the island.

), but its lower side is covered with a dielectric material 2 such as silicon dioxide,
2', and has a structure supported by a polycrystalline semiconductor matrix 3.

Then, in each single crystal semiconductor region, an NPN (NPN) transistor as exemplified in FIG. 1, a resistor, a diode, and other circuit elements (not shown) are formed from the surface by techniques such as impurity diffusion or ion implantation to form a semiconductor. It is made up of an integrated circuit.

However, since this conventional semiconductor integrated circuit using dielectric insulation separation is made of a composite material of single-crystal semiconductor regions 1, 1' and polycrystalline semiconductor matrix 3, thermal history during dielectric insulation separation processing and subsequent There have been drawbacks such as wafer deformation in curvature and increase in crystal defects during heat treatment during the circuit element formation process such as diffusion treatment.

That is, in the conventional semiconductor integrated circuit shown in FIG. 1, a isolation groove is formed in a single crystal semiconductor wafer, a dielectric material such as an oxide film is formed on the surface of the wafer, and a semiconductor material (mainly silicon) is further deposited. Because it is manufactured using a method that obtains isolated single crystal semiconductor regions by polishing away most of the single crystal semiconductor wafer, the semiconductor material deposited on the dielectric material is not single crystal but polycrystalline. Differences in physical properties between single crystals and polycrystals have led to curved deformation due to thermal history, etc.

For this reason, the photoetching accuracy during integrated circuit manufacturing decreases due to the bending deformation, or special techniques are required to prevent deformation, such as adding a small amount of oxygen to the polycrystal or adding multiple insulating films to the polycrystal. However, it had the disadvantage of increasing the cost of integrated circuits.

The present invention is an improved method of manufacturing semiconductor integrated circuits using the conventional dielectric insulation separation method described above, and is an economical method that prevents wafer bending and deformation, and simplifies the polishing work in the insulation separation process. A method for manufacturing a semiconductor integrated circuit is provided.

In the present invention, after processing a separation groove in a single crystal semiconductor wafer, a dielectric region is formed inside the single crystal wafer by ion implantation, and then a single crystal semiconductor is grown, and finally the original single crystal wafer is By removing a large portion, a plurality of single crystal semiconductor base bodies supported by the single crystal semiconductor base body and insulated and separated by a dielectric material are formed.

The present invention will be explained in detail below with reference to the drawings.

FIG. 2 is a partial cross-sectional view of a semiconductor integrated circuit embodying the present invention, in which a plurality of single crystal semiconductor regions 11°11' are supported by a single crystal semiconductor matrix 13 surrounded by dielectric films 12, 12'. It is being

This single crystal semiconductor matrix 13 consists of two parts 13a and 13b divided by dotted lines in FIG. The portion 13b far from the dielectric films 12, 12' is a single crystal semiconductor grown on the surface of the portion 13a.

Then, appropriate circuit elements are formed in the single crystal regions 11 and 11', and wiring (not shown) is provided to complete an integrated circuit.

The circuit elements are insulated and separated by the dielectric films 12 and 12'.

3a to 3d represent manufacturing process diagrams for manufacturing the semiconductor integrated circuit shown in FIG. 2 according to the present invention.

First, as shown in FIG. 3a, grooves 23 and 23' are formed in a single crystal semiconductor wafer 21 using an etching mask 22 such as photoetched silicon dioxide or photoresist.

In this case, if a single crystal semiconductor with a (100) plane orientation is used for the wafer 21 and an anisotropic etching solution is used that has different etching rates depending on the direction of the crystal axis, the grooves 23, 23'
As shown in the figure, the shape can be accurate or can be a rust shape.

Next, after removing the etching mask 22, as shown in FIG. 3, ions are implanted from the bottom of the figure to form a dielectric film 24 at a certain distance from the bottom surface of the wafer 21.

In this case, the ions to be implanted are oxygen, nitrogen, carbon, etc., and the implanted region is covered with an oxide film of a semiconductor element,
A dielectric film 24 such as a nitride film or a carbide film is formed.

Here, a feature is that a thin single crystal semiconductor region 25 still remains on the lower surface of the wafer 21.

Subsequently, as shown in FIG. 3C, a semiconductor matrix 26 is deposited thickly on the lower surface of the wafer 21.

Since the semiconductor matrix 26 is deposited on the surface of the single crystal semiconductor region 25, a single crystal semiconductor growth technique called epitaxial growth technique in ordinary semiconductor technology can be used as is, and it can be deposited as a single crystal.

Therefore, the deposition thickness can be precisely controlled, and
Its volume resistivity, impurity components, etc. can be controlled, and the surface 27 after deposition is also smooth.

Finally, when the original single crystal semiconductor wafer 21 is removed little by little from the upper surface by polishing or etching to expose the dielectric film 24 on the surface, the dielectric film 24 is insulated and isolated as shown in FIG. Multiple single crystal semiconductor regions 2
A dielectric insulation separated wafer in which 8 is supported by the single crystal semiconductor base body 26 is completed.

Circuit elements are then formed using conventional techniques.

In the above steps, if a step is created in advance in the impurity concentration on the wafer 21, the polishing work in the steps from C to d in FIG. It is possible to leave it.

Further, if necessary, the lower surface of the single crystal semiconductor base body 26 may be polished and etched to make it smoother.

If the single crystal semiconductor base body 26 is formed by adding a small amount of a specific impurity so that it has the opposite conductivity type to the single crystal semiconductor region 28, the region 25 also becomes the same conductivity type as the base body 26 during crystal deposition or circuit element formation. The impurity diffuses and temporarily forms the dielectric film 24.
Even if there is a partial defect such as a pinhole in the single crystal semiconductor region 28, a rectifying junction can be formed between the single crystal semiconductor region 28 and the single crystal semiconductor matrix 26, so there is no possibility of poor insulation between the plurality of single crystal semiconductor regions. It can be prevented.

These are one of the specific application examples of the configuration of the present invention.

As explained above, by implementing the present invention, a plurality of single crystal semiconductor regions separated by dielectric insulation are supported by a single crystal semiconductor matrix, unlike conventional systems supported by a polycrystalline semiconductor matrix. The deformation of the wafer, which is caused by the difference in the growth rate of the oxide film between the single crystal and the polycrystal, or the shrinkage of the polycrystal due to recrystallization due to heat, which occurs in the prior art, does not occur at all.

In addition, polycrystalline semiconductors are fragile in terms of strength, but by creating a single crystal matrix, the strength is improved, and the thickness of the matrix can be made thinner than when using a conventional polycrystalline matrix, allowing crystal growth. It can also save time.

Furthermore, the surface of the polycrystalline matrix has many irregular irregularities, and it was necessary to polish the surface of the polycrystalline matrix smooth before polishing the single crystal Ueno side. However, by implementing the present invention, Since the base material is a single crystal, its deposition surface is smooth, and the polishing process can be eliminated or reduced.

As a result, according to the technique of the present invention, it is possible to manufacture semiconductor integrated circuits with high precision and economically.

[Brief explanation of drawings]

FIG. 1 is a partial cross-sectional view of a semiconductor integrated circuit using the conventional dielectric isolation method, FIG. 2 is a partial cross-sectional view of a semiconductor integrated circuit according to the present invention, and FIG. 3 a and d are the circuits in FIG. 1 is a process diagram for manufacturing a semiconductor integrated circuit according to the method of manufacturing a semiconductor integrated circuit according to the present invention. 11.11.11', 2B... Single crystal semiconductor region, 12, 12', 24... Dielectric film, 13° 26... Single crystal semiconductor matrix, 21・・・・・・
Single crystal semiconductor wafer 22...Mask, 23.
·····groove.

Claims (1)

[Claims] 1. Forming a groove on the surface of a single crystal semiconductor wafer, forming a dielectric film inside the wafer by implanting ions from the surface side, and then growing a single crystal semiconductor on the surface, Thereafter, a portion of the back side of the wafer is removed until a portion of the dielectric film is exposed, forming a plurality of single crystal semiconductor regions insulated and separated by the dielectric film and supported by a single crystal semiconductor matrix. A method for manufacturing a semiconductor integrated circuit, comprising forming circuit elements in a single crystal semiconductor region. 2. The method of manufacturing a semiconductor integrated circuit according to claim 1, wherein the single crystal semiconductor base body is formed to have a conductivity type opposite to that of the single crystal semiconductor region separated by a dielectric film.