JPH1126835A - Semiconductor hall element and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the detecting sensitivity of an active area formed in the surface layer area of a semiconductor substrate for a magnetic flux which is impressed upon the semiconductor substrate obliquely to or in parallel with the surface of the substrate by forming the active area so that the bottom of the area may be inclined continuously against the surface of the substrate from one end to the other end. SOLUTION: A galvanomagnetic section, namely, an active area 14 and an electrode 16 for inputting current or outputting voltage are formed in the surface layer section of a semi-insulating gallium arsenide substrate 12 split in a square shape. The active area 14 has an n-type conductivity and an n<+> -area having a high carrier concentration (10<18> cm<-3> ) is formed below the electrode 16. In addition, the surface of the substrate 12 is coated with a protective film 20. The depth of the active area 14 from the surface of the substrate 12 is not uniform, but is continuously changed in an oblique depth distribution. Therefore, the active area 14 can detect a magnetic flux with high sensitivity even when the magnetic flux is impressed upon the substrate in parallel with the surface of the substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor Hall element and a method of manufacturing the same, and more particularly, to a semiconductor Hall element capable of detecting a magnetic field oblique to a substrate of the element with high sensitivity and a method of manufacturing the same.

[0002]

2. Description of the Related Art A semiconductor Hall element is an element for detecting the intensity of a magnetic field as a voltage signal by utilizing the Hall effect of a semiconductor. For example, in a device such as a video cassette recorder or a floppy disk drive. Widely used to control the operation of motors.

FIG. 8 is a schematic configuration diagram showing a conventional semiconductor Hall element. That is, FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along line AA ′.

[0004] A semiconductor Hall element is generally a III-V
It is formed on a group III compound semiconductor substrate. In the example shown in FIG. 8, on the surface layer portion of a semi-insulating gallium arsenide substrate 110 divided into squares each having a side of 200 to 300 microns, a magnetoelectric converter 120 and electrodes for current input or voltage output are provided. 130 are formed. Magnetoelectric converter 1
Reference numeral 20 denotes an n-type region formed at a uniform depth from the surface of the substrate 110, and may be referred to as an “active region”.
Further, an n ⁺ -type region having a high carrier concentration is formed below the electrode 130. Further, the surface of the substrate 110 is covered with a protective film 140.

A conventional Hall element as shown in FIG.
It has sufficient sensitivity to magnetic flux in a direction perpendicular to the surface of the substrate 110, but has little sensitivity to magnetic flux in a direction parallel to the surface.

Here, the sensitivity characteristics of the Hall element will be described with reference to FIG.

FIG. 9 is a schematic explanatory view showing a state in which a magnetic flux B is applied to the semiconductor substrate 200. Here, the width of the semiconductor substrate 200 is w, the length is 1, the thickness is d,
Assuming that the angle between the surface of the substrate 200 and the magnetic flux B is θ,
The Hall output voltage Vh due to the Hall effect is represented by the following equation.

Vh = Kh · Ic · B · sin θ (1) where Kh = Rh · fh (θ / w) / d In the above equation, Rh is an amount called “Hall coefficient”. Fh is a function of (θ / w) and is called a “form factor”. In equation (1), assuming that the magnetic flux B is constant, the Hall voltage Vh becomes maximum when θ = 90 °, that is, when the magnetic flux B is perpendicular to the substrate surface, and θ =
When the magnetic flux B is 0 °, that is, when the magnetic flux B is parallel to the substrate surface, the Hall voltage Vh becomes minimum. That is, if the Hall element is arranged in a direction parallel to the magnetic flux, the detection sensitivity decreases.

For this reason, when the conventional Hall element as shown in FIG. 8 is used, a device for mounting is devised so that the substrate surface is as vertical as possible to the magnetic flux to be detected. Was.

[0010]

However, in recent years, there has been a demand for further miniaturization and thinning of various electronic devices equipped with a brushless motor using a Hall element. In order to meet this requirement, it often occurs that it is difficult to mount the Hall element perpendicular to the direction of the magnetic flux to be detected. As described above, when the Hall element is mounted obliquely with respect to the magnetic flux due to the dimensional restriction, the detection sensitivity is reduced and the reliability of the electronic device is reduced. Further, in an extreme case, the magnetic flux cannot be detected substantially, and it may be impossible to use the Hall element.

FIG. 10 is a schematic configuration diagram showing a main part of a thin brushless motor used in a video tape recorder or a floppy disk drive. That is, in the brushless motor, the electromagnet 150 and the magnet 180 face each other. The magnet 180 is fixed to the rotor 160, rotates around a shaft 182, and is supported by a bearing 182. In order to detect the magnetic flux from the electromagnet 150, the Hall element 17 is used.
0 is used. Here, in order to reduce the thickness of the motor, the Hall element 170 is desirably mounted in a direction parallel to the electromagnet 150 as shown in FIG. As a result, as shown in FIG.
Is incident on the Hall element 170 from an oblique direction.

However, as described above with reference to FIG. 9, the conventional Hall element has a problem that the detection sensitivity decreases as the direction of the magnetic flux incident on the element substrate approaches parallel. Therefore, it has been difficult to simultaneously satisfy the two requirements of maintaining the detection sensitivity of the Hall element and miniaturizing the mounted device.

The present invention has been made in view of such a problem. That is, the present invention has sufficient sensitivity not only to the magnetic flux in the direction perpendicular to the substrate of the Hall element but also to the magnetic flux in the direction parallel thereto, and eliminates the need for elaborate mounting when using the same. It is another object of the present invention to provide a semiconductor Hall element which has high reliability and can be used in a wide range of applications, and a method for manufacturing the same.

[0014]

That is, a semiconductor Hall element of the present invention is configured as having an active region having a bottom surface inclined with respect to the surface of a semiconductor substrate. By forming the active region in this manner, the sensitivity to magnetic flux applied obliquely or parallel to the substrate can be improved.

The semiconductor substrate is a semi-insulating gallium arsenide substrate, and the active region is preferably an n-type region.

Further, it is desirable to use silicon as a dopant for the n-type region.

Further, the method of manufacturing a semiconductor Hall element according to the present invention is configured to include a step of forming a concave portion having an inclined surface on a surface of a semiconductor substrate and embedding a semiconductor crystal in the concave portion to form an active region. .

It is desirable that such a concave portion is formed by mesa etching.

A second method of manufacturing a semiconductor Hall element according to the present invention comprises forming a mask having a wedge-shaped cross section on the surface of a semiconductor substrate and transmitting a dopant through the mask to introduce a dopant. You.

The mask having such a wedge-shaped cross-sectional shape can be formed by utilizing side etching, or by depositing a thin film into a step shape and, if necessary, softening by heating. Can be formed.

[0021]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a schematic structural view showing a semiconductor Hall element according to the present invention. That is, FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along line AA ′.

The semiconductor Hall element 10 according to the present invention can be formed, for example, on a group III-V compound semiconductor substrate. In the example shown in FIG. 1, the surface layer portion of the semi-insulating gallium arsenide substrate 12 divided into a square shape is
A magnetoelectric converter or active region 14 and electrodes 16 for current input or voltage output are formed. The conductivity type of the active region 14 is n-type, and the carrier concentration thereof can be, for example, 10 ¹⁷ cm ⁻³ . The electrode 16
Is formed under the n + -type region 18 having a high carrier concentration.
Are formed. The carrier concentration is, for example, 10 ¹⁸
cm ⁻³ . Further, the surface of the substrate 12 is covered with a protective film 20.

Here, according to the present invention, the depth of the active region 14 is not uniform from the surface of the substrate 12 and is formed so as to change continuously. Thus, the active region 14
Is formed so as to have an oblique depth distribution with respect to the surface of the substrate 12, so that a sufficient detection sensitivity can be obtained even for a magnetic flux parallel to the substrate.

Regarding the detection sensitivity of the Hall element of the present invention,
This will be described below with reference to FIG.

FIG. 2A is a schematic perspective view of the active region 14 of the Hall element according to the present invention, and FIG. 2B shows a state where a magnetic flux _B0 is applied to the active region 14. It is a schematic side view showing. Here, the width of the active region 14 is w, the length is 1, the shallowest depth from the substrate surface is a, the deepest depth from the substrate surface is (a + b), and the bottom surface of the active region is the substrate surface. And the angle formed by と. Also, θ, δ, and h are defined as shown in FIG. Then, the voltage due to the Hall effect: Ey = Rh · j · B Hall coefficient: Rh = 1 / (n · c · q) Current density: j = I · cos θ / (w · h) Magnetic flux density: B = B ₀ · cos (δ−θ). Therefore, the Hall voltage Vh can be expressed by the following equation.

[0027]

(Equation 1) That is, it can be seen that the center value of the Hall voltage distribution is shifted by (ψ / 2), and the magnitude is cos (ψ / 2) times.

FIG. 3 is a graph showing the output voltage characteristics of the Hall element represented by the equation (2) in comparison with the characteristics of the conventional Hall element. That is, the vertical axis in the figure represents the output voltage of the Hall element. The horizontal axis represents the angle of incidence of the magnetic flux on the substrate surface, and the angle when the magnetic flux is perpendicularly incident on the substrate surface is represented as zero.

As is apparent from FIG. 2, in the conventional Hall element, the detection sensitivity of the Hall element peaks when the magnetic flux is perpendicularly incident on the substrate surface.
According to the present invention, the peak of the detection sensitivity of the Hall element is obtained when the incident angle of the magnetic flux is (ψ / 2). Further, it can be seen that the Hall element according to the present invention exhibits broader sensitivity characteristics than the conventional one, and the range of sensitivity to the incident magnetic flux is wider than the conventional one.

In FIG. 3, at an angle α represented on the horizontal axis,
The Hall voltages of the conventional Hall element and the Hall element according to the present invention match. That is, according to the present invention, when the angle of incidence of the magnetic flux is larger than α, higher sensitivity than before can be obtained. According to the experiment of the inventor, a plurality of Hall elements in which the bottom surface of the active region 14 has various angles with respect to the substrate surface are prototyped, and the Hall voltage Vh is measured for each of the Hall elements while changing the incident direction of magnetic flux. As a result, it was confirmed that the sensitivity characteristics as shown in FIG. 3 were obtained.

As is clear from the above description, according to the present invention, a higher detection sensitivity is provided for the magnetic flux obliquely incident on the substrate surface of the element than in the prior art. Further, the magnetic flux in the direction parallel to the substrate surface can be detected. As a result, the Hall element can be mounted in the direction parallel to the magnetic flux, and various devices such as a brushless motor can be easily reduced in size and thickness. Further, the mounting process is facilitated, the manufacturing cost is reduced, and the reliability of various devices equipped with the Hall element can be improved.

Next, a method of manufacturing a Hall element according to the present invention will be described.

FIG. 4 is a schematic process sectional view showing a process of manufacturing a Hall element according to the present invention. First, as shown in FIG. 4A, a photoresist mask 30 having an opening 32 is formed on the surface of a semi-insulating gallium arsenide substrate 12 having a plane orientation (100) by a photolithography method. Next, through the opening 32, the surface of the substrate 12 is
Etch anisotropically down to about a micron. The etching method at this time is preferably so-called mesa etching, for example, methyl bromide (Br ₂ —CH ₃
OH) can be used. This mesa etching makes an angle of 54 ゜ 44 ′ with respect to the surface of the substrate 12 (111), (1).
The inclined surface portion 34 composed of the normal mesa surface of -1-1) is formed.

Next, as shown in FIG. 4B, the photoresist mask 30 is removed, an n-type gallium arsenide layer is epitaxially grown, and the surface is flattened by lapping. To form The carrier concentration of the active region 14 is, for example, 10 ¹⁷
cm ⁻³ . The epitaxial growth method may be any method as long as the method allows buried growth on an inclined surface, and for example, a liquid phase growth method (liquid phase growth method).
epitaxy: LPE). In addition, metal-organic vapor phase epitaxy (metal-organic)
vaporphase epitaxy: MOVP
E) and molecular beam epitaxy (molecular)
vapor phase epitaxy: VP such as beam epitaxy: MBE
E) may also be used.

Next, as shown in FIG. 4C, a photoresist mask 36 is formed, and an n-type dopant is selectively introduced to form an n ⁺ region 18. Here, the n ⁺ region 18 is formed so as to leave only one of two opposing inclined surfaces 34 of the n-type region. By forming in this manner, the active region 14 having a bottom surface inclined with respect to the substrate surface can be formed.

As the method of introducing the n-type dopant when forming the n ⁺ region 18, for example, an ion implantation method or a thermal diffusion method can be used. As the n-type dopant, for example, silicon can be used. In the case of employing the ion implantation method, for example, silicon having an atomic weight of 29 is implanted at an acceleration voltage of 360 kV and a dose of 4 × 10 ¹³ cm ⁻² , followed by annealing to form the n ⁺ region 18. be able to.

Next, as shown in FIG. 4D, by removing the photoresist mask 36 and forming the protective film 20 and the electrode 16, the Hall element 10 is completed. As a material of the protective film 20, for example, polysilicate glass (PSG), silicon oxide, silicon nitride, aluminum oxide, or the like can be used. The electrode 16 only needs to be capable of forming a good contact with the n ⁺ region 18. For example, the electrode 16 has a structure in which a gold-germanium alloy layer, a nickel layer, and a gold layer are stacked in this order. Can be.

Next, a second method for manufacturing a Hall element according to the present invention will be described with reference to FIG.

FIG. 5 is a schematic process sectional view showing a second method of manufacturing a Hall element according to the present invention. In this method, first, as shown in FIG. 3A, a mask 40 having a wedge-shaped cross-sectional shape and a mask 42 having a constant thickness are formed on the surface of a semi-insulating gallium arsenide substrate 12. Form each. The mask 40 is formed so as to be transparent to a dopant introduced in a later step. The mask 42 is formed so as to shield the dopant. As a material for these masks, for example, silicon oxide, silicon nitride, resist, polyimide, or the like can be used.

A mask 40 having a wedge-shaped cross section
Can be formed using, for example, side etching.

FIG. 6 shows a mask 4 formed by side etching.
FIG. 9 is a schematic explanatory diagram in the case of forming 0. First, as shown in FIG. 1A, a film 40a such as a silicon oxide film is formed on a substrate 12, and a resist mask 60 having a predetermined opening pattern is formed thereon.

Next, the silicon oxide film 40a is etched through the opening of the resist mask 60. Then, around the opening, the silicon oxide 40a below the resist mask 60 is eroded by side etching. In order to cause such side etching remarkably, it is desirable to use a wet etching method as an etching method. In the portion where the side etching occurs, the thickness of the silicon oxide 40a gradually changes, and a wedge-shaped cross-sectional shape as shown in FIG. 6B can be obtained.

Next, as shown in FIG. 6C, by removing the unnecessary portions of the resist mask 60 and the silicon oxide film 40a, the mask 40 having a wedge-shaped cross-sectional shape is obtained.

Next, another method for forming the mask 40 having such a wedge-shaped cross section will be described with reference to FIG.

FIG. 7 is a process sectional view for forming a mask 40 having a wedge-shaped sectional shape. First, FIG.
As shown in (a) to (c), a predetermined mask material 40
, 40c, 40d,... are laminated stepwise. For example, by repeating a process of depositing a resist in a thin film shape and exposing and patterning using a photomask having a smaller pattern in order, a stepwise lamination can be achieved.

Next, when the surface of the resist is softened by heat treatment or the like to flatten the surface, as shown in FIG. 7D, a continuous slope is formed and has a wedge-shaped cross-sectional shape. A mask 40 is obtained. Here, it is desirable to use a resist or another organic material in order to soften by heat treatment to cause flattening.

Further, when forming a step-like laminated structure as shown in FIGS. 7A to 7C, if the number of layers is increased to form a fine step-like structure, the resulting mask is Even if the surface is not flattened, it can be used substantially as a mask having a wedge-shaped cross-sectional shape in the present invention. Therefore, even when a material such as silicon oxide or silicon nitride is used, if a step-like laminated structure including a large number of layers is used, a surface flattening step as shown in FIG. It can be used as the wedge mask 40 of the present invention.

Referring back to FIG. 5, after forming predetermined masks 40 and 42, a dopant is introduced through the mask 40 as shown in FIG.
An active region 14 is formed. At this time, the mask 42 shields the dopant. As a method for introducing the dopant, for example, an ion implantation method, a thermal diffusion method, or the like can be used.

Since the mask 40 has a wedge-shaped cross-sectional shape, the amount of dopant introduced through the mask 40 varies from place to place, reflecting the thickness of the mask 40. As a result, the bottom surface of the formed active region 14 is inclined with respect to the substrate surface.

Here, conditions for the ion implantation method include, for example, implantation of silicon having an atomic weight of 29 at an acceleration voltage of 360 kV and a dose of 3 to 4 × 10 ¹² cm ⁻² , followed by annealing. The active region 14
Can be formed.

Next, as shown in FIG.
By removing 0 and 42 to form a new mask 44 and introducing a dopant through the opening, n ⁺
A region 18 is formed.

In this case, the method of introducing the dopant is as follows.
For example, a method such as an ion implantation method or a thermal diffusion method can be used. Conditions for ion implantation are as follows:
For example, an acceleration voltage of 360 kV and a dose of 4 × 10
By implanting silicon having an atomic weight of 29 at ¹³ cm ^-2 and thereafter performing annealing, the n ⁺ region 18 can be formed.

Next, as shown in FIG. 5D, by removing the mask 44 and forming the protective film 20 and the electrode 16, the Hall element 10 is completed. The materials of the protective film 20 and the electrode 16 can be the same as those described above.

[0054]

The present invention is embodied in the form described above and has the following effects.

First, according to the present invention, the detection sensitivity to magnetic flux obliquely incident on the substrate surface of the element is higher than that of the related art. Further, the magnetic flux in the direction parallel to the substrate surface can be detected. As a result, the Hall element can be mounted in the direction parallel to the magnetic flux, and various devices such as a brushless motor can be easily reduced in size and thickness.

Further, according to the present invention, it is not necessary to take special measures when mounting the Hall element. Therefore, the mounting process is facilitated, the manufacturing cost is reduced, and the reliability of various devices equipped with the Hall element can be improved.

As described above, according to the present invention, it is possible to easily obtain a high-performance Hall element, and industrial advantages are great.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a semiconductor Hall element according to the present invention. That is, FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along line AA ′.

FIG. 2 (a) is a schematic perspective view of an active region 14 of a Hall element according to the present invention, and FIG. 2 (b) shows a state where a magnetic flux _B0 is applied to the active region 14. It is a schematic side view showing.

FIG. 3 is a graph showing the output voltage characteristics of the Hall element represented by the equation (2) in comparison with the characteristics of a conventional Hall element.

FIG. 4 is a schematic process sectional view illustrating a process of manufacturing a Hall element according to the present invention.

FIG. 5 is a schematic process sectional view illustrating a second method of manufacturing a Hall element according to the present invention.

FIG. 6 is a schematic explanatory view in the case of forming a mask 40 by side etching.

FIG. 7 is a process cross-sectional view in forming a mask 40 having a wedge-shaped cross-sectional shape.

FIG. 8 is a schematic configuration diagram showing a conventional semiconductor Hall element. That is, FIG. 3A is a plan view thereof, and FIG. 3B is a sectional view taken along line AA ′.

FIG. 9 is a schematic explanatory diagram illustrating a state where a magnetic flux B is applied to a semiconductor substrate 200.

FIG. 10 is a schematic configuration diagram illustrating a main part of a thin brushless motor.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor Hall element 12 Semiconductor substrate 14 Active region 16 Electrode 18 Contact region 20 Protective film 30 Mask 32 Opening 34 Inclined surface 36 Mask 40 Mask 42 Mask 44 Mask 100 Semiconductor Hall element 110 Semiconductor substrate 120 Active area 130 Electrode 140 Protective film

Claims (15)

[Claims] 1. A Hall element comprising: a semiconductor substrate; and an active region formed in a surface layer region of the semiconductor substrate, wherein the active region has a depth from one end to the other end. A semiconductor Hall element formed so as to be continuously deeper. 2. A Hall element having a semiconductor substrate and an active region formed in a surface layer region of the semiconductor substrate, wherein the Hall element converts an applied magnetic flux into a voltage signal and outputs the voltage signal. A semiconductor Hall element wherein the depth of the active region from the surface of the semiconductor substrate is not constant so that sensitivity to the magnetic flux parallel to the substrate surface is increased. 3. A semiconductor substrate and an active region formed in a surface layer region of the semiconductor substrate, wherein two stripes have a surface pattern of a shape substantially orthogonal to each other. An active region formed so that the depth of the active region from the surface of the semiconductor substrate in at least one of the stripe portions is continuously increased from one end of the stripe toward the other end; A semiconductor Hall element, comprising: a contact region formed adjacent to both ends of each of the stripes in a region; and an electrode formed in contact with the contact region. 4. A semiconductor substrate made of semi-insulating gallium arsenide, and an n-type region selectively formed in a surface layer region of the semiconductor substrate, wherein two stripes are substantially orthogonal to each other. A surface pattern, wherein a depth from a surface of the semiconductor substrate in a portion of at least one of the two stripes is continuously increased from one end to the other end of the stripe; An active region comprising a formed region; and an n-type region formed adjacent to both ends of each of the stripes of the active region, the contact region having a higher carrier concentration than the active region. And an electrode formed in contact with the contact region. 5. The semiconductor Hall device according to claim 4, wherein the n-type impurity contained in said active region is silicon. 6. An etching step of selectively etching a surface of a semiconductor substrate to form a recess having a surface inclined with respect to the surface of the substrate, and growing a semiconductor crystal in the recess of the semiconductor substrate. A crystal growth step of filling the recess, a contact area forming step of forming a contact area adjacent to both ends of one of the inclined surfaces of the recess, and a metal contacting the contact area. An electrode forming step of depositing: a method of manufacturing a semiconductor Hall element. 7. An etching step of selectively etching the surface of a semi-insulating gallium arsenide substrate to form a recess having a surface inclined with respect to the surface of the substrate, and forming a recess in the recess of the semiconductor substrate. a crystal growth step of growing n-type gallium arsenide and filling the recess with the n-type gallium arsenide; and forming an n-type gallium arsenide in a region adjacent to both ends of one of the inclined surfaces of the recess. A contact region forming step of selectively introducing impurities to form a contact region having a carrier concentration higher than that of the n-type gallium arsenide; and an electrode forming step of depositing a metal in contact with the contact region. A method for manufacturing a semiconductor Hall element, comprising: 8. The semi-insulating gallium arsenide substrate comprises (10
0), and the etching in the etching step is a mesa
Etching, and the inclined surface is the (100)
8. The method of claim 7, wherein any of the substrates is a regular mesa surface. 9. A mask forming step of forming, on a surface of a semiconductor substrate, a first mask having a wedge-shaped cross-sectional shape and a second mask surrounding the first mask, and transmitting the first mask through the first mask. By selectively introducing impurities into the surface layer region of the substrate, an active region whose depth from the surface of the substrate continuously changes corresponding to the wedge-shaped cross-sectional shape of the first mask is formed. Forming an active region, forming a contact region having a carrier concentration higher than the active region adjacent to an end of the active region, and depositing a metal in contact with the contact region. A method of manufacturing a semiconductor Hall element, comprising: 10. A semi-insulating gallium arsenide substrate, comprising:
A mask forming step of forming a first mask having a wedge-shaped cross-sectional shape and a second mask surrounding the first mask; and transmitting the first mask to selectively remove n-type impurities from the substrate. By introducing into the surface layer region, the first
Forming an active region in which the depth from the surface of the substrate continuously changes in accordance with the wedge-shaped cross-sectional shape of the mask; and n in the region adjacent to the end of the active region. A contact region forming a contact region having a higher carrier concentration than the active region by selectively introducing a type impurity, and an electrode forming step of depositing a metal in contact with the contact region. A method for manufacturing a semiconductor Hall element, comprising: 11. The mask forming step comprises: depositing a mask material on the substrate, forming a third mask having a predetermined opening on the mask material, and forming a third mask through the opening of the third mask. Etching the mask material so as to cause side etching of the mask material under the third mask around the opening, so that the mask material has the wedge-shaped cross-sectional shape.
The method according to claim 9, further comprising the step of: 12. The mask forming step comprises forming a resist mask having a step-like cross-sectional shape by sequentially depositing a plurality of resist layers having different pattern dimensions, and softening the resist by heating the resist mask. 11. The method according to claim 9, further comprising the step of forming the first mask having a wedge-shaped cross section.
The method described in. 13. A step of forming a first mask having a stepped cross-sectional shape by sequentially depositing a plurality of mask layers having different pattern dimensions on a surface of a semiconductor substrate, and a second mask surrounding the periphery thereof. Forming a mask including a step of forming a mask, and selectively introducing impurities into the surface layer region of the substrate by transmitting the first mask to the surface layer region of the semiconductor substrate. An active region forming step of forming an active region so that the depth of the region containing the impurity is continuously increased toward the other end, and adjacent to each end of the active region, A contact region forming step of forming a contact region having a high carrier concentration; and an electrode forming step of depositing a metal in contact with the contact region. Manufacturing method of body Hall element. 14. A semi-insulating gallium arsenide substrate, comprising:
A mask forming step including a step of forming a first mask having a stepped cross-sectional shape by sequentially depositing a plurality of mask layers having different pattern dimensions, and a step of forming a second mask surrounding the periphery thereof By selectively introducing an n-type impurity into the surface layer region of the substrate by transmitting the first mask to the surface layer region of the semiconductor substrate from one end to the other end of the surface of the substrate. Forming an active region in which the depth from the active region is continuously increased by selectively introducing an n-type impurity into a region adjacent to each end of the active region. A contact region forming a contact region having a higher carrier concentration, and an electrode forming step of depositing a metal in contact with the contact region. Of manufacturing a semiconductor Hall element. 15. The method according to claim 13, wherein said mask layer in said mask forming step is made of any material selected from the group consisting of silicon oxide, silicon nitride, and resist. The described method.