JPH06163556A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH06163556A
JPH06163556A JP31702292A JP31702292A JPH06163556A JP H06163556 A JPH06163556 A JP H06163556A JP 31702292 A JP31702292 A JP 31702292A JP 31702292 A JP31702292 A JP 31702292A JP H06163556 A JPH06163556 A JP H06163556A
Authority
JP
Japan
Prior art keywords
semiconductor device
type
epitaxial layer
effect
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31702292A
Other languages
Japanese (ja)
Inventor
Masahiro Toeda
雅寛 戸枝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP31702292A priority Critical patent/JPH06163556A/en
Publication of JPH06163556A publication Critical patent/JPH06163556A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide a semiconductor device having an epitaxial layer on a semiconductor substrate in which gettering effect and latch-up free effect can be achieved. CONSTITUTION:A P<+>-type impurity layer 2 is formed at the border of a lightly doped P-type silicon substrate 1 and a P-type epitaxial layer 3. Consequently, latch-up free effect and gettering effect are achieved and since a lightly doped P-type silicon substrate is employed, outward diffusion of impurities from the rear surface can be restrained completely. The semiconductor device thus fabricated can withstand wet etching process and high temperature long time diffusion process.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体装置に関し、特に
エピタキシャル層を有する半導体装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having an epitaxial layer.

【0002】[0002]

【従来の技術】ゲッタリング効果とラッチアップフリー
効果とを得るために従来の半導体装置では、半導体基板
中の不純物濃度を高くしている。以下図2を用いて説明
する。
2. Description of the Related Art In order to obtain a gettering effect and a latch-up free effect, a conventional semiconductor device has a high impurity concentration in a semiconductor substrate. This will be described below with reference to FIG.

【0003】例えば、高濃度のボロンを不純物とするシ
リコン単結晶から成るP+ 型シリコン基板1Aの表面上
に、ボロンを不純物とするP型エピタキシャル層3を形
成する。この構造におけるP+ 型シリコン基板1Aの濃
度は、8.0×1018個/cm3 程度に製造し、そし
て、P型エピタキシャル層3の濃度は、7×1014個/
cm3 程度である。以上の様な構造におけるP+ 型シリ
コン基板1Aにより高性能なゲッタリング効果そして、
ラッチアップフリー効果が期待できる。
For example, a P type epitaxial layer 3 having boron as an impurity is formed on the surface of a P + type silicon substrate 1A made of a silicon single crystal having a high concentration of boron as an impurity. The P + type silicon substrate 1A in this structure is manufactured to have a concentration of about 8.0 × 10 18 pieces / cm 3 , and the P type epitaxial layer 3 has a concentration of 7 × 10 14 pieces / cm 3.
It is about cm 3 . High-performance gettering effect by the P + type silicon substrate 1A having the above structure
Latch-up free effect can be expected.

【0004】しかし、1018個/cm3 程度の高濃度の
ボロンを不純物とするP+ 型シリコン基板では、その裏
面から不純物の外方拡散が発生するため、その裏面に、
例えばLPCVD成長による酸化シリコン膜4を500
nm程度の厚さに形成している。この酸化シリコン膜4
によってボロンの外方拡散を抑える事は初期的には可能
であるが、本拡散工程において、ウェットエッチングに
よる裏面酸化膜の薄膜化や、高温長時間の熱履歴を使用
しなければならない拡散工程においては、基板裏面から
のボロンの外方拡散を防ぐ事は難かしい。
However, the P + -type silicon substrate to a high concentration of boron of about 10 18 / cm 3 and an impurity, since the outward diffusion of impurities generated from the back surface, the back surface thereof,
For example, the silicon oxide film 4 formed by LPCVD is grown to 500
It is formed to a thickness of about nm. This silicon oxide film 4
Although it is initially possible to suppress the out-diffusion of boron by this method, in this diffusion process, in the diffusion process that requires thinning of the backside oxide film by wet etching and the use of heat history at high temperature for a long time. , It is difficult to prevent outward diffusion of boron from the back surface of the substrate.

【0005】[0005]

【発明が解決しようとする課題】上述したように従来の
半導体基板では、ゲッタリング効果そしてラッチアップ
フリー効果を得るために、高濃度のボロン(1018個/
cm3 オーダ)を不純物とするP+ 型シリコン基板を使
用している。このため、その裏面にボロンの外方拡散防
止用の酸化シリコン膜などを形成しているがこの酸化シ
リコン膜が、半導体素子形成工程のウェットエッチング
や高温長時間の熱履歴に耐えられなくなり、ボロンの外
方拡散を抑えることができなくなる。このため、ゲッタ
リング効果及びラッチアップフリー効果が製造工程の途
中で減少し、半導体装置の特性及び歩留りが低下すると
いう問題があった。
As described above, in the conventional semiconductor substrate, in order to obtain the gettering effect and the latch-up free effect, high concentration boron (10 18 /
A P + type silicon substrate having an impurity of the order of cm 3 ) is used. For this reason, a silicon oxide film for preventing the outward diffusion of boron is formed on its back surface, but this silicon oxide film cannot withstand the wet etching in the semiconductor element forming process and the thermal history of high temperature for a long time. It becomes impossible to suppress the outward diffusion of. Therefore, there is a problem that the gettering effect and the latch-up free effect are reduced during the manufacturing process, and the characteristics and yield of the semiconductor device are reduced.

【0006】[0006]

【課題を解決するための手段】本発明の半導体装置は、
半導体基板上にエピタキシャル層を有する半導体装置に
おいて、前記エピタキシャル層と前記半導体基板との境
界部にそのエピタキシャル層と半導体基板よりも不純物
濃度の高い層を設けたものである。
The semiconductor device of the present invention comprises:
In a semiconductor device having an epitaxial layer on a semiconductor substrate, a layer having a higher impurity concentration than the epitaxial layer and the semiconductor substrate is provided at a boundary portion between the epitaxial layer and the semiconductor substrate.

【0007】[0007]

【実施例】次に本発明について図面を参照して説明す
る。
The present invention will be described below with reference to the drawings.

【0008】図1は本発明の一実施例の断面図である。FIG. 1 is a sectional view of an embodiment of the present invention.

【0009】ボロンを不純物とするシリコ単結晶、例え
ばその濃度を1.0×1012個/cm3 程度の低濃度の
P型シリコン基板1の表面に、やはりボロンを8.0×
1018個/cm3 程度含み、深さ5μm程度のP+ 型不
純物層2を形成する。このP+ 型不純物層2は、シリコ
ンのエピタキシャル成長、又はガス拡散によって形成す
ることができる。続いて、このP+ 型不純物層2の表面
に、ボロンを不純物とし、濃度が7×1014個/cm3
程度のP型エピタキシャル層3を形成する。
A silicon single crystal containing boron as an impurity, for example, 8.0 × boron is also formed on the surface of a P-type silicon substrate 1 having a low concentration of about 1.0 × 10 12 pieces / cm 3.
A P + -type impurity layer 2 containing about 10 18 / cm 3 and having a depth of about 5 μm is formed. The P + -type impurity layer 2 can be formed by epitaxial growth of silicon or gas diffusion. Then, on the surface of the P + -type impurity layer 2, boron is used as an impurity and the concentration is 7 × 10 14 pieces / cm 3
A P-type epitaxial layer 3 having a certain degree is formed.

【0010】この様に形成された本実施例によれば、P
+ 型不純物層3によって、ゲッタリング効果及びラッチ
アップフリー効果が得られる。更にP型シリコン基板1
中のボロンは低濃度であることから、その裏面からのボ
ロンの外方拡散は抑制される。また、従来必要であった
シリコン基板裏面への酸化シリコン膜の形成が不要にな
る。
According to this embodiment thus formed, P
The gettering effect and the latch-up free effect are obtained by the + type impurity layer 3. Furthermore, P-type silicon substrate 1
Since boron in the inside has a low concentration, outward diffusion of boron from its back surface is suppressed. Further, it is not necessary to form a silicon oxide film on the back surface of the silicon substrate, which has been conventionally required.

【0011】尚、上記実施例においてはP型不純物を用
いた場合について説明したが、N型不純物の場合であっ
ても同様の効果を得ることができる。
In the above embodiment, the case of using the P-type impurity has been described, but the same effect can be obtained even in the case of the N-type impurity.

【0012】[0012]

【発明の効果】以上説明した様に本発明は、半導体基板
上にエピタキシャル層を有する半導体装置において、そ
の半導体基板とエピタキシャル層との境界領域に高濃度
不純物層を形成したので、ゲッタリング効果及びラッチ
アップフリー効果を製造工程の後半にまで維持できる。
また、半導体基板中の不純物を低濃度にすることが可能
となり、その裏面からの不純物、例えばボロンなどの外
方拡散を完全に抑える事ができる。
As described above, according to the present invention, in the semiconductor device having the epitaxial layer on the semiconductor substrate, the high-concentration impurity layer is formed in the boundary region between the semiconductor substrate and the epitaxial layer. The latch-up free effect can be maintained even in the latter half of the manufacturing process.
Further, it becomes possible to reduce the concentration of impurities in the semiconductor substrate, and it is possible to completely suppress the outward diffusion of impurities such as boron from the back surface thereof.

【0013】このため、従来使用していた高濃度不純物
基板に必要であった裏面への酸化シリコン膜を使用しな
くても、高温長時間の素子形成拡散工程に流すことが可
能となり、外方拡散による半導体基板への影響を最小限
に抑える事ができるため、半導体装置の信頼性及び歩留
りを向上させることができる。
For this reason, it is possible to carry out a high temperature and long time element formation diffusion process without using a silicon oxide film on the back surface, which is required for a high concentration impurity substrate which has been used conventionally. Since the influence of diffusion on the semiconductor substrate can be minimized, the reliability and yield of the semiconductor device can be improved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例の断面図。FIG. 1 is a sectional view of an embodiment of the present invention.

【図2】従来の半導体装置の一例の断面図。FIG. 2 is a sectional view of an example of a conventional semiconductor device.

【符号の説明】[Explanation of symbols]

1 P型シリコン基板 1A P+ 型シリコン基板 2 P+ 型不純物層 3 P型エピタキシャル層 4 酸化シリコン膜1 P-type silicon substrate 1A P + type silicon substrate 2 P + type impurity layer 3 P type epitaxial layer 4 Silicon oxide film

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 半導体基板上にエピタキシャル層を有す
る半導体装置において、前記エピタキシャル層と前記半
導体基板との境界部にそのエピタキシャル層と半導体基
板よりも不純物濃度の高い層を設けたことを特徴とする
半導体装置。
1. A semiconductor device having an epitaxial layer on a semiconductor substrate, wherein a layer having a higher impurity concentration than the epitaxial layer and the semiconductor substrate is provided at a boundary portion between the epitaxial layer and the semiconductor substrate. Semiconductor device.
JP31702292A 1992-11-26 1992-11-26 Semiconductor device Pending JPH06163556A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31702292A JPH06163556A (en) 1992-11-26 1992-11-26 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31702292A JPH06163556A (en) 1992-11-26 1992-11-26 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH06163556A true JPH06163556A (en) 1994-06-10

Family

ID=18083551

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31702292A Pending JPH06163556A (en) 1992-11-26 1992-11-26 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH06163556A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099476A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2017175145A (en) * 2017-05-01 2017-09-28 株式会社Sumco Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089916A (en) * 1983-10-24 1985-05-20 Matsushita Electronics Corp Manufacture of semiconductor device
JPS6466932A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Epitaxial silicon wafer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6089916A (en) * 1983-10-24 1985-05-20 Matsushita Electronics Corp Manufacture of semiconductor device
JPS6466932A (en) * 1987-09-07 1989-03-13 Fujitsu Ltd Epitaxial silicon wafer

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014099476A (en) * 2012-11-13 2014-05-29 Sumco Corp Method for manufacturing semiconductor epitaxial wafer, semiconductor epitaxial wafer, and method for manufacturing solid state image sensor
JP2017175145A (en) * 2017-05-01 2017-09-28 株式会社Sumco Semiconductor epitaxial wafer manufacturing method, semiconductor epitaxial wafer, and solid-state imaging element manufacturing method

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Effective date: 19980714