JPS6466932A - Epitaxial silicon wafer - Google Patents

Epitaxial silicon wafer

Info

Publication number
JPS6466932A
JPS6466932A JP22360687A JP22360687A JPS6466932A JP S6466932 A JPS6466932 A JP S6466932A JP 22360687 A JP22360687 A JP 22360687A JP 22360687 A JP22360687 A JP 22360687A JP S6466932 A JPS6466932 A JP S6466932A
Authority
JP
Japan
Prior art keywords
approximately
impurity concentration
type
substrate
region
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP22360687A
Other languages
Japanese (ja)
Inventor
Seiichi Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP22360687A priority Critical patent/JPS6466932A/en
Publication of JPS6466932A publication Critical patent/JPS6466932A/en
Pending legal-status Critical Current

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  • Solid State Image Pick-Up Elements (AREA)

Abstract

PURPOSE:To enable microwave heating, to inhibit substrate currents, to prevent the variation and deterioration of performance and to shorten a manufacturing process by forming a single crystal silicon substrate having specific impurity concentration, a specific high impurity concentration region shaping the surface layer section of the substrate and an epitaxial silicon layer. CONSTITUTION:A P-type region, which is shaped by using boron as an impurity and which has impurity concentration of approximately 10<18>-10<19>cm<-3>, depth of approximately 10-100mum and high concentration, a P<+> type region 2, is formed to the surface layer on the main surface side of a P-type substrate, which has impurity concentration in a 10<15>-10<16>cm<-3> order, resistivity of approximately 10-20OMEGAcm, thickness of approximately 0.5-1mm and low impurity concentration, a P<-> type silicon substrate 1, as a high impurity concentration region. A P-type epitaxial silicon layer 3 adapted for shaping a device and having resistivity of approximately 8-12OMEGAcm and thickness of approximately 10-20mum is laminated onto the main surface, the P<+> type region 2, of said P<-> type silicon substrate 1.
JP22360687A 1987-09-07 1987-09-07 Epitaxial silicon wafer Pending JPS6466932A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22360687A JPS6466932A (en) 1987-09-07 1987-09-07 Epitaxial silicon wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22360687A JPS6466932A (en) 1987-09-07 1987-09-07 Epitaxial silicon wafer

Publications (1)

Publication Number Publication Date
JPS6466932A true JPS6466932A (en) 1989-03-13

Family

ID=16800825

Family Applications (1)

Application Number Title Priority Date Filing Date
JP22360687A Pending JPS6466932A (en) 1987-09-07 1987-09-07 Epitaxial silicon wafer

Country Status (1)

Country Link
JP (1) JPS6466932A (en)

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245568A (en) * 1990-02-23 1991-11-01 Sanyo Electric Co Ltd Solid-state image sensing element
JPH03250765A (en) * 1990-02-28 1991-11-08 Sanyo Electric Co Ltd Solid-state image sensing element
JPH06163556A (en) * 1992-11-26 1994-06-10 Nec Corp Semiconductor device
JP2005175251A (en) * 2003-12-12 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor wafer and manufacturing method thereof
KR100579217B1 (en) * 1999-10-26 2006-05-11 주식회사 실트론 Method of manufacturing on p/p+ epitaxial wafers by means of low energy ion implantation
JPWO2004086488A1 (en) * 2003-03-26 2006-06-29 コマツ電子金属株式会社 Semiconductor epitaxial wafer
JP2015002329A (en) * 2013-06-18 2015-01-05 シャープ株式会社 Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device
JP2015008314A (en) * 2014-08-14 2015-01-15 株式会社Sumco Method of producing epitaxial wafer and epitaxial wafer

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03245568A (en) * 1990-02-23 1991-11-01 Sanyo Electric Co Ltd Solid-state image sensing element
JPH03250765A (en) * 1990-02-28 1991-11-08 Sanyo Electric Co Ltd Solid-state image sensing element
JPH06163556A (en) * 1992-11-26 1994-06-10 Nec Corp Semiconductor device
KR100579217B1 (en) * 1999-10-26 2006-05-11 주식회사 실트론 Method of manufacturing on p/p+ epitaxial wafers by means of low energy ion implantation
JPWO2004086488A1 (en) * 2003-03-26 2006-06-29 コマツ電子金属株式会社 Semiconductor epitaxial wafer
JP2005175251A (en) * 2003-12-12 2005-06-30 Matsushita Electric Ind Co Ltd Semiconductor wafer and manufacturing method thereof
JP2015002329A (en) * 2013-06-18 2015-01-05 シャープ株式会社 Epitaxial wafer, method for manufacturing the same, and nitride semiconductor device
JP2015008314A (en) * 2014-08-14 2015-01-15 株式会社Sumco Method of producing epitaxial wafer and epitaxial wafer

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