JPS55153347A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS55153347A
JPS55153347A JP6034379A JP6034379A JPS55153347A JP S55153347 A JPS55153347 A JP S55153347A JP 6034379 A JP6034379 A JP 6034379A JP 6034379 A JP6034379 A JP 6034379A JP S55153347 A JPS55153347 A JP S55153347A
Authority
JP
Japan
Prior art keywords
substrate
layer
single crystal
utilizing
heat treatment
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP6034379A
Other languages
Japanese (ja)
Inventor
Shigeharu Horiuchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Original Assignee
CHIYOU LSI GIJUTSU KENKYU KUMIAI
CHO LSI GIJUTSU KENKYU KUMIAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CHIYOU LSI GIJUTSU KENKYU KUMIAI, CHO LSI GIJUTSU KENKYU KUMIAI filed Critical CHIYOU LSI GIJUTSU KENKYU KUMIAI
Priority to JP6034379A priority Critical patent/JPS55153347A/en
Publication of JPS55153347A publication Critical patent/JPS55153347A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To relieve thermal strain generated during heat treatment by a method wherein on a back surface of an insulating single crystal substrate which is utilized during fabrication of an SOS structured semiconductor device, a layer which is composed of a material which has nearly equal thermal expansion coefficient as a semiconductor layer on a front surface and less hardness than the substrate is formed. CONSTITUTION:On a back surface of a sapphire substrate 1, a single crystal Si layer 2 is deposited utilizing vapor phase deposition, and a back side reinforcement is applied on the substrate 1. Next thereto on the surface of the substrate 1 a single crystal Si layer 3 on which elements are to be formed is grown by vapor phase deposition in the same way. Next thereto in the layer 3 plural number of MOS integrated circuits 41, 42 etc. are formed, being isolated by a scribing lise 5 utilizing conventional method. Next thereto they are covered by a protective film such as wax etc., and utilizing mixture of fluoric and nitric acid the layer 2 which was used as a reinforcement and now becomes useless is etched away and the substrate 1 is divided into a piece of circuit after cutting it by a diamond stylus along a scribing line. By this method deterioration of circuits can not occur in spite of heat treatment during a process.
JP6034379A 1979-05-18 1979-05-18 Manufacture of semiconductor device Pending JPS55153347A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6034379A JPS55153347A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6034379A JPS55153347A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS55153347A true JPS55153347A (en) 1980-11-29

Family

ID=13139412

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6034379A Pending JPS55153347A (en) 1979-05-18 1979-05-18 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS55153347A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05166923A (en) * 1991-12-12 1993-07-02 Nichia Chem Ind Ltd Method for cutting gallium nitride compound semiconductor wafer
US5877094A (en) * 1994-04-07 1999-03-02 International Business Machines Corporation Method for fabricating a silicon-on-sapphire wafer

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832468A (en) * 1971-08-31 1973-04-28
JPS5057381A (en) * 1973-09-19 1975-05-19
JPS5199972A (en) * 1975-02-28 1976-09-03 Nippon Electric Co HANDOTA ISOCHI

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4832468A (en) * 1971-08-31 1973-04-28
JPS5057381A (en) * 1973-09-19 1975-05-19
JPS5199972A (en) * 1975-02-28 1976-09-03 Nippon Electric Co HANDOTA ISOCHI

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05166923A (en) * 1991-12-12 1993-07-02 Nichia Chem Ind Ltd Method for cutting gallium nitride compound semiconductor wafer
US5877094A (en) * 1994-04-07 1999-03-02 International Business Machines Corporation Method for fabricating a silicon-on-sapphire wafer
US6238935B1 (en) 1994-04-07 2001-05-29 International Business Machines Corporation Silicon-on-insulator wafer having conductive layer for detection with electrical sensors

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