JPS5613737A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS5613737A
JPS5613737A JP8811679A JP8811679A JPS5613737A JP S5613737 A JPS5613737 A JP S5613737A JP 8811679 A JP8811679 A JP 8811679A JP 8811679 A JP8811679 A JP 8811679A JP S5613737 A JPS5613737 A JP S5613737A
Authority
JP
Japan
Prior art keywords
distortion layer
layer
cutting
grinding
distortion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8811679A
Other languages
Japanese (ja)
Inventor
Yukio Takano
Isao Yoshida
Kunihiro Matsukuma
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP8811679A priority Critical patent/JPS5613737A/en
Publication of JPS5613737A publication Critical patent/JPS5613737A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE:To obtain a remarkable gettering effect by a method wherein a cutting distortion layer on the surface at the element forming side is ground and removed, and thermally treated, and a portion deeper than the depth of a grinding distortion layer is removed by means of etching. CONSTITUTION:When a semiconductor substrate 1 is cut down from a crystal rod, cutting distortion layers 2, 2' are formed. The thickness is normally about 30mum. When the distortion layer 2 on one surface is ground and removed, a grinding distortion layer 3 is formed in place of the layer 2. The thickness is thick when grains are large, differs according to surface directions, but is normally about 10mum. The whole is thermally treated, and impurities in the substrate are collected to the cutting distortion layer 2' and the grinding distortion layer 3. The whole is normally treated for about three hours at 1,100 deg.C. When the grinding distortion layer 3 is removed by means of etching, there are hardly impurities and the defects of crystals on the surface of the substrate, and a residual portion is the optimum for forming a semiconductor device. The leaving of the cutting distortion layer 2' is advantageous because impurities introduced in subsequent processes and the formation of the defects of the crystals can be removed.
JP8811679A 1979-07-13 1979-07-13 Manufacture of semiconductor device Pending JPS5613737A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8811679A JPS5613737A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8811679A JPS5613737A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS5613737A true JPS5613737A (en) 1981-02-10

Family

ID=13933912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8811679A Pending JPS5613737A (en) 1979-07-13 1979-07-13 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5613737A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171485A (en) * 1983-03-18 1984-09-27 松下電器産業株式会社 Tubular heater
JPS62110292A (en) * 1985-11-08 1987-05-21 松下電器産業株式会社 Sheath heater
JPH02143532A (en) * 1988-10-03 1990-06-01 Motorola Inc Method of removing impurity in semiconductor wafer
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
JP2005093869A (en) * 2003-09-19 2005-04-07 Mimasu Semiconductor Industry Co Ltd Method of regenerating silicon wafer, and regenerated wafer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134071A (en) * 1975-05-16 1976-11-20 Nippon Denshi Kinzoku Kk Method to eliminate crystal defects of silicon

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS51134071A (en) * 1975-05-16 1976-11-20 Nippon Denshi Kinzoku Kk Method to eliminate crystal defects of silicon

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59171485A (en) * 1983-03-18 1984-09-27 松下電器産業株式会社 Tubular heater
JPS62110292A (en) * 1985-11-08 1987-05-21 松下電器産業株式会社 Sheath heater
JPH02143532A (en) * 1988-10-03 1990-06-01 Motorola Inc Method of removing impurity in semiconductor wafer
US5635414A (en) * 1995-03-28 1997-06-03 Zakaluk; Gregory Low cost method of fabricating shallow junction, Schottky semiconductor devices
JP2005093869A (en) * 2003-09-19 2005-04-07 Mimasu Semiconductor Industry Co Ltd Method of regenerating silicon wafer, and regenerated wafer

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