JPS55113332A - Manufacture of wafer - Google Patents

Manufacture of wafer

Info

Publication number
JPS55113332A
JPS55113332A JP1982579A JP1982579A JPS55113332A JP S55113332 A JPS55113332 A JP S55113332A JP 1982579 A JP1982579 A JP 1982579A JP 1982579 A JP1982579 A JP 1982579A JP S55113332 A JPS55113332 A JP S55113332A
Authority
JP
Japan
Prior art keywords
wafer
main surface
amount
thickness
symmetrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1982579A
Other languages
Japanese (ja)
Inventor
Masato Fujita
Masaru Takaishi
Takao Ishihara
Masaru Tsukahara
Hideo Shibuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP1982579A priority Critical patent/JPS55113332A/en
Publication of JPS55113332A publication Critical patent/JPS55113332A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0661—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

PURPOSE: To prevent the wafer from breaking off by a method wherein symmetrical edge bevels are provided on the edges of a wafer, and thereby head-to-break beveled parts are formed and the thickness of the outermost edge part is secured.
CONSTITUTION: By slicing an ingot, disk-shaped thin water 10 is formed. By grinding both surfaces of wafer 10, processing distortions are removed. After this, symmetrical beveled parts 11 are formed on its upper and lower edges. At this time, the outer end of wafer 10 has a certain thickness. Next, the back of main surface 12 is ground. The amount of removal is made the same as the amount of polishing of the main surface at the time when the main surface is ground later. Next, by etching wafer 10, its processing distortions are removed. Next, the main surface is polished, and the amount same as the amount of removal of the back surface is removed. Then, upper and lower edge bevels 11 are made symmetrical each other. If the upper and lower bevels are made symmetrical when the thickness of wafer 10 and the thickness of its outermost edge are set, each beveled part becomes the maximum, so that the outer edge is prevented from breaking off and the wafer is protected from being contaminated by fine broken pieces.
COPYRIGHT: (C)1980,JPO&Japio
JP1982579A 1979-02-23 1979-02-23 Manufacture of wafer Pending JPS55113332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1982579A JPS55113332A (en) 1979-02-23 1979-02-23 Manufacture of wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1982579A JPS55113332A (en) 1979-02-23 1979-02-23 Manufacture of wafer

Publications (1)

Publication Number Publication Date
JPS55113332A true JPS55113332A (en) 1980-09-01

Family

ID=12010071

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1982579A Pending JPS55113332A (en) 1979-02-23 1979-02-23 Manufacture of wafer

Country Status (1)

Country Link
JP (1) JPS55113332A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4588473A (en) * 1982-09-28 1986-05-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor wafer process
JPS61146799A (en) * 1984-12-19 1986-07-04 Shin Etsu Chem Co Ltd Single crystal wafer of lithium tantalate
US5045505A (en) * 1989-04-28 1991-09-03 Shin-Etsu Handotai Co., Ltd. Method of processing substrate for a beveled semiconductor device
US5110764A (en) * 1989-04-17 1992-05-05 Shin-Etsu Handotai Co., Ltd. Method of making a beveled semiconductor silicon wafer
EP0798405A2 (en) * 1996-03-25 1997-10-01 Shin-Etsu Handotai Co., Ltd. Method of manufacturing semiconductor wafers
EP0844046A2 (en) * 1996-10-02 1998-05-27 Ngk Insulators, Ltd. A process for machining an edge portion of a ceramic article preform without chipping

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029279A (en) * 1973-07-20 1975-03-25
JPS5310966A (en) * 1976-07-19 1978-01-31 Hitachi Ltd Semiconductor wafer
JPS5420663A (en) * 1977-07-18 1979-02-16 Toshiba Corp Grinding method of semiconductor wafers
JPS5424571A (en) * 1977-07-25 1979-02-23 Nec Corp Manufacture for semiconductor wafer

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5029279A (en) * 1973-07-20 1975-03-25
JPS5310966A (en) * 1976-07-19 1978-01-31 Hitachi Ltd Semiconductor wafer
JPS5420663A (en) * 1977-07-18 1979-02-16 Toshiba Corp Grinding method of semiconductor wafers
JPS5424571A (en) * 1977-07-25 1979-02-23 Nec Corp Manufacture for semiconductor wafer

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4588473A (en) * 1982-09-28 1986-05-13 Tokyo Shibaura Denki Kabushiki Kaisha Semiconductor wafer process
JPS61146799A (en) * 1984-12-19 1986-07-04 Shin Etsu Chem Co Ltd Single crystal wafer of lithium tantalate
JPH053438B2 (en) * 1984-12-19 1993-01-14 Shinetsu Chem Ind Co
US5110764A (en) * 1989-04-17 1992-05-05 Shin-Etsu Handotai Co., Ltd. Method of making a beveled semiconductor silicon wafer
US5045505A (en) * 1989-04-28 1991-09-03 Shin-Etsu Handotai Co., Ltd. Method of processing substrate for a beveled semiconductor device
EP0798405A2 (en) * 1996-03-25 1997-10-01 Shin-Etsu Handotai Co., Ltd. Method of manufacturing semiconductor wafers
EP0798405A3 (en) * 1996-03-25 1999-04-14 Shin-Etsu Handotai Co., Ltd. Method of manufacturing semiconductor wafers
EP0844046A2 (en) * 1996-10-02 1998-05-27 Ngk Insulators, Ltd. A process for machining an edge portion of a ceramic article preform without chipping
EP0844046A3 (en) * 1996-10-02 1998-11-18 Ngk Insulators, Ltd. A process for machining an edge portion of a ceramic article preform without chipping
US5954567A (en) * 1996-10-02 1999-09-21 Ngk Insulators, Ltd. Process for machining an edge portion of a ceramic article preform without chipping

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