JPS574115A - Manufacture of junction of semiconductors - Google Patents

Manufacture of junction of semiconductors

Info

Publication number
JPS574115A
JPS574115A JP7715180A JP7715180A JPS574115A JP S574115 A JPS574115 A JP S574115A JP 7715180 A JP7715180 A JP 7715180A JP 7715180 A JP7715180 A JP 7715180A JP S574115 A JPS574115 A JP S574115A
Authority
JP
Japan
Prior art keywords
opening
junction
substrate
type
electrode layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7715180A
Other languages
Japanese (ja)
Inventor
Masamichi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Telegraph and Telephone Corp
Original Assignee
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Telegraph and Telephone Corp filed Critical Nippon Telegraph and Telephone Corp
Priority to JP7715180A priority Critical patent/JPS574115A/en
Publication of JPS574115A publication Critical patent/JPS574115A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02436—Intermediate layers between substrates and deposited layers
    • H01L21/02439—Materials
    • H01L21/02488—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02656—Special treatments
    • H01L21/02664—Aftertreatments
    • H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Thyristors (AREA)
  • Recrystallisation Techniques (AREA)

Abstract

PURPOSE:To obtain a flat p-n junction of semiconductors on the surface of a semiconductor substrate being exposed in an opening by a method wherein an insulating film is adhered on the substrate, the opening is formed at a junction forming region, an electrode layer consisted of a semiconductor material for formation of a growth layer and a material to decide the type of conduction thereof is accumulated on the whole surface containing the opening and a heat treatment is performed. CONSTITUTION:The SiO2 film 2 is adhered on the n type Si substrate 1, and the opening is formed in the p-n junction forming region. The Al electrode layer 14 containing Si in Al is accumulated on the whole surface thereof containing the opening, the heat treatment is performed at about 500 deg.C to make Si in the electrode layer 14 to grow liquid phase epitaxially in the opening part on the substrate 1 to make a p type crystal growth layer 13 containing Al of about 2X 10<18>cm<-3> as an impurity to grow. Accordingly the flat p-n junction is formed at the interface between the surface of the n type Si substrate 1 and the p type crystal growth layer 13. Namely because the face of the p-n junction is formed on the surface without being sunk in the substrate 1, it has no curved face, and deterioration of withstand voltage is not generated. Moreover because the pattern of junction is formed in accordance with the size of the opening, the pattern of the desired shape can be obtained.
JP7715180A 1980-06-10 1980-06-10 Manufacture of junction of semiconductors Pending JPS574115A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7715180A JPS574115A (en) 1980-06-10 1980-06-10 Manufacture of junction of semiconductors

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7715180A JPS574115A (en) 1980-06-10 1980-06-10 Manufacture of junction of semiconductors

Publications (1)

Publication Number Publication Date
JPS574115A true JPS574115A (en) 1982-01-09

Family

ID=13625783

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7715180A Pending JPS574115A (en) 1980-06-10 1980-06-10 Manufacture of junction of semiconductors

Country Status (1)

Country Link
JP (1) JPS574115A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151416A (en) * 1983-02-17 1984-08-29 Agency Of Ind Science & Technol Fabrication of semiconductor crystal thin film

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151416A (en) * 1983-02-17 1984-08-29 Agency Of Ind Science & Technol Fabrication of semiconductor crystal thin film
JPH0136690B2 (en) * 1983-02-17 1989-08-02 Kogyo Gijutsuin

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