JPH0136690B2 - - Google Patents
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- Publication number
- JPH0136690B2 JPH0136690B2 JP58023805A JP2380583A JPH0136690B2 JP H0136690 B2 JPH0136690 B2 JP H0136690B2 JP 58023805 A JP58023805 A JP 58023805A JP 2380583 A JP2380583 A JP 2380583A JP H0136690 B2 JPH0136690 B2 JP H0136690B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- semiconductor
- thin film
- substrate
- single crystal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000010408 film Substances 0.000 claims description 71
- 239000010409 thin film Substances 0.000 claims description 38
- 239000013078 crystal Substances 0.000 claims description 36
- 239000004065 semiconductor Substances 0.000 claims description 34
- 239000000758 substrate Substances 0.000 claims description 29
- 229910052751 metal Inorganic materials 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 19
- 230000008018 melting Effects 0.000 claims description 14
- 238000002844 melting Methods 0.000 claims description 14
- 239000007790 solid phase Substances 0.000 claims description 13
- 229910045601 alloy Inorganic materials 0.000 claims description 9
- 239000000956 alloy Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 3
- 238000000034 method Methods 0.000 description 20
- 229910004298 SiO 2 Inorganic materials 0.000 description 19
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 11
- 229910000676 Si alloy Inorganic materials 0.000 description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052745 lead Inorganic materials 0.000 description 3
- 229910052718 tin Inorganic materials 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 2
- 238000003486 chemical etching Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000007733 ion plating Methods 0.000 description 2
- 238000005224 laser annealing Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 238000000348 solid-phase epitaxy Methods 0.000 description 2
- 238000007740 vapor deposition Methods 0.000 description 2
- 229910008813 Sn—Si Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 238000005566 electron beam evaporation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000035515 penetration Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02535—Group 14 semiconducting materials including tin
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Materials Engineering (AREA)
- Recrystallisation Techniques (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、絶縁膜上に高品質半導体結晶薄膜を
形成し、これを利用して半導体装置を製造する方
法に関する。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method of forming a high quality semiconductor crystal thin film on an insulating film and manufacturing a semiconductor device using the same.
近時、絶縁基板上に半導体単結晶薄膜を製造す
る技術が注目されているが、この技術では、SOS
（サフアイア上のシリコン）の例でも判るように
次の(1)〜(3)のような利点が得られる。
Recently, the technology to manufacture semiconductor single crystal thin films on insulating substrates has been attracting attention.
As can be seen in the example of (silicon on sapphire), the following advantages (1) to (3) can be obtained.
(1) 単結晶薄膜を島状に分離、若しくは誘電体で
分離することにより、素子間の分離を容易かつ
完全に行い得る。(1) By separating a single crystal thin film into islands or using a dielectric material, it is possible to easily and completely separate elements.
(2) 拡散やイオン注入等で不純物を半導体の絶縁
物界面まで導入する際、ｐ―ｎ接合の面積を著
しく小さくできるので、浮遊容量が小さく高速
動作が可能となる。(2) When introducing impurities to the insulator interface of a semiconductor by diffusion or ion implantation, the area of the pn junction can be significantly reduced, so stray capacitance is small and high-speed operation is possible.
(3) 単結晶薄膜上にMOSインバータを作製する
際、基板バイアス効果がないことからスイツチ
ング速度を速くすることができる。また、単結
晶薄膜が半導体単結晶基板上に堆積した絶縁膜
上に形成されたものであり、絶縁膜の一部に開
孔が存在し薄膜の一部が基板と接触している場
合、半導体表面からの電気抵抗が単結晶のため
低くなり、抵抗の大きな多結晶を絶縁膜上に堆
積したものより優れた特性が得られる。(3) When fabricating a MOS inverter on a single crystal thin film, the switching speed can be increased because there is no substrate bias effect. In addition, if a single crystal thin film is formed on an insulating film deposited on a semiconductor single crystal substrate, and a part of the insulating film has an opening and a part of the thin film is in contact with the substrate, the semiconductor Since it is a single crystal, the electrical resistance from the surface is low, resulting in superior properties compared to those made by depositing high-resistance polycrystals on an insulating film.
このような単結晶薄膜構造は、最近発達したレ
ーザアニール法や固相成長法等で部分的に可能と
なつている。レーザアニール法では、まず半導体
単結晶基板上にSiO2膜を酸化若しくは堆積によ
り形成し、このSiO2膜の一部を除去して開孔を
形成したのち、全面に多結晶Si膜を被着し、多結
晶Si膜を基板表面からSiO2膜上まで延在させる。
次いで、パルス若しくはCWレーザビーム照射
し、単結晶上の多結晶Si膜を溶融し、パルスの終
了若しくはビームの通過により多結晶Si膜が固化
する際、その固化がSiO2膜上の溶融Siにおよぶ
ようにする。その結果、基板表面で発生したエピ
タキシヤル成長がSiO2膜上のSi膜にも連らなり、
単結晶薄膜が得られることになる。しかしなが
ら、上記方法は多結晶Si膜の溶融固化を伴うた
め、得られる薄膜表面に凹凸が生じ、また薄膜の
一部が消失する虞れがあり好ましくない。 Such a single-crystal thin film structure has become partially possible using recently developed laser annealing methods, solid phase growth methods, and the like. In the laser annealing method, a SiO 2 film is first formed by oxidation or deposition on a semiconductor single crystal substrate, a portion of this SiO 2 film is removed to form an opening, and then a polycrystalline Si film is deposited on the entire surface. Then, the polycrystalline Si film is extended from the substrate surface to the top of the SiO 2 film.
Next, pulsed or CW laser beam irradiation is applied to melt the polycrystalline Si film on the single crystal, and when the polycrystalline Si film solidifies when the pulse ends or the beam passes, the solidification changes to the molten Si on the SiO 2 film. Let it spread. As a result, the epitaxial growth that occurred on the substrate surface continued to the Si film on the SiO 2 film,
A single crystal thin film will be obtained. However, since the above method involves melting and solidifying the polycrystalline Si film, the surface of the obtained thin film may be uneven and there is a risk that part of the thin film may disappear, which is not preferable.
一方、固相成長法では前述の開孔を有する単結
晶基板上絶縁膜構造を良く表面処理し、開孔部単
結晶表面を清浄にしたのち、全面に高純度のアモ
ルフアスSiを蒸着等により堆積する。次いで、電
気炉で長時間アニール、例えばSiの場合600〔℃〕
の温度でアニールする。このアニールにより、ま
ず開孔部のアモルフアスSiに固相エピタキシヤル
成長が起こり、次いで横方向の固相エピタキシヤ
ル成長が進行し、SiO2膜上に単結晶薄膜が得ら
れることになる。この場合、固相成長であるが故
に薄膜表面は平坦となる。さらに、溶融を伴わず
比較的低い温度で単結晶薄膜を得ることができ
る。しかしながら、上記方法にあつても約600
〔℃〕の温度が必要であり、この温度は既存の電
極にAl等を使用した場合には高温すぎる。すな
わち、Si基板上にMOSトランジスタその他のデ
バイスを形成し、Al配線を施したものを使用し
た場合、上記温度（600℃）でAlの突き抜けが起
こりｐ―ｎ接合がシヨートしてしまう。また、上
記方法では開孔部の接触部分から固相エピタキシ
ヤル成長が横方向に進行するのと同時に、しばし
ばSiO2膜上のアモルフアスSiの中から任意方向
の結晶核発生が起こり、得られる薄膜が多結晶化
する等の問題があつた。 On the other hand, in the solid phase growth method, the insulating film structure on a single crystal substrate with the above-mentioned openings is well surface-treated, the single crystal surface of the opening area is cleaned, and then high-purity amorphous Si is deposited on the entire surface by vapor deposition etc. do. Next, it is annealed for a long time in an electric furnace, e.g. 600 [℃] in the case of Si.
Anneal at a temperature of Through this annealing, solid phase epitaxial growth first occurs on the amorphous Si in the opening, and then solid phase epitaxial growth progresses in the lateral direction, resulting in a single crystal thin film being obtained on the SiO 2 film. In this case, since solid phase growth is used, the thin film surface becomes flat. Furthermore, a single crystal thin film can be obtained at a relatively low temperature without melting. However, even with the above method, approximately 600
A temperature of [°C] is required, and this temperature is too high when using Al or the like for existing electrodes. That is, when a MOS transistor or other device is formed on a Si substrate and is provided with Al wiring, penetration of the Al occurs at the above temperature (600° C.) and the pn junction is shorted. In addition, in the above method, at the same time that solid-phase epitaxial growth progresses laterally from the contact area of the opening, crystal nucleation often occurs in arbitrary directions from the amorphous Si on the SiO 2 film, and the resulting thin film There were problems such as polycrystallization.
本発明の目的は、通常の固相成長法より低い温
度で絶縁物上に高品質半導体結晶薄膜を形成し、
これを利用して半導体装置を製造する方法を提供
することにある。
The purpose of the present invention is to form a high-quality semiconductor crystal thin film on an insulator at a lower temperature than normal solid phase growth methods,
An object of the present invention is to provide a method of manufacturing a semiconductor device using this.
本発明の骨子は、固相成長法におけるアモルフ
アス半導体の堆積に代りに、半導体を多量に含有
した低融点金属膜、或いは半導体と低融点金属と
の合金膜を堆積することにある。
The gist of the present invention is to deposit a low melting point metal film containing a large amount of semiconductor, or an alloy film of a semiconductor and a low melting point metal, instead of depositing an amorphous semiconductor in the solid phase growth method.
すなわち本発明は、絶縁膜上に半導体結晶薄膜
を製造する方法において、単結晶半導体基板上に
絶縁膜を選択形成したのち、基板及び絶縁膜上に
半導体を含有する低融点金属或いは半導体と低融
点金属との合金膜を被着し、次いで上記金属或い
は合金膜をアニールし上記半導体を基板表面から
絶縁膜上にわたつて固相エピタキシヤル成長せし
め、絶縁膜上に固相エピタキシヤル成長した半導
体結晶薄膜にトランジスタを形成するようにした
方法である。 That is, the present invention provides a method for manufacturing a semiconductor crystal thin film on an insulating film, in which an insulating film is selectively formed on a single crystal semiconductor substrate, and then a low melting point metal containing a semiconductor or a semiconductor and a low melting point metal is formed on the substrate and the insulating film. An alloy film with a metal is deposited, and then the metal or alloy film is annealed to cause the semiconductor to grow solid-phase epitaxially from the substrate surface onto the insulating film, thereby producing a semiconductor crystal grown in solid-phase epitaxially on the insulating film. This is a method in which a transistor is formed in a thin film.
〔発明の効果〕
本発明によれば、通常の固相成長法より低温の
熱処理で金属膜若しくは合金膜中の半導体原子が
拡散し、絶縁膜の開孔部における単結晶基板表面
から固相エピタキシヤル成長が起こる。このた
め、通常の固相成長法よりも低い温度で単結晶薄
膜を得ることができる。ここで、前記半導体を例
えばSiとし低融点金属としてAlを用いると、エ
ピタキシヤル成長したSi中に多量のAlが含有さ
れ、トランジスタ形成には不向きな高濃度のP+
の単結晶薄膜が形成されるので、好ましくない。
したがつて、低融点金属としてはSiと同じ族の
SnやPb等を用いればよい。Sn、Pbのいずれを用
いた場合にあつても300〔℃〕程度のアニールによ
り単結晶薄膜が得られ、Sn及びPbが族で中性
であるため薄膜の電気的特性も良好なものとな
る。また、本発明によれば非晶質絶縁膜上に単結
晶薄膜を製造し得ることから、高価なサフアイア
基板を用いる必要がなく、製造コストの低減化を
はかり得る等の利点がある。さらに、アモルフア
スSiを用いた場合のような任意方向の結晶核発生
が起こり、得られる薄膜が多結晶化する等の不都
合はない。[Effects of the Invention] According to the present invention, semiconductor atoms in a metal film or an alloy film are diffused by heat treatment at a lower temperature than that in a normal solid phase epitaxy method, and solid phase epitaxy occurs from the surface of a single crystal substrate in an opening in an insulating film. Growth will occur. Therefore, a single-crystal thin film can be obtained at a lower temperature than in a normal solid-phase growth method. Here, if the semiconductor is Si, for example, and Al is used as the low melting point metal, a large amount of Al will be contained in the epitaxially grown Si, resulting in a high concentration of P + that is unsuitable for forming a transistor.
This is not preferable because a single crystal thin film of
Therefore, low melting point metals include those in the same group as Si.
Sn, Pb, etc. may be used. Regardless of whether Sn or Pb is used, a single-crystal thin film can be obtained by annealing at about 300 [℃], and since Sn and Pb are neutral in the group, the electrical properties of the thin film are also good. . Further, according to the present invention, since a single crystal thin film can be manufactured on an amorphous insulating film, there is no need to use an expensive sapphire substrate, and there are advantages such as reduction in manufacturing costs. Furthermore, unlike when amorphous Si is used, there are no disadvantages such as generation of crystal nuclei in arbitrary directions and polycrystalline formation of the resulting thin film.
第１図ａ，ｂは本発明の一実施例に係わる単結
晶Si薄膜製造工程を示す断面図である。まず、第
１図ａに示す如く（100）Si単結晶基板１の上面
を熱酸化し、厚さ2000〔Å〕のSiO2膜２を形成す
る。次いで、基板１上の半分のSiO2膜２を直線
状の境界で除去する。この試料をH2O：HF＝
20：１程度の希弗酸で表面処理し、水滴を切つて
そのまま真空チエンバの中に入れる。この処理に
より基板１の表面には、所謂自然酸化膜は殆んど
発生しない。次いで、10-8〔Torr〕の真空中で堆
積合金中のSi濃度が所定の値、例えば15〔％〕と
なるように、第１図ｂに示す如くSn―Si合金膜
３を電子ビーム同時蒸着で厚さ1.5〔μm〕程度被
着する。
FIGS. 1a and 1b are cross-sectional views showing the manufacturing process of a single-crystal Si thin film according to an embodiment of the present invention. First, as shown in FIG. 1a, the upper surface of a (100) Si single crystal substrate 1 is thermally oxidized to form a SiO 2 film 2 with a thickness of 2000 Å. Next, half of the SiO 2 film 2 on the substrate 1 is removed along the linear boundary. This sample is H 2 O: HF=
The surface is treated with dilute hydrofluoric acid (about 20:1), water droplets are removed, and the material is placed directly into a vacuum chamber. Due to this treatment, almost no so-called natural oxide film is generated on the surface of the substrate 1. Next, the Sn--Si alloy film 3 is simultaneously exposed to electron beams as shown in FIG . It is deposited to a thickness of about 1.5 [μm] by vapor deposition.
次に、上記試料をN2を流した電気炉に入れ、
350〔℃〕の温度で熱処理を行う。この熱処理の
100時間経過後、表面のSn―Si合金膜３を希塩酸
で溶解しSiO2膜２上を光学顕微鏡で観察したと
ころ、単結晶Si薄膜が折出しているのが判明し
た。また、基板１を裏面からの化学エツチングに
より薄くしTEM（透過型電子顕微鏡）で観察した
ところ、基板１表面は勿論、基板１表面から
SiO2膜２上に単結晶Si薄膜が約10〔μm〕伸びてい
ることが判明した。さらに、SiO2膜２の端から
10〔μm〕以上離れたところでは、Si結晶は折出し
ていなかつた。 Next, the above sample was placed in an electric furnace flowing N2 ,
Heat treatment is performed at a temperature of 350 [℃]. This heat treatment
After 100 hours had passed, the Sn--Si alloy film 3 on the surface was dissolved with dilute hydrochloric acid and the top of the SiO 2 film 2 was observed with an optical microscope, and it was found that a single crystal Si thin film had been precipitated. In addition, when the substrate 1 was thinned by chemical etching from the back side and observed with a TEM (transmission electron microscope), it was found that not only the surface of the substrate 1 but also the surface of the substrate 1 was etched.
It was found that the single-crystal Si thin film extended about 10 [μm] on the SiO 2 film 2. Furthermore, from the edge of SiO 2 film 2
No Si crystal was precipitated at a distance of 10 μm or more.
このように本実施例では、SiO2膜２上での単
結晶Si薄膜の固相エピタキシヤル成長を500〔℃〕
以下の低温で行うことができる。このため、単結
晶Si薄膜形成に極めて有効である。なお、Si薄膜
の成長は前記Sn―Si合金膜３中のSiが拡散によ
り基板１、つまりSi単結晶例に移動して折出する
ものと考えられる。 In this way, in this example, solid phase epitaxial growth of a single crystal Si thin film on SiO 2 film 2 was performed at 500 [°C].
It can be carried out at low temperatures such as: Therefore, it is extremely effective for forming single-crystal Si thin films. It is considered that the growth of the Si thin film is caused by the Si in the Sn--Si alloy film 3 moving to the substrate 1, that is, an example of a Si single crystal, by diffusion and being precipitated.
第２図ａ〜ｅは他の実施例に係わる単結晶Si薄
膜製造工程を示す断面図である。この実施例で
は、まず第２図ａに示す如く（100）Si単結晶基
板１上にSiO2膜２をLPCVD法で厚さ3000〔Å〕
堆積する。次いで、第２図ｂに示す如くSiO2膜
２を幅20〔μm〕のストライプ状に残し、その間隔
３〔μm〕部分５を開孔部となるべくエツチングし
て単結晶基板１を露出せしめる。この試料を〜
10-10〔Torr〕の高真空中、温度1000〔℃〕に10分
間保持し、露出単結晶表面の自然酸化膜を除去す
る。次いで、先の実施例と同様に電子ビーム蒸着
法を用い、第２図ｃに示す如くSiの含有量５〔％〕
のSn―Si合金膜６を厚さ１〔μm〕程度被着する。 FIGS. 2a to 2e are cross-sectional views showing the manufacturing process of a single-crystal Si thin film according to another embodiment. In this example, first, as shown in FIG. 2a, a SiO 2 film 2 is deposited on a (100) Si single crystal substrate 1 to a thickness of 3000 Å using the LPCVD method.
accumulate. Next, as shown in FIG. 2b, the SiO 2 film 2 is left in the form of stripes with a width of 20 [μm], and the portions 5 with a spacing of 3 [μm] are etched to form openings to expose the single crystal substrate 1. This sample ~
10 -10 [Torr] in a high vacuum at a temperature of 1000 [℃] for 10 minutes to remove the natural oxide film on the exposed single crystal surface. Next, as in the previous example, using the electron beam evaporation method, the Si content was reduced to 5% as shown in Figure 2c.
A Sn--Si alloy film 6 of approximately 1 [μm] in thickness is deposited.
次に、上記試料を350〔℃〕の温度で100時間ア
ニールする。その後、第２図ｂに示す如くイオン
プレーテイング法によりSn―Si合金膜６の表面
付近にSiを１×1018〔cm-2〕埋め込み、続いて350
〔℃〕で100時間の熱処理を施した。これにより、
第２図ｅに示す如くSiO2膜３上に単結晶Si薄膜
７が成長形成されることになる。なお、Siのイオ
ンプレーテイングはSn―Si合金膜６中のSi濃度
を高めるための方法である。上記試料において、
Sn―Si合金膜６を希塩酸でエツチングし光学顕
微鏡で観察したところ、20〔μm〕幅のSiO2膜２
上に折出しているのが見られた。また、基板１を
裏面からの化学エツチングにより薄くしTEMで
観察したところ、SiO2膜２上のSi薄膜７はその
80〔％〕が基板１と同じ結晶方位を有することが
判明した。なお、Si薄膜７の膜厚は約1000〔Å〕
であつた。 Next, the above sample is annealed at a temperature of 350 [° C.] for 100 hours. Thereafter, as shown in FIG. 2b, 1×10 18 [cm -2 ] of Si was embedded near the surface of the Sn-Si alloy film 6 by ion plating, and then 350
Heat treatment was performed at [℃] for 100 hours. This results in
As shown in FIG. 2e, a single crystal Si thin film 7 is grown on the SiO 2 film 3. Note that Si ion plating is a method for increasing the Si concentration in the Sn--Si alloy film 6. In the above sample,
When the Sn--Si alloy film 6 was etched with dilute hydrochloric acid and observed with an optical microscope, it was found that the SiO 2 film 2 was 20 [μm] wide.
It was seen folding upward. In addition, when the substrate 1 was thinned by chemical etching from the back side and observed with a TEM, it was found that the Si thin film 7 on the SiO 2 film 2 was
It was found that 80% had the same crystal orientation as substrate 1. The thickness of the Si thin film 7 is approximately 1000 Å.
It was hot.
かくして本実施例によつても、先の実施例と同
様の効果が得られる。また、実施例で得られた単
結晶Si薄膜７上に第３図に示す如くMOSトラン
ジスタを作製し、その電気測定を行つたところ電
子移動度500〔cm2／υ・sec〕が得られた。この値
はバルク半導体上のそれよりは小さい（約1/2）
がトランジスタ素子として動作するには十分大き
な値である。なお、第３図中８はゲート酸化膜、
９はゲート電極を示し、また７ａ，７ｂはソー
ス・ドレイン領域を示している。 Thus, this embodiment also provides the same effects as the previous embodiment. Furthermore, when a MOS transistor was fabricated as shown in FIG. 3 on the single crystal Si thin film 7 obtained in the example and electrical measurements were performed, an electron mobility of 500 [cm 2 /υ・sec] was obtained. . This value is smaller (about 1/2) than that on bulk semiconductors.
is a sufficiently large value to operate as a transistor element. In addition, 8 in FIG. 3 is a gate oxide film,
Reference numeral 9 indicates a gate electrode, and 7a and 7b indicate source/drain regions.
なお、本発明は上述した各実施例に限定される
ものではない。例えば、前記Sn―Si合金膜の代
りには、Siを多量に含むSn金属膜を用いてもよ
い。また、低融点金属としてのSnの代りには、
Siと同じ族のPbを使用することも可能である。
さらに、半導体としてSiの他に、Geや―族
化合物半導体に適用することもできる。―族
化合物半導体に適用する場合、低融点金属として
は族の金属を用いればよい。また、半導体を多
量に含む低融点金属膜或いは半導体と低融点金属
との合金膜中における半導体の割合は、仕様に応
じて適宜定めればよい。さらに、絶縁膜の選択形
成方法及び上記合金膜や金属膜等の被着方法は、
何ら実施例に限定されるものでなく、適宜変更可
能である。その他、本発明の要旨を逸脱しない範
囲で、種々変形して実施することができる。 Note that the present invention is not limited to each of the embodiments described above. For example, instead of the Sn--Si alloy film, an Sn metal film containing a large amount of Si may be used. Also, instead of Sn as a low melting point metal,
It is also possible to use Pb from the same group as Si.
Furthermore, in addition to Si, the present invention can also be applied to Ge and - group compound semiconductors. When applied to - group compound semiconductors, metals from the group may be used as the low melting point metal. Further, the proportion of the semiconductor in a low melting point metal film containing a large amount of semiconductor or an alloy film of a semiconductor and a low melting point metal may be determined as appropriate depending on the specifications. Furthermore, the method for selectively forming the insulating film and the method for depositing the alloy film, metal film, etc.
The present invention is not limited to the embodiments and can be modified as appropriate. In addition, various modifications can be made without departing from the gist of the present invention.
第１図ａ，ｂは本発明の一実施例に係わる単結
晶Si薄膜製造工程を示す断面図、第２図ａ〜ｅは
他の実施例を説明するための工程断面図、第３図
は上記他の実施例により得た単結晶Si薄膜上に作
製したMOSトランジスタ構造を示す断面図であ
る。
１…Si単結晶基板、２…SiO2膜（絶縁膜）、
３，６…Sn―Si合金膜、５…開孔部、７…単結
晶Si薄膜、７ａ，７ｂ…ソース・ドレイン領域、
８…ゲート酸化膜、９…ゲート電極。
FIGS. 1a and 1b are cross-sectional views showing the manufacturing process of a single-crystal Si thin film according to one embodiment of the present invention, FIGS. 2 a to e are process cross-sectional views for explaining another embodiment, and FIG. FIG. 3 is a cross-sectional view showing a MOS transistor structure fabricated on a single-crystal Si thin film obtained in another example. 1...Si single crystal substrate, 2...SiO 2 film (insulating film),
3, 6... Sn--Si alloy film, 5... Opening part, 7... Single crystal Si thin film, 7a, 7b... Source/drain region,
8... Gate oxide film, 9... Gate electrode.
Claims (1)
工程と、上記基板及び絶縁膜上に半導体を含有す
る該半導体と同族元素の低融点金属膜或いは半導
体と該半導体と同族元素の低融点金属との合金膜
を被着する工程と、上記金属膜或いは合金膜をア
ニールし、前記半導体を前記基板表面から前記絶
縁膜上にわたつて固相エピタキシヤル成長せしめ
る工程と、この絶縁膜上に固相エピタキシヤル成
長した半導体結晶薄膜にトランジスタを形成する
工程とを具備したことを特徴とする半導体装置の
製造方法。1. A step of selectively forming an insulating film on a single crystal semiconductor substrate, and a low melting point metal film of an element of the same group as the semiconductor containing a semiconductor on the substrate and the insulating film, or a low melting point metal of the semiconductor and an element of the same group as the semiconductor. a step of depositing an alloy film on the insulating film; a step of annealing the metal film or alloy film to cause solid phase epitaxial growth of the semiconductor from the surface of the substrate onto the insulating film; 1. A method of manufacturing a semiconductor device, comprising the step of forming a transistor in an epitaxially grown semiconductor crystal thin film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2380583A JPS59151416A (en) | 1983-02-17 | 1983-02-17 | Fabrication of semiconductor crystal thin film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2380583A JPS59151416A (en) | 1983-02-17 | 1983-02-17 | Fabrication of semiconductor crystal thin film |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59151416A JPS59151416A (en) | 1984-08-29 |
| JPH0136690B2 true JPH0136690B2 (en) | 1989-08-02 |
Family
ID=12120537
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2380583A Granted JPS59151416A (en) | 1983-02-17 | 1983-02-17 | Fabrication of semiconductor crystal thin film |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59151416A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574115A (en) * | 1980-06-10 | 1982-01-09 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of junction of semiconductors |
-
1983
- 1983-02-17 JP JP2380583A patent/JPS59151416A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS574115A (en) * | 1980-06-10 | 1982-01-09 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of junction of semiconductors |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59151416A (en) | 1984-08-29 |
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