JPH0832037A - Manufacture of semiconductor substrate - Google Patents

Abstract

PURPOSE:To reduce remaining crystal defects, improve semiconductor characteristics, and avoid deterioration of semiconductor characteristics caused by the new surface level. CONSTITUTION:In a manufacturing method of a semiconductor substrate wherein after a semiconductor layer 3 formed on a first substratum 1 is stuck on a second substratum 6, the first substratum 1 is selectively eliminated to leave the semiconductor layer 3, an amorphous region is re-crystallized by heat treatment at a temperature lower than the melting point before the sticking of the substratums, after at least crystal defect existing in the semiconductor layer 3 on the first substratum 1 is selectively turned into the amorphous state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor substrate, and more particularly to a method for manufacturing a semiconductor substrate suitable for manufacturing an epitaxial silicon-on-silicon wafer and a silicon-on-insulator.

[0002]

2. Description of the Related Art SOI substrates are useful in performing element isolation required for integrated circuit fabrication. As a technique for realizing this, in Japanese Patent Laid-Open No. 5-21338, an epitaxial silicon layer is grown on porous silicon, and then this substrate is bonded to a second substrate via an insulating layer, and the first substrate is placed on the back surface. A method of forming an SOI substrate is disclosed in which the removal is further performed and the porous layer is also removed. However, in this known method, crystal defects may exist in single crystal silicon grown from porous silicon. Further, crystal defects may be introduced even when growing at a low temperature in order to suppress the diffusion of impurities.

It is also widely practiced to manufacture an SOI substrate by epitaxial growth on a single crystal substrate, but if there is a lattice mismatch between the substrate and the epitaxial growth layer, crystal defects will be introduced. For example, in silicon epitaxial growth (SOS) on sapphire,
It has been reported that many crystal defects such as micro twins due to the difference in lattice constant between the substrate material and the single crystal thin layer occur near the interface between the epitaxial layer and the substrate.

In order to reduce these crystal defects, Inoue et al., In JP-A-56-45047 discloses an epitaxial silicon layer formed on sapphire by performing a first random ion implantation to form an epitaxial film having many crystal defects. After amorphizing the lower portion of the silicon layer, heat treatment is performed to recover crystallinity by solid-phase epitaxial growth from the upper portion of the non-amorphous epitaxial silicon to reduce crystal defects in the epitaxial silicon. After that, similarly, random ion implantation is performed to amorphize the upper portion of the epitaxial silicon layer and then heat treatment is performed, and single crystal is grown by solid phase epitaxial growth from the lower portion of the epitaxial silicon layer where the crystal defect density is reduced by the first random ion implantation. It forms a thin layer.

Further, LAU, etc. are described in Appl. Phys. L
ett. 34 (1), 1 January, 76, 197.
9 shows that crystal defects of epitaxial silicon on sapphire are reduced by channeling ion implantation and solid phase growth.

On the other hand, the crystal defect density generally confirmed by homoepitaxial growth of a silicon single crystal by CVD on a silicon single crystal substrate is 10 ² / cm ² or less, but in order to suppress the diffusion of impurities, the temperature is low. Even when grown, the crystal defects may increase. Further, it is known that when epitaxially growing on porous silicon, many crystal defects such as stacking faults, micro twins, and dislocations exist.

[0007]

In the SOI substrate, crystal defects in the silicon layer have a problem that carrier mobility is lowered and leak current is increased. Reducing crystal defects in the silicon layer is essential for improving the characteristics of integrated circuits. The crystal defects include stacking faults, dislocations, and micro twins. In particular, stacking faults and dislocations often penetrate in the film thickness direction. Inoue et al. Examined the random ion implantation method in Japanese Patent Laid-Open No. 56-45047, and Lau et al.
ppl. Phys. Lett. 34 (1), 1Janu
The channel ion implantation method studied by Ary, 76, 1979 recovered the crystal defects existing at a specific depth in the film, but for stacking faults and dislocations continuously distributed in the film thickness direction, a part thereof was recovered. Since only the region containing is amorphized, it is necessary to remove these defects by regrowth of stacking faults and dislocations remaining in the non-amorphized portion at the stage of recovering the crystallinity by the subsequent heat treatment. Was difficult.

Further, when the crystal defects are reduced by the ion implantation method after the SOI substrate is manufactured, if atomic mixing occurs at the interface between the semiconductor layer and the insulating layer, a new interface level is generated and the leak current increases, Strict control of the implantation energy was necessary because it leads to the incorporation of impurities into the semiconductor layer. Therefore, at the interface between the semiconductor layer having the most crystal defects and the insulating layer, amorphization becomes insufficient, and it is difficult to recover the defects by heat treatment.

Further, in the method disclosed in Japanese Patent Laid-Open No. 5-21338, the crystal defects are selectively etched in the chemical etching carried out when the porous layer is removed, and the etchant invades so that the buried insulating layer is formed. The layer may be eroded to form voids on the bonding surface of the first substrate and the second substrate.

The present invention is intended to produce a semiconductor substrate having no crystal defects by selectively recovering dislocations, stacking faults, and crystal defects near the interface between the semiconductor layer and the insulating layer, which often penetrate in the film thickness direction.

[0011]

According to a method of manufacturing a semiconductor substrate of the present invention, a semiconductor layer formed on a first substrate is bonded to a second substrate, and then the first substrate is left as the semiconductor layer. In the method for manufacturing a semiconductor substrate which is selectively removed by selective removal, at least crystal defects existing in the semiconductor layer on the first substrate are selectively amorphized before bonding the two substrates, and then the melting point is smaller than the melting point. The amorphous region is recrystallized by heat treatment at a temperature.

In the present invention, in order to selectively amorphize the crystal defects existing in the semiconductor layer formed on the first substrate, channeling ion implantation is performed from an orientation other than the dislocation line to form a film. This is performed by selectively amorphizing only stacking faults and dislocations, which are crystal defects penetrating in the thickness direction, and the vicinity thereof, and then by solid phase epitaxial growth with the crystal part distributed throughout the semiconductor layer as a nucleus. After forming a semiconductor single crystal layer having no crystal defects and further bonding it to a second substrate having an insulating layer on at least the surface thereof, the single crystal lower portion on the first substrate is selectively removed to obtain interface steepness. It is possible to provide a good SOI substrate.

The present invention will be described in more detail below. In a single crystal, a channel having a relatively sparse electron density is formed surrounded by rows of lattice atoms along a low index axis or a low index plane. In general, the ions injected along the channel give energy to the outer shell electrons of the lattice atoms while propagating at a small angle with the lattice atoms of the crystal. Compared to the case of implanting from a random direction, it can be implanted to a deep position with the same energy.

Now, consider the case where a crystal defect exists in the single crystal layer. Since the atoms in the crystal defect portion are present at positions deviated from the crystal lattice, the ions traveling along the channeling have a high probability of colliding with only the atoms in the crystal defect portion. As a result, the crystal defect portion and its vicinity are selectively made amorphous. The present inventor, as shown in Examples to be described later, selectively amorphizes crystal defects by performing channeling ion implantation on a single crystal silicon formed on a silicon substrate from a specific orientation to include the defects. It was found that the original single crystallinity can be maintained in the non-existing part. Further, the present inventor has performed a heat treatment on a sample in which only the crystal defect portion is selectively made amorphous, so that the amorphous region surrounded by the single crystal regions is a single crystal region. It was confirmed that solid-phase epitaxial growth from No. 1 made a single crystal and no new crystal defects were introduced.

Prior to fabricating the SOI structure, the present invention
In order to perform channeling ion implantation, Inoue et al. Have previously disclosed the method disclosed in Japanese Patent Laid-Open No. 56-45047 and Lau et al.
ppl. Phys. Lett. 34 (1), 1Janu
Compared with the case where the method shown in Ary, 76, 1979 is used to perform ion implantation after the SOS structure is formed, stacking faults, dislocations, and semiconductor layers that often penetrate the single crystal silicon layer particularly in the film thickness direction. We have found an effect on amorphization of many crystal defects near the interface of the insulating layer.

Further, by eliminating the crystal defects existing in the semiconductor layer, even the chemical etching which is carried out when removing the porosity disclosed in Japanese Patent Laid-Open No. 21338/1993 is applied by selective etching of a specific portion. The generation of voids at the mating interface is also improved.

[0017]

Embodiments of the present invention will be described in detail below with reference to the drawings. [Embodiment 1] FIGS. 1 (a) to 1 (d) are sectional views showing the manufacturing steps of the first embodiment of the method for producing a semiconductor substrate of the present invention.

As shown in FIG. 1A, 5 inches <00
1> Single-crystal silicon wafer 1 is anodized in a mixed solution of HF aqueous solution and alcohol to be porous to form porous silicon layer 2, and then epitaxial silicon layer 3 is formed on porous silicon layer 2 by CVD method. Grow.
Dislocation lines 4 having [011] direction, [134] direction and [112] direction were confirmed in the silicon layer 3 by a transmission electron microscope.

Other than in the dislocation line direction of the crystal of the silicon layer 3
Si from a direction within 1 ° to the channeling direction⁺I
On, C⁺Ion, Ge⁺Ion or Pb⁺Ion
1 × 10¹³~ 1 × 10¹⁴atoms / cm²inject.
<100> is preferable to <111> as the injection direction.
Yes. Since the implanted ions are channeled, the
It collides with only the child and amorphizes the vicinity including dislocations. Also,
No defects are observed by TEM observation, and amorphous regions are scattered.
I was sure that. In other areas, it is a single crystal.
It was confirmed by electron diffraction. Impulse with injected ions
When it becomes amorphous due to a collision, the implanted ions remain at that position.
Therefore, the implanted ions are the same group IV ions as silicon.
It is preferable to use ON. Or, the inert gas Io
Can also be used. As shown in FIG. 1 (b),
N after injection₂Heat treatment at 1000 ° C for 2 hours in an atmosphere
To recover the crystallinity of the amorphous part by solid phase growth.
Was. No defects were confirmed by TEM observation. In addition,
Co-etching (K₂Cr₂O ₇To HF + H₂Diluted with O
Undiluted solution undiluted solution: HF: H₂Liquid diluted with O = 1: 2: 3
Defects are revealed even after etching for 3 min.
There was no.

Next, as shown in FIG. 1 (c), the single crystal
The recon layer 3 is made of SiO 2 with a thickness of 0.5 μm. ₂Has layer 5 on the surface
Bonded with silicon wafer 6₂10 in the atmosphere
It was completely adhered by heat treatment at 00 ° C. for 2 hours. Ion implantation
The heat treatment to recover the post-crystallinity should be omitted.
Alternatively, only the heat treatment in the bonding step may be performed.

Next, as shown in FIG. 1D, 49% H
F: 70% HNO ₃ : CH ₃ COOH = 1.2: 10:
After etching the back surface of the substrate with 10 liquid to expose the porous silicon, the porous silicon was removed by etching with 49% HF: 30% H ₂ O ₂ = 1: 5 liquid to manufacture an SOI substrate.

In the SOI silicon layer manufactured according to the present invention, the defect portion penetrating in the film thickness direction, which is seen in the SOI silicon layer manufactured by the method disclosed in Japanese Patent Application Laid-Open No. Hei 5-21338, is formed. It was not found, and the formation of voids at the bonding interface could be suppressed to 1/3 of the conventional case. [Embodiment 2] FIGS. 2A to 2D are sectional views showing the manufacturing steps of the second embodiment of the method for manufacturing a semiconductor substrate of the present invention.

As shown in FIG. 2A, 5 inches <00
1> Single-crystal silicon wafer 1 is anodized in a mixed solution of HF aqueous solution and alcohol to be porous to form porous silicon layer 2, and then epitaxial silicon layer is formed on porous silicon layer 2 by CVD method. Grow 3 Dislocation lines 4 having [011] direction, [134] direction and [112] direction were confirmed in the silicon layer 3 by a transmission electron microscope.

Other than the dislocation line direction of the crystal of the silicon layer 3
Si from a direction within 1 ° to the channeling direction⁺I
On, C⁺Ion, Ge⁺Ion or Pb⁺Ion
1 × 10¹³~ 1 × 10¹⁴atoms / cm²inject.
<100> is preferable to <111> as the injection direction.
Yes. Since the implanted ions are channeled, the
It collides with only the child and amorphizes the vicinity including dislocations. Also,
No defects are observed by TEM observation, and amorphous regions are scattered.
I was sure that. In other areas, it is a single crystal.
It was confirmed by electron diffraction. Impulse with injected ions
When it becomes amorphous due to a collision, the implanted ions remain at that position.
Therefore, the implanted ions are the same group IV ions as silicon.
It is preferable to use ON. Or, the inert gas Io
Can also be used. As shown in FIG. 2 (b),
N after injection₂Heat treatment at 1000 ° C for 2 hours in an atmosphere
To recover the crystallinity of the amorphous part by solid phase growth.
Was. No defects were confirmed by TEM observation. In addition,
Co-etching (K₂Cr₂O ₇To HF + H₂Diluted with O
Undiluted solution undiluted solution: HF: H₂Liquid diluted with O = 1: 2: 3
Defects are revealed even after etching for 3 min.
There was no.

Next, as shown in FIG. 2 (c), the single crystal silicon layer 3 is bonded to a second substrate 8 such as an aluminum substrate having an aluminum oxide layer 7 on at least the surface thereof, and then in a N ₂ atmosphere. It was made to adhere by heat treatment at 1000 ° C. for 2 hours.

Next, as shown in FIG. 2D, 49% H
F: 70% HNO ₃ : CH ₃ COOH = 1.2: 10:
After etching the back surface of the substrate with 10 liquid to expose the porous silicon, 49% HF: 30% H ₂ O ₂ = 1: 5 liquid is used to etch and remove the porous silicon to obtain an SOI substrate without crystal defects. It was made.

Sapphire can be used as the second substrate. 3A to 3C are cross-sectional views of the manufacturing process in this case.
It is shown in (d). In the figure, 9 indicates a sapphire substrate.

In each of the embodiments described above, since the crystal defects are eliminated and the second substrate is bonded to the second substrate, the steepness of the interface between the semiconductor layer and the insulating layer is good, and the unevenness introduced into the interface by ion implantation is good. It is possible to improve the decrease in carrier mobility due to.

[0029]

As described above, according to the present invention, it is possible to reduce residual crystal defects in an SOI substrate or the like, which has been a problem in the past, and to improve semiconductor characteristics. Further, according to the present invention, atomic agitation in the vicinity of the single crystal layer and the insulating layer, which is introduced by ion implantation in the conventional method, is suppressed in the present invention, so that deterioration of semiconductor characteristics due to generation of a new interface state can be avoided.

[Brief description of drawings]

1A to 1D are cross-sectional views of a manufacturing process of a first embodiment of a method for manufacturing a semiconductor substrate of the present invention.

2A to 2D are cross-sectional views of a manufacturing process of a second embodiment of the method for manufacturing a semiconductor substrate of the present invention.

3A to 3D are cross-sectional views of a manufacturing process when sapphire is used as the second substrate.

[Explanation of symbols]

1 Single Crystal Silicon Wafer 2 Porous Silicon Layer 3 Epitaxial Silicon Layer 4 Dislocation Lines (Crystal Defects) 5 SiO ₂ Layer 6 Silicon Wafer 7 Aluminum Oxide Layer 8 Aluminum Substrate 9 Sapphire Substrate

Claims (8)

[Claims] 1. A method for manufacturing a semiconductor substrate, comprising: bonding a semiconductor layer formed on a first substrate to a second substrate; and then selectively removing the first substrate while leaving the semiconductor layer. Prior to bonding the substrates, at least crystal defects existing in the semiconductor layer on the first substrate are selectively amorphized, and then a heat treatment is performed at a temperature lower than the melting point to recrystallize the amorphous regions. A method for manufacturing a semiconductor substrate, wherein the method comprises: 2. The method for manufacturing a semiconductor substrate according to claim 1, wherein the first substrate has a porous layer on at least a surface thereof. 3. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second substrate has a silicon oxide layer on at least a surface thereof. 4. The method for manufacturing a semiconductor substrate according to claim 1, wherein the second substrate has an aluminum oxide layer on at least a surface thereof. 5. The method of manufacturing a semiconductor substrate according to claim 1, wherein the second substrate is sapphire. 6. The method of manufacturing a semiconductor substrate according to claim 1, wherein the selective amorphization of the crystal defects is performed by implanting channeling ions into the semiconductor layer. 7. The production of a semiconductor substrate according to claim 6, wherein the selective amorphization of the crystal defects is performed by channeling ion implantation from a direction other than a dislocation line existing in the semiconductor layer. Method. 8. The semiconductor according to claim 6, wherein the channeling ion implantation is performed by an ion of an element in the same group as an element forming the semiconductor layer or an ion of an inert gas. Substrate manufacturing method.