JPH0590394A - Semiconductor device - Google Patents
Semiconductor deviceInfo
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- JPH0590394A JPH0590394A JP24752791A JP24752791A JPH0590394A JP H0590394 A JPH0590394 A JP H0590394A JP 24752791 A JP24752791 A JP 24752791A JP 24752791 A JP24752791 A JP 24752791A JP H0590394 A JPH0590394 A JP H0590394A
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- Prior art keywords
- layer
- film layer
- groove
- insulating film
- reaching
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は，半導体装置，特にＳＯ
Ｉ基板における溝アイソレーションに関する。BACKGROUND OF THE INVENTION The present invention relates to a semiconductor device, especially SO.
The present invention relates to groove isolation in an I substrate.
【０００２】ＳＯＩ(Semiconductor On Insulator ／ S
ilicon On Insulator)基板は，完全素子分離が可能であ
るので，ＳＯＩ基板を用いて作製した半導体装置には，
ラッチアップフリー，ノイズフリーといった種々の有利
さがある。この点から，ＳＯＩ基板を用いた半導体装置
の開発が盛んに行われている。SOI (Semiconductor On Insulator / S)
Since the Silicon On Insulator) substrate is capable of complete element isolation, a semiconductor device manufactured using an SOI substrate is
There are various advantages such as latch-up free and noise free. From this point of view, the development of semiconductor devices using an SOI substrate has been actively conducted.
【０００３】[0003]
【従来の技術】図１３は，従来例を示す図であり，従来
のＳＯＩ基板における溝アイソレーションの例を示して
いる。2. Description of the Related Art FIG. 13 is a diagram showing a conventional example and shows an example of groove isolation in a conventional SOI substrate.
【０００４】同図において，４１はＳｉＯ2 膜，４２は
Ｓi 活性領域，４３は溝である。従来，ＳＯＩ基板にお
ける溝アイソレーションは，ＳｉＯ2 膜４１上に形成さ
れたＳi 層の表面からＳｉＯ2 膜４１に達する溝４３
ａ，４３ｂを掘ってＳi 活性領域４２ａ，４２ｂ，４２
ｃを相互に完全分離することにより行っていた。In the figure, 41 is a SiO 2 film, 42 is a Si active region, and 43 is a groove. Conventionally, the groove isolation in the SOI substrate, a groove 43 from the surface of the Si layer formed on the SiO 2 film 41 reaches the SiO 2 film 41
Si active regions 42a, 42b, 42 by digging a, 43b
This was done by completely separating c from each other.
【０００５】[0005]
【発明が解決しようとする課題】従来のＳＯＩ基板にお
ける溝アイソレーションでは，溝４３ａ，４３ｂとＳｉ
Ｏ2 膜４１とが交差する部分にストレスの集中が起こ
り，欠陥が生じていた。この欠陥は，Ｓi 活性領域４２
ａ，４２ｂ，４２ｃ中を斜め上方に伝播し，表面の素子
形成領域にまで達する（この様子を図中の×印で示
す）。その結果，形成された素子は，リークを起こしや
すく，動作が不安定になったり，消費電力が増大する，
という問題があった。In the conventional trench isolation in the SOI substrate, the trenches 43a and 43b and the Si are not formed.
Stress was concentrated at the intersection with the O 2 film 41, resulting in defects. This defect is caused by the Si active region 42
The light propagates obliquely upward in a, 42b, and 42c and reaches the element formation region on the surface (this state is indicated by a mark x in the figure). As a result, the formed element easily leaks, the operation becomes unstable, and the power consumption increases.
There was a problem.
【０００６】この問題点を解決するために，溝４３ａ，
４３ｂとＳｉＯ2 膜４１とが交差する部分で発生した欠
陥が到達しない位置に素子を形成することが考えられ
る。しかし，そのようにすると，Ｓi 活性領域４２ａ，
４２ｂ，４２ｃの面積が増大し，集積度が低下する，と
いう問題が生じる。In order to solve this problem, the grooves 43a,
It is conceivable to form the element at a position where the defect generated at the intersection of 43b and the SiO 2 film 41 does not reach. However, by doing so, the Si active region 42a,
There is a problem that the areas of 42b and 42c increase and the integration degree decreases.
【０００７】本発明は，上記の問題点を解決して，欠陥
の発生を防止，または発生した欠陥が素子形成領域に到
達するのを防止して，歩留まりの向上を図ると共に高集
積化を実現する半導体装置，特にＳＯＩ基板を用い，溝
アイソレーションを施した半導体装置を提供することを
目的とする。The present invention solves the above problems and prevents the occurrence of defects, or prevents the generated defects from reaching the element formation region, thereby improving the yield and achieving high integration. It is an object of the present invention to provide a semiconductor device having a groove isolation using a semiconductor device, especially an SOI substrate.
【０００８】[0008]
【課題を解決するための手段】図２は，本発明が対象と
する溝アイソレーションを示す図であり，図（ａ）はＵ
字型アイソレーションの例を示しており，図（ｂ）はＶ
字型アイソレーションの例を示している。FIG. 2 is a view showing groove isolation targeted by the present invention, and FIG.
An example of character-shaped isolation is shown, and FIG.
An example of character-shaped isolation is shown.
【０００９】図（ａ）に示すＵ字型溝は，ＲＩＥなどの
異方性エッチングによって形成される。図（ｂ）に示す
Ｖ字型溝は，結晶方向に依存する選択エッチングによっ
て形成される。例えば，（１００）基板を，ＫＯＨ＋Ｈ
2 Ｏ＋ＩＰＡ（イソプロピルアルコール）溶液でエッチ
ングすると，＜１１１＞方向にのみ選択的にエッチング
が進行するので，Ｖ字型溝を形成することができる。The U-shaped groove shown in FIG. 1A is formed by anisotropic etching such as RIE. The V-shaped groove shown in FIG. 6B is formed by selective etching depending on the crystal direction. For example, (100) substrate, KOH + H
When etching is performed with a 2 O + IPA (isopropyl alcohol) solution, the V-shaped groove can be formed because the etching selectively progresses only in the <111> direction.
【００１０】図１は，本発明の基本構成を示す図であ
る。図中，１は絶縁膜層，２は半導体活性領域，３は溝
である。以下，タイプ別に本発明の基本構成を説明す
る。FIG. 1 is a diagram showing the basic configuration of the present invention. In the figure, 1 is an insulating film layer, 2 is a semiconductor active region, and 3 is a groove. The basic configuration of the present invention will be described below for each type.
【００１１】（１）タイプ１［図１（ａ）］ これは，絶縁膜層１およびその上に形成された半導体層
から成るＳＯＩ基板を用い，半導体層に，絶縁膜層１に
到達しない位置まで溝３ａ，３ｂを形成して，素子が形
成される半導体活性領域２ａ，２ｂ，２ｃを相互に分離
するものであり，溝３ａ，３ｂは，絶縁膜層１に到達し
ない位置まで形成し，溝３ａ，３ｂの下部に，絶縁膜層
１にまで到達する高濃度不純物拡散層４ａ，４ｂを形成
する。(1) Type 1 [FIG. 1 (a)] This is an SOI substrate composed of an insulating film layer 1 and a semiconductor layer formed on the SOI substrate. Trenches 3a, 3b are formed to separate the semiconductor active regions 2a, 2b, 2c in which elements are formed from each other. The trenches 3a, 3b are formed up to a position not reaching the insulating film layer 1, High-concentration impurity diffusion layers 4a and 4b reaching the insulating film layer 1 are formed below the trenches 3a and 3b.
【００１２】（２）タイプ２［図１（ｂ）］ これは，絶縁膜層１およびその上に形成された半導体層
から成るＳＯＩ基板を用い，半導体層に，絶縁膜層１に
到達しない位置まで溝３ａ，３ｂを形成して，素子が形
成される半導体活性領域２ａ，２ｂ，２ｃを相互に分離
するものであり，溝３ａ，３ｂは，絶縁膜層１に到達し
ない位置まで形成し，溝３ａ，３ｂの側壁および下部
に，絶縁膜層１にまで到達する酸化膜層５ａ，５ｂを形
成する。(2) Type 2 [FIG. 1 (b)] This is an SOI substrate composed of an insulating film layer 1 and a semiconductor layer formed on the insulating film layer 1, and the semiconductor layer is at a position not reaching the insulating film layer 1. Trenches 3a, 3b are formed to separate the semiconductor active regions 2a, 2b, 2c in which elements are formed from each other. The trenches 3a, 3b are formed up to a position not reaching the insulating film layer 1, Oxide film layers 5a and 5b reaching the insulating film layer 1 are formed on the sidewalls and lower portions of the trenches 3a and 3b.
【００１３】（３）タイプ３［図１（ｃ）］ これは，絶縁膜層１およびその上に形成された半導体層
から成るＳＯＩ基板を用い，半導体層に，絶縁膜層１に
到達しない位置まで溝３ａ，３ｂを形成して，素子が形
成される半導体活性領域２ａ，２ｂ，２ｃを相互に分離
するものであり，溝３ａ，３ｂは，絶縁膜層１に到達し
ない位置まで形成し，溝３ａ，３ｂの下部に，絶縁膜層
１にまで到達する第２の溝６ａ，６ｂを形成する。(3) Type 3 [FIG. 1 (c)] This is an SOI substrate composed of an insulating film layer 1 and a semiconductor layer formed on the insulating film layer 1, and a position where the insulating layer 1 does not reach the semiconductor layer. Trenches 3a, 3b are formed to separate the semiconductor active regions 2a, 2b, 2c in which elements are formed from each other. The trenches 3a, 3b are formed up to a position not reaching the insulating film layer 1, Second trenches 6a and 6b reaching the insulating film layer 1 are formed below the trenches 3a and 3b.
【００１４】[0014]
【作用】（１）タイプ１［図１（ａ）］ 溝３ａ，３ｂは，絶縁膜層１に到達しない位置までしか
形成していないから，欠陥が発生することは無い。そし
て，溝３ａ，３ｂの下部に形成された，絶縁膜層１にま
で到達する高濃度不純物拡散層４ａ，４ｂによって半導
体活性領域２ａ，２ｂ，２ｃ相互の完全分離が達成され
る。(1) Type 1 [FIG. 1 (a)] Since the grooves 3a and 3b are formed only up to the position where they do not reach the insulating film layer 1, no defect occurs. Then, the semiconductor active regions 2a, 2b, 2c are completely separated from each other by the high-concentration impurity diffusion layers 4a, 4b formed below the trenches 3a, 3b and reaching the insulating film layer 1.
【００１５】（２）タイプ２［図１（ｂ）］ 溝３ａ，３ｂは，絶縁膜層１に到達しない位置までしか
形成していないから，欠陥が発生することは無い。そし
て，溝３ａ，３ｂの側壁および下部に形成された，絶縁
膜層１にまで到達する酸化膜層５ａ，５ｂによって半導
体活性領域２ａ，２ｂ，２ｃ相互の完全分離が達成され
る。(2) Type 2 [FIG. 1 (b)] Since the grooves 3a and 3b are formed only up to the position where they do not reach the insulating film layer 1, no defect occurs. Then, the oxide film layers 5a and 5b formed on the sidewalls and lower portions of the trenches 3a and 3b and reaching the insulating film layer 1 achieve complete isolation between the semiconductor active regions 2a, 2b and 2c.
【００１６】（３）タイプ３［図１（ｃ）］ このタイプでは，溝３ａ，３ｂの下部に絶縁膜層１にま
で到達する第２の溝６ａ，６ｂが形成されているので，
第２の溝６ａ，６ｂと絶縁膜層１とが交差する点で欠陥
が発生するが，この欠陥は，図中×印で示すように伝播
して溝３ａ，３ｂの下部で止まる。したがって，半導体
活性領域２ａ，２ｂ，２ｃ中の素子形成領域に影響が及
ぶことは無い。(3) Type 3 [FIG. 1 (c)] In this type, since the second grooves 6a and 6b reaching the insulating film layer 1 are formed below the grooves 3a and 3b,
A defect occurs at a point where the second trenches 6a and 6b intersect with the insulating film layer 1, but this defect propagates as shown by a mark X in the figure and stops at the bottom of the trenches 3a and 3b. Therefore, the element formation regions in the semiconductor active regions 2a, 2b, 2c are not affected.
【００１７】溝３ａ，３ｂの側下部に形成された，絶縁
膜層１にまで到達する第２の溝６ａ，６ｂによって半導
体活性領域２ａ，２ｂ，２ｃ相互の完全分離が達成され
る。Complete isolation of the semiconductor active regions 2a, 2b, 2c from each other is achieved by the second trenches 6a, 6b formed under the sides of the trenches 3a, 3b and reaching the insulating film layer 1.
【００１８】[0018]
【実施例】以下に示す実施例においては，ＳｉＯ2 膜１
１層上にシリコン層を形成したＳＯＩ基板を用い，シリ
コン層をＳｉＯ2 膜１１層に到達しない位置まで掘って
溝１３ａ，１３ｂを形成したものを対象にする。EXAMPLES In the examples shown below, the SiO 2 film 1 was used.
An SOI substrate in which a silicon layer is formed on one layer is used, and the silicon layer is dug up to a position where it does not reach the SiO 2 film 11 to form grooves 13a and 13b.
【００１９】本発明は，以上のものに限らず，絶縁膜層
上に半導体層を形成したＳＯＩ基板一般に適用すること
ができる。 （実施例１，図３）溝１３ａ，１３ｂの下部にｐ型Ｓｉ
活性領域１２ａ，１２ｂ，１２ｃと同じ導電型で，Ｓｉ
Ｏ2 膜層１１にまで到達するｐ+ 型高濃度不純物拡散層
１４ａ，１４ｂを形成したものである。The present invention is not limited to the above, but can be applied to an SOI substrate in which a semiconductor layer is formed on an insulating film layer in general. (Example 1, FIG. 3) P-type Si is formed below the grooves 13a and 13b.
The same conductivity type as the active regions 12a, 12b, 12c, Si
The p + type high-concentration impurity diffusion layers 14a and 14b reaching the O 2 film layer 11 are formed.
【００２０】（実施例２，図４）溝１３ａの下部に，ｐ
型Ｓｉ活性領域１２ｂと同じ導電型でＳｉＯ2 膜１１に
まで到達するｐ+ 型高濃度不純物拡散層１５ａおよびｎ
型Ｓｉ活性領域１２ａと同じ導電型でＳｉＯ2 膜層１１
にまで到達するｎ+ 型高濃度不純物拡散層１６ａを形成
し，溝１３ｂの下部にｐ型Ｓｉ活性領域１２ｂと同じ導
電型でＳｉＯ2 膜層１１にまで到達するｐ+ 型高濃度不
純物拡散層１５ｂおよびｎ型Ｓｉ活性領域１２ｃと同じ
導電型でＳｉＯ2 膜層１１にまで到達するｎ+ 型高濃度
不純物拡散層１６ｂを形成したものである。(Example 2, FIG. 4) In the lower part of the groove 13a, p
P + high-concentration impurity diffusion layers 15a and n reaching the SiO 2 film 11 with the same conductivity type as that of the Si-type active region 12b.
Type Si active region 12a having the same conductivity type as the SiO 2 film layer 11
N + -type high-concentration impurity diffusion layer 16a reaching the temperature is formed, and a p + -type high-concentration impurity diffusion layer reaching the SiO 2 film layer 11 with the same conductivity type as the p-type Si active region 12b is formed under the groove 13b. The n + -type high-concentration impurity diffusion layer 16b reaching the SiO 2 film layer 11 is formed with the same conductivity type as that of 15b and the n-type Si active region 12c.
【００２１】（実施例３，図５）溝１３ａ，１３ｂの下
部のｐ型Ｓｉ活性領域１２ａ，１２ｂ，１２ｃ側にｐ型
Ｓｉ活性領域１２ａ，１２ｂ，１２ｃと同じ導電型で，
ＳｉＯ2 膜層１１にまで到達するｐ+ 型高濃度不純物拡
散層１７ａ，１７ｂ，１７ｃ，１７ｄを形成し，ｐ+ 型
高濃度不純物拡散層１７ａ，１７ｂの間に反対導電型の
ｎ+ 型高濃度不純物拡散層１８ａを形成し，ｐ+ 型高濃
度不純物拡散層１７ｃ，１７ｄの間に反対導電型のｎ+
型高濃度不純物拡散層１８ｂを形成したものである。(Embodiment 3, FIG. 5) The same conductivity type as the p-type Si active regions 12a, 12b, 12c is provided on the p-type Si active regions 12a, 12b, 12c side below the grooves 13a, 13b.
P + -type high concentration impurity diffusion layers 17a reaching the SiO 2 film layer 11, 17b, 17c, 17d is formed, the p + -type high concentration impurity diffusion layers 17a, 17b opposite conductivity type of the n + -type high during A high-concentration impurity diffusion layer 18a is formed, and n + of the opposite conductivity type is formed between the p + -type high-concentration impurity diffusion layers 17c and 17d.
The high-concentration impurity diffusion layer 18b is formed.
【００２２】（実施例４，図６）溝１３ａ，１３ｂの側
壁および下部に，ＳｉＯ2 膜層１１にまで到達するＳｉ
Ｏ2 膜層１９ａ，１９ｂを形成したものである。(Embodiment 4, FIG. 6) Si reaching the SiO 2 film layer 11 on the side walls and lower portions of the grooves 13a and 13b.
The O 2 film layers 19a and 19b are formed.
【００２３】（実施例５，図７）溝１３ａ，１３ｂの下
部のｐ型Ｓｉ活性領域１２ａ，１２ｂ，１２ｃ側にｐ型
Ｓｉ活性領域１２ａ，１２ｂ，１２ｃと同じ導電型で，
ＳｉＯ2 膜層１１にまで到達するｐ+ 型高濃度不純物拡
散層２０ａ，２０ｂ，２０ｃ，２０ｄを形成し，ｐ+ 型
高濃度不純物拡散層２０ａ，２０ｂの間にＳｉＯ2 膜層
２１ａを形成し，ｐ+ 型高濃度不純物拡散層２０ｃ，２
０ｄの間にＳｉＯ2 膜層２１ｂを形成したものである。(Embodiment 5, FIG. 7) The same conductivity type as the p-type Si active regions 12a, 12b, 12c is provided on the p-type Si active regions 12a, 12b, 12c side below the grooves 13a, 13b.
The p + type high-concentration impurity diffusion layers 20a, 20b, 20c, 20d reaching the SiO 2 film layer 11 are formed, and the SiO 2 film layer 21a is formed between the p + -type high concentration impurity diffusion layers 20a, 20b. , P + -type high-concentration impurity diffusion layers 20c, 2
The SiO 2 film layer 21b is formed between 0d.
【００２４】（実施例６，図８）溝１３ａの下部に，ｐ
型Ｓｉ活性領域１２ｂと同じ導電型でＳｉＯ2 膜１１に
まで到達するｐ+ 型高濃度不純物拡散層２２ａおよびｎ
型Ｓｉ活性領域１２ａと同じ導電型でＳｉＯ2 膜層１１
にまで到達するｎ+ 型高濃度不純物拡散層２３ａを形成
し，溝１３ｂの下部にｐ型Ｓｉ活性領域１２ｂと同じ導
電型でＳｉＯ2 膜層１１にまで到達するｐ+ 型高濃度不
純物拡散層２２ｂおよびｎ型Ｓｉ活性領域１２ｃと同じ
導電型でＳｉＯ2 膜層１１にまで到達するｎ+ 型高濃度
不純物拡散層２３ｂを形成し，ｐ+型高濃度不純物拡散
層２２ａおよびｎ+ 型高濃度不純物拡散層２３ａの間に
ＳｉＯ2 膜層２４ａを形成し，ｐ+ 型高濃度不純物拡散
層２２ｂおよびｎ+ 型高濃度不純物拡散層２３ｂの間に
ＳｉＯ2 膜層２４ｂを形成したものである。(Embodiment 6, FIG. 8) In the lower part of the groove 13a, p
P + -type high-concentration impurity diffusion layers 22a and n reaching the SiO 2 film 11 with the same conductivity type as that of the Si-type active region 12b.
Type Si active region 12a having the same conductivity type as the SiO 2 film layer 11
Until forming a n + -type high concentration impurity diffusion layers 23a to reach, p + -type high concentration impurity diffusion layer to reach the SiO 2 film layer 11 at the same conductivity type as p-type Si active region 12b on the bottom of the groove 13b in the same conductivity type as 22b and n-type Si active region 12c to a SiO 2 film layer 11 to form the n + -type high concentration impurity diffusion layer 23b to reach, p + -type high concentration impurity diffusion layers 22a and n + -type high concentration the SiO 2 layer 24a is formed between the impurity diffusion layers 23a, it is obtained by forming a SiO 2 film layer 24b between the p + -type high concentration impurity diffusion layer 22b and the n + -type high concentration impurity diffusion layers 23b.
【００２５】（実施例７，図９）溝１３ａ，１３ｂの下
部に，ＳｉＯ2 膜層１１にまで到達する第２の溝２５
ａ，２５ｂを形成したものである。(Embodiment 7, FIG. 9) A second groove 25 reaching the SiO 2 film layer 11 is formed below the grooves 13a and 13b.
a and 25b are formed.
【００２６】（実施例８，図１０）溝１３ａ，１３ｂの
下部にＳｉＯ2 膜層１１にまで到達する第２の溝２７
ａ，２７ｂを掘った後，ｐ型Ｓｉ活性領域１２ａ，１２
ｂ，１２ｃと同じ導電型で，ＳｉＯ2 膜層１１にまで到
達するｐ+ 型高濃度不純物拡散層２６ａ，２６ｂ，２６
ｃ，２６ｄを形成したものである。(Embodiment 8; FIG. 10) A second groove 27 reaching the SiO 2 film layer 11 below the grooves 13a and 13b.
After digging a and 27b, p-type Si active regions 12a and 12
p + -type high-concentration impurity diffusion layers 26a, 26b, 26 which have the same conductivity type as b, 12c and reach the SiO 2 film layer 11.
c and 26d are formed.
【００２７】（実施例９，図１１）溝１３ａ，１３ｂの
下部にＳｉＯ2 膜層１１にまで到達する第２の溝３０
ａ，３０ｂを掘った後，溝１３ａの下部に，ｐ型Ｓｉ活
性領域１２ｂと同じ導電型でＳｉＯ2 膜１１にまで到達
するｐ+ 型高濃度不純物拡散層２８ａおよびｎ型Ｓｉ活
性領域１２ａと同じ導電型でＳｉＯ2 膜層１１にまで到
達するｎ+ 型高濃度不純物拡散層２９ａを形成し，溝１
３ｂの下部にｐ型Ｓｉ活性領域１２ｂと同じ導電型でＳ
ｉＯ2 膜層１１にまで到達するｐ+ 型高濃度不純物拡散
層２８ｂおよびｎ型Ｓｉ活性領域１２ｃと同じ導電型で
ＳｉＯ2 膜層１１にまで到達するｎ+ 型高濃度不純物拡
散層２９ｂを形成したものである。(Example 9; FIG. 11) A second groove 30 reaching the SiO 2 film layer 11 under the grooves 13a and 13b.
After digging a and 30b, a p + -type high-concentration impurity diffusion layer 28a and an n-type Si active region 12a which reach the SiO 2 film 11 with the same conductivity type as the p-type Si active region 12b are formed below the groove 13a. An n + -type high-concentration impurity diffusion layer 29a reaching the SiO 2 film layer 11 with the same conductivity type is formed, and the groove 1
3b has the same conductivity type as that of the p-type Si active region 12b at the bottom thereof.
An n + -type high-concentration impurity diffusion layer 29b reaching the SiO 2 film layer 11 is formed with the same conductivity type as the p + -type high-concentration impurity diffusion layer 28b reaching the iO 2 film layer 11 and the n-type Si active region 12c. It was done.
【００２８】（実施例１０，図１２）溝１３ａ，１３ｂ
の下部にＳｉＯ2 膜層１１にまで到達する第２の溝３２
ａ，３２ｂを掘った後，溝１３ａ，１３ｂおよび第２の
溝３２ａ，３２ｂの側壁および下部に，ＳｉＯ2 膜層１
１にまで到達するＳｉＯ2 膜層３１ａ，３１ｂ，３１
ｃ，３１ｄを形成したものである。(Embodiment 10, FIG. 12) Grooves 13a, 13b
The second groove 32 reaching the SiO 2 film layer 11 at the bottom of the
After digging a and 32b, the SiO 2 film layer 1 is formed on the side walls and lower parts of the grooves 13a and 13b and the second grooves 32a and 32b.
SiO 2 film layers 31a, 31b, 31 reaching 1
c and 31d are formed.
【００２９】[0029]
【発明の効果】本発明によれば，ＳＯＩ基板を用い，溝
アイソレーションを施した半導体装置において，欠陥の
発生を防止，または発生した欠陥が素子形成領域に到達
するのを防止して，歩留まりの向上を図ると共に高集積
化を実現することができる。According to the present invention, in a semiconductor device using an SOI substrate and having groove isolation, the occurrence of defects is prevented, or the generated defects are prevented from reaching the element formation region, and the yield is improved. It is possible to achieve higher integration and higher integration.
【図１】本発明の基本構成を示す図である。FIG. 1 is a diagram showing a basic configuration of the present invention.
【図２】本発明が対象とする溝アイソレーションを示す
図である。FIG. 2 is a diagram showing groove isolation targeted by the present invention.
【図３】実施例１を示す図である。FIG. 3 is a diagram showing Example 1.
【図４】実施例２を示す図である。FIG. 4 is a diagram showing a second embodiment.
【図５】実施例３を示す図である。FIG. 5 is a diagram showing a third embodiment.
【図６】実施例４を示す図である。FIG. 6 is a diagram showing a fourth embodiment.
【図７】実施例５を示す図である。FIG. 7 is a diagram showing a fifth embodiment.
【図８】実施例６を示す図である。FIG. 8 is a diagram showing a sixth embodiment.
【図９】実施例７を示す図である。FIG. 9 is a diagram showing Example 7.
【図１０】実施例８を示す図である。FIG. 10 is a diagram showing an eighth embodiment.
【図１１】実施例９を示す図である。FIG. 11 is a diagram showing Example 9.
【図１２】実施例１０を示す図である。FIG. 12 is a diagram showing Example 10.
【図１３】従来例を示す図である。FIG. 13 is a diagram showing a conventional example.
１ 絶縁膜層 ２ 半導体活性領域 ３ 溝 ４ 高濃度不純物拡散層 ５ 酸化膜層 ６ 第２の溝 1 Insulating Film Layer 2 Semiconductor Active Region 3 Groove 4 High Concentration Impurity Diffusion Layer 5 Oxide Film Layer 6 Second Groove
Claims (3)
体層から成るＳＯＩ基板を用い，半導体層に溝を形成し
て，素子が形成される半導体活性領域を相互に分離する
半導体装置であって， 溝は，絶縁膜層に到達しない位置まで形成し， 該溝の下部に，絶縁膜層にまで到達する高濃度不純物拡
散層を形成したことを特徴とする半導体装置。1. A semiconductor device in which an SOI substrate including an insulating film layer and a semiconductor layer formed thereon is used, a groove is formed in the semiconductor layer, and semiconductor active regions in which elements are formed are separated from each other. The semiconductor device is characterized in that the groove is formed up to a position not reaching the insulating film layer, and a high-concentration impurity diffusion layer reaching the insulating film layer is formed under the groove.
体層から成るＳＯＩ基板を用い，半導体層に溝を形成し
て，素子が形成される半導体活性領域を相互に分離する
半導体装置であって， 溝は，絶縁膜層に到達しない位置まで形成し， 該溝の下部に，絶縁膜層にまで到達する酸化膜層を形成
したことを特徴とする半導体装置。2. A semiconductor device in which an SOI substrate including an insulating film layer and a semiconductor layer formed thereon is used, a groove is formed in the semiconductor layer, and semiconductor active regions in which elements are formed are separated from each other. The semiconductor device is characterized in that the groove is formed to a position not reaching the insulating film layer, and an oxide film layer reaching the insulating film layer is formed below the groove.
体層から成るＳＯＩ基板を用い，半導体層に溝を形成し
て，素子が形成される半導体活性領域を相互に分離する
半導体装置であって， 絶縁膜層に到達しない第１の溝を形成し， 該第１の溝の下部に，絶縁膜層にまで到達する第２の溝
を形成したことを特徴とする半導体装置。3. A semiconductor device in which an SOI substrate including an insulating film layer and a semiconductor layer formed thereon is used, a groove is formed in the semiconductor layer, and semiconductor active regions in which elements are formed are separated from each other. A semiconductor device is characterized in that a first groove that does not reach the insulating film layer is formed, and a second groove that reaches the insulating film layer is formed below the first groove.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24752791A JPH0590394A (en) | 1991-09-26 | 1991-09-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24752791A JPH0590394A (en) | 1991-09-26 | 1991-09-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0590394A true JPH0590394A (en) | 1993-04-09 |
Family
ID=17164826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24752791A Pending JPH0590394A (en) | 1991-09-26 | 1991-09-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0590394A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656537A (en) * | 1994-11-28 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having SOI structure |
| KR100318463B1 (en) * | 1998-10-28 | 2002-02-19 | 박종섭 | Method for fabricating body contact SOI device |
| KR100505402B1 (en) * | 1999-06-22 | 2005-08-04 | 주식회사 하이닉스반도체 | Method of manufacturing body contacted SOI device |
| KR100505403B1 (en) * | 1999-06-22 | 2005-08-05 | 주식회사 하이닉스반도체 | Method of manufacturing body contacted SOI device |
| JP2007220718A (en) * | 2006-02-14 | 2007-08-30 | Toyota Motor Corp | Semiconductor substrate, method of manufacturing same and semiconductor device |
| JP2010239044A (en) * | 2009-03-31 | 2010-10-21 | Sanken Electric Co Ltd | Integrated semiconductor device and method for manufacturing method the same |
-
1991
- 1991-09-26 JP JP24752791A patent/JPH0590394A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5656537A (en) * | 1994-11-28 | 1997-08-12 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a semiconductor device having SOI structure |
| KR100318463B1 (en) * | 1998-10-28 | 2002-02-19 | 박종섭 | Method for fabricating body contact SOI device |
| KR100505402B1 (en) * | 1999-06-22 | 2005-08-04 | 주식회사 하이닉스반도체 | Method of manufacturing body contacted SOI device |
| KR100505403B1 (en) * | 1999-06-22 | 2005-08-05 | 주식회사 하이닉스반도체 | Method of manufacturing body contacted SOI device |
| JP2007220718A (en) * | 2006-02-14 | 2007-08-30 | Toyota Motor Corp | Semiconductor substrate, method of manufacturing same and semiconductor device |
| JP2010239044A (en) * | 2009-03-31 | 2010-10-21 | Sanken Electric Co Ltd | Integrated semiconductor device and method for manufacturing method the same |
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