JPS6089916A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS6089916A JPS6089916A JP19854583A JP19854583A JPS6089916A JP S6089916 A JPS6089916 A JP S6089916A JP 19854583 A JP19854583 A JP 19854583A JP 19854583 A JP19854583 A JP 19854583A JP S6089916 A JPS6089916 A JP S6089916A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- type
- semiconductor device
- oxygen
- atmosphere
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02373—Group 14 semiconducting materials
- H01L21/02381—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
Abstract
Description
【発明の詳細な説明】 産業上の利用分野 本発明は半導体装置の製造方法に関する。[Detailed description of the invention] Industrial applications The present invention relates to a method for manufacturing a semiconductor device.
従来例の構成とその問題点
一般にＮ型別基板は、０ＭＯ５等に多く用いられ２べ一
′ｊ
ている。しかし通常のａＺ法による基板は結晶引き上は
時に、原料融液の対流が原因となり、ウェーハ面内で同
心円状に不純物の濃度ムラが生じる。Conventional Structures and Their Problems In general, N-type separate substrates are often used in 0MO5 and the like, and two substrates are used. However, in the case of a substrate formed by the usual aZ method, crystal pulling is sometimes caused by convection of the raw material melt, resulting in concentric impurity concentration unevenness within the wafer surface.
このバラつきは、Ｓ、Ｒ法によると±８係程度ある。According to the S and R methods, this variation is about a factor of ±8.
しかし、この程度の不純物濃度のバラツキであっても、
畠結晶品質に敏感な固体撮像装置においては、固定パタ
ーン雑音として観測され、画質劣化の一要因となってい
る。However, even with this level of variation in impurity concentration,
Hatake:In solid-state imaging devices that are sensitive to crystal quality, this is observed as fixed pattern noise and is a factor in deteriorating image quality.
この解決には、基板面内に周期的不純物分布を有しない
エビウェーハが最適である。しかし通常のＮ／Ｎ″−エ
ピウェーハをＣＭＯＳプロセスに適用すると、表面に欠
陥が生じ、デバイスの性能低下を引き起こす。特に固体
撮像装置においては、上記欠陥は白傷となり、歩留りを
著しく低下させる原因となる。この白傷の原因は、エビ
基板中の過飽和酸素による。この対策としては、エビ基
板にいわゆるイントリンシノクゲノタリ／グ（Ｉ 、
Ｇ、）処理を施し、基板の酸素濃度を低下さ−ぎれば良
いことがわかっている。To solve this problem, shrimp wafers that do not have periodic impurity distribution within the substrate plane are optimal. However, when a normal N/N''-epi wafer is applied to a CMOS process, defects occur on the surface and cause a decline in device performance.Particularly in solid-state imaging devices, the above-mentioned defects become white scratches and cause a significant decrease in yield. The cause of these white scratches is supersaturated oxygen in the shrimp substrate.As a countermeasure to this problem, the shrimp substrate is coated with so-called intrinsinochenotarii/g (I,
It has been found that it is sufficient to reduce the oxygen concentration of the substrate by performing a treatment (G.).
しかし、現状では、ａＺ−Ｎ型基板において、不３１・
−−・
鈍物濃度が高いものは、特にｓｂ ドープ基板では、十
分な１．Ｇ、が効きにくいという実験結果が得られてい
る。つ捷り、１．Ｇ、が効率良く効く、すなわち高密度
のバルク欠陥の発生が可能なのは、比抵抗が１〜数１０
０ｃｍ 、リンドープのものである。However, at present, in the aZ-N type substrate,
--- A substrate with a high obtuse concentration, especially an sb-doped substrate, has a sufficient 1. Experimental results have shown that G is less effective. Threading, 1. G is effective, that is, it is possible to generate a high density of bulk defects when the resistivity is between 1 and several tens of tens.
0 cm, phosphorus-doped.
そのため、高温処理によっても品質の劣化しないＮ／Ｎ
エピウェーハは実現できていない。Therefore, the quality does not deteriorate even with high temperature processing.N/N
Epiwafers have not been realized.
発明の目的
本発明は上記欠点を解消するためになされたもので、基
板に高濃度の不純物層を有し、なおかつ高温処理による
エピタキシャル層の品質劣化をまねくことのない高品質
エピタキシャルウェーハを得ることのできる半導体装置
の製造方法を提供するものである。Purpose of the Invention The present invention has been made to eliminate the above-mentioned drawbacks, and it is an object of the present invention to obtain a high-quality epitaxial wafer that has a highly concentrated impurity layer on the substrate and that does not cause quality deterioration of the epitaxial layer due to high-temperature treatment. The present invention provides a method for manufacturing a semiconductor device that enables the following.
発明の構成
本発明は比抵抗１〜数１０ＱａｎのＣＺ、Ｎ型Ｓｉ基板
の表面から、酸素を外方拡散させる熱処理工程と、基板
内にプレシピテートの核を発生させる熱処理工程と、前
記プレシピテートを成長させる熱処理工程と、前記基板
の一方あるいは両面の酸化物等を除去する工程と、前記
基板にＮ型高濃度不純物層を形成する工程と、その」二
にＮ型エピタキシャル層を形成する工程をそなえた半導
体装置の製造方法である。Structure of the Invention The present invention comprises a heat treatment process for outwardly diffusing oxygen from the surface of a CZ or N-type Si substrate with a specific resistance of 1 to several tens of Qan, a heat treatment process for generating precipitate nuclei within the substrate, and a heat treatment process for growing the precipitate. a step of removing oxides, etc. from one or both sides of the substrate, a step of forming an N-type high concentration impurity layer on the substrate, and a second step of forming an N-type epitaxial layer. This is a method for manufacturing a semiconductor device.
実施例の説明
以下図面を参照しながら本発明の詳細な説明する。第１
図は本発明によって作られた半導体装置の断面模式図で
ある。１１は出発材料であるＮ型ＣＺ基板、１２は後述
の熱処理により形成した無欠陥領域、１３は前記熱処理
により形成した高密度欠陥領域、１４はＮ型高濃度不純
物領域、１６はＮ型エピタキシャル層である。DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to the drawings. 1st
The figure is a schematic cross-sectional view of a semiconductor device manufactured according to the present invention. 11 is an N-type CZ substrate which is a starting material, 12 is a defect-free region formed by the heat treatment described below, 13 is a high-density defect region formed by the heat treatment, 14 is an N-type high concentration impurity region, and 16 is an N-type epitaxial layer. It is.
第２図は、本発明の一実施例の工程図である。FIG. 2 is a process diagram of an embodiment of the present invention.
まず第２図（ａ）に示す比抵抗８〜１２ΩｍのＣＺ 、
Ｎ型Ｓ１基板１１を用い、基板１１中に含まれる酸素を
外方拡散させる目的でアルゴン雰囲気中、１１００’０
．４時間の熱処理を行う。次にバルク内プレシピテート
発生核を形成させる目的で、酸素雰囲気中、７００’Ｃ
，１６時間の熱処理を行う。First, CZ with a specific resistance of 8 to 12 Ωm shown in Fig. 2(a),
Using an N-type S1 substrate 11, the temperature was set at 1100'0 in an argon atmosphere for the purpose of outwardly diffusing oxygen contained in the substrate 11.
．． Heat treatment is performed for 4 hours. Next, in order to form precipitate generation nuclei in the bulk, the temperature was set at 70'C in an oxygen atmosphere.
, heat treatment for 16 hours.
次に前記プし・シピテートを成長させる目的で、酸５・
・ ：・
素雰囲気中、１０００’Ｃ，ｅ時間の熱処理を行う。Next, for the purpose of growing the above-mentioned polycypitate, acid 5.
・ :・ Heat treatment is performed at 1000'C for e hours in an elementary atmosphere.
その時の断面は、第２図（ｂ）の様になる。次に表面の
ＳｉＯ２を除去し、第２図（Ｃ）の様にＮ型高濃度不純
物層１４を、イオン注入により形成する。そしてその上
に活性層となるＮ型エピタキシャル層１６を形成する。The cross section at that time will be as shown in FIG. 2(b). Next, the SiO2 on the surface is removed, and an N-type high concentration impurity layer 14 is formed by ion implantation as shown in FIG. 2(C). Then, an N-type epitaxial layer 16 that becomes an active layer is formed thereon.
その結果、第２図（ｄ）に示すＮ／Ｎ ／Ｎ断面構造と
なるが、実効的にはＮ／Ｎ＋エピウェーハと同一となる
。As a result, the N/N/N cross-sectional structure shown in FIG. 2(d) is obtained, which is effectively the same as the N/N+ epiwafer.
エピタキシャル層１６下に、高濃度不純物層１４を有し
ているので、Ｎ／Ｎエピウェーハに比べてより大きなゲ
ッタリング効果が期待できる。その高濃度不純物層１４
の不純物濃度は、デバイスの特性。Since the highly concentrated impurity layer 14 is provided below the epitaxial layer 16, a greater gettering effect can be expected compared to an N/N epitaxial wafer. The high concentration impurity layer 14
The impurity concentration is a characteristic of the device.
エピタキシャル膜厚に合せて自由に制御できる。It can be freely controlled according to the epitaxial film thickness.
またこの構造より得られる効果として、活性層でアルエ
ピタキシャル層１６との間にポテンシャルバリヤができ
、バルクからの擬似信号混入のストッパとなる。Further, as an effect obtained from this structure, a potential barrier is formed between the active layer and the epitaxial layer 16, which serves as a stopper for the mixing of spurious signals from the bulk.
なお、Ｐ型基板に対しても本発明の方法は当然に実施で
きる。Incidentally, the method of the present invention can naturally be applied to a P-type substrate as well.
発明の効果
６７・−１・
以上のように本発明によれば、活性層の比抵抗の周期的
分布を除去し、エピタキシャル基板に含有する酸素の影
響を防止し、なおかつ、基板の高濃度不純物効果をも期
待でき、高品質の半導体装置を製造することができる。Effects of the Invention 67.-1. As described above, according to the present invention, the periodic distribution of resistivity in the active layer can be removed, the influence of oxygen contained in the epitaxial substrate can be prevented, and the high concentration impurity in the substrate can be prevented. Effects can also be expected, and high quality semiconductor devices can be manufactured.
第１図は、本発明によって製造された半導体装置の断面
模式図、第２図（ａ）〜（（ｉ）は、本発明の製造工程
断面図である。
１１・・・・・・ＣＺ、Ｎ型、Ｓｉ基板、１２・・・・
・・無欠陥領域、１３・・・・・・高密度欠陥領域、１
４・・・・・Ｎ型高濃度不純物層、１６・・・・・・Ｎ
型エピタキシャル層。FIG. 1 is a schematic cross-sectional view of a semiconductor device manufactured according to the present invention, and FIGS. 2(a) to (i) are cross-sectional views of the manufacturing process of the present invention. 11...CZ, N type, Si substrate, 12...
...Defect-free area, 13...High-density defect area, 1
4...N-type high concentration impurity layer, 16...N
type epitaxial layer.
Claims (1)
記基板に含捷れる酸素を外方拡散する工程と、希ガスま
たは酸化性ガス雰囲気中で熱処理し、プレシピテート発
生核を前記基板に形成する工程と、希ガスまたは酸化性
ガス雰囲気中で熱処理し、前記プレシピテート発生核を
成長させる工程と、前記−導電型の不純物を拡散して前
記基板裏面に高濃度不純物層を形成する工程と、前記基
板の表面に前記−導電型のエピタキシアル層を形成する
工程とを含むことを特徴とする半導体装置の製造方法。A step of heat-treating a semiconductor substrate of one conductivity type in a rare gas atmosphere to outwardly diffuse oxygen contained in the substrate, and a step of heat-treating a semiconductor substrate of one conductivity type in a rare gas or oxidizing gas atmosphere to form precipitate generation nuclei in the substrate. a step of heat-treating in a rare gas or oxidizing gas atmosphere to grow the precipitate generation nuclei; and a step of diffusing the - conductivity type impurity to form a highly concentrated impurity layer on the back surface of the substrate. A method for manufacturing a semiconductor device, comprising the step of forming the - conductivity type epitaxial layer on the surface of the substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19854583A JPS6089916A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP19854583A JPS6089916A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6089916A true JPS6089916A (en) | 1985-05-20 |
Family
ID=16392942
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP19854583A Pending JPS6089916A (en) | 1983-10-24 | 1983-10-24 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6089916A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163556A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Semiconductor device |
-
1983
- 1983-10-24 JP JP19854583A patent/JPS6089916A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH06163556A (en) * | 1992-11-26 | 1994-06-10 | Nec Corp | Semiconductor device |
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