JPS61135128A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS61135128A JPS61135128A JP25792284A JP25792284A JPS61135128A JP S61135128 A JPS61135128 A JP S61135128A JP 25792284 A JP25792284 A JP 25792284A JP 25792284 A JP25792284 A JP 25792284A JP S61135128 A JPS61135128 A JP S61135128A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- heat treatment
- film
- defects
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 14
- 238000004519 manufacturing process Methods 0.000 title claims description 9
- 238000010438 heat treatment Methods 0.000 claims abstract description 36
- 239000000758 substrate Substances 0.000 claims abstract description 21
- 238000000034 method Methods 0.000 claims abstract description 16
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 14
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims abstract description 5
- 230000007547 defect Effects 0.000 abstract description 21
- 235000012431 wafers Nutrition 0.000 abstract description 19
- 229910052760 oxygen Inorganic materials 0.000 abstract description 13
- 239000001301 oxygen Substances 0.000 abstract description 13
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 abstract description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 5
- 229910052710 silicon Inorganic materials 0.000 abstract description 5
- 239000010703 silicon Substances 0.000 abstract description 5
- 239000012298 atmosphere Substances 0.000 abstract description 3
- 238000000151 deposition Methods 0.000 abstract description 3
- 239000012299 nitrogen atmosphere Substances 0.000 abstract description 3
- 238000001312 dry etching Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract description 2
- 229920005591 polysilicon Polymers 0.000 abstract 3
- 238000000746 purification Methods 0.000 abstract 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 abstract 1
- 230000003647 oxidation Effects 0.000 abstract 1
- 238000007254 oxidation reaction Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 7
- 230000003749 cleanliness Effects 0.000 description 5
- 238000011109 contamination Methods 0.000 description 5
- 239000013078 crystal Substances 0.000 description 5
- 239000000047 product Substances 0.000 description 5
- 230000006866 deterioration Effects 0.000 description 4
- 230000000903 blocking effect Effects 0.000 description 3
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000001556 precipitation Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 229910001385 heavy metal Inorganic materials 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000155 melt Substances 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 239000002244 precipitate Substances 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は半導体装置の製造方法に関し、特に半導体基板
の結晶欠陥を低減する方法に係る。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for reducing crystal defects in a semiconductor substrate.
周知の如く、例えばシリコン基板(ウェハ)表面に形成
された各種の機能素子が正常に動作するためには、素子
中あるいはその近傍に欠陥がないことが望ましい。こう
した欠陥の原因は多々あるが、主として素子製造工程中
に受ける重金属汚染などによる場合と、シリコン結晶中
に含まれる酸素が素子製造工程の熱処理によって析出を
起す場合とがある。このようなことから、従来、欠陥の
発生を回避する手段として種々の試みが行なわれている
。As is well known, in order for various functional elements formed on the surface of a silicon substrate (wafer) to operate normally, it is desirable that there be no defects in or near the element. There are many causes for these defects, but mainly due to heavy metal contamination during the element manufacturing process, and oxygen contained in the silicon crystal precipitates during heat treatment during the element manufacturing process. For this reason, various attempts have been made to avoid the occurrence of defects.
第1の手段として、結晶成長中の融液に磁場をかけるこ
とにより得られた低い酸素濃度のウェハを用いることが
行なわれている。このように低酸素濃度のウェハを用い
れば、ウェハの表面領域での欠陥発生が少ないことが報
告されている(星他:半導体研究20、P254 (1
983))。しかしながら、大口径結晶を用いる傾向に
ある現在では、こうした低酸素濃度のウェハを得るため
には、巨大な磁場印加装置が必要となる。したがって、
装置の費用及び磁場印加に必要な電気代などを考慮する
と、一部の特殊な素子を除いてコスト高と。A first method is to use a wafer with a low oxygen concentration obtained by applying a magnetic field to a melt during crystal growth. It has been reported that by using a wafer with such a low oxygen concentration, fewer defects occur in the wafer surface area (Hoshi et al.: Semiconductor Research 20, p. 254 (1)
983)). However, with the current trend of using large-diameter crystals, obtaining wafers with such a low oxygen concentration requires a huge magnetic field application device. therefore,
Considering the cost of the device and the cost of electricity required to apply the magnetic field, the cost is high except for some special elements.
なる欠点を有する。It has some drawbacks.
また、第2の手段として、素子製造工程前にウェハを1
000〜1250℃で熱処理し、ウェハ表面近傍の酸素
濃度を低減する方法が採用されている。(松下、宇佐美
、渡辺二半導体研究20、Pl 98 (1983))
。しかしながら、こうした方法により工業的に常に安定
した無欠陥表面ウェハを得ることは困難である。実例と
して、最初清浄に管理された熱処理炉を用いて1000
〜1250℃の所定温度で4時間熱処理を行ない、素子
を形成した後、ウェハ表面近傍の欠陥の発生密度を調べ
たところ、第1表に示す結果が得られた。In addition, as a second means, one wafer is processed before the device manufacturing process.
A method of reducing the oxygen concentration near the wafer surface by performing heat treatment at 000 to 1250° C. has been adopted. (Matsushita, Usami, Watanabe 2 Semiconductor Research 20, Pl 98 (1983))
. However, it is difficult to obtain industrially stable defect-free surface wafers using such methods. As a practical example, we used a heat treatment furnace that was kept clean to begin with.
After performing a heat treatment at a predetermined temperature of ~1250° C. for 4 hours to form a device, the density of defects near the wafer surface was examined, and the results shown in Table 1 were obtained.
また、同一炉を同一温度条件で3ケ月使用した後、上記
と同一の熱処理を行った場合の欠陥発生密度を第1表に
併記する。Table 1 also shows the defect occurrence density when the same heat treatment as above was performed after using the same furnace for three months under the same temperature conditions.
第 1 表
第1表から、熱処理温度が高いぼどウェハ表面近傍の初
期の欠陥発生密度が小さく、欠陥の発生が抑制されてい
ることがわかる。一方、熱処理炉を清浄に管理するうえ
では、1000〜1250℃の範囲では温度が低いほう
が望ましい。これは以下のような理由による。すなわち
、熱処理炉に用いられる反応管の材質は、通常高純度石
英又は高純度炭化ケイ素であるが、いずれの場合も上記
温度範囲では高い温度はど劣化が速いことが経験的に知
られている。したがって、熱処理温度が高いほど、反応
管の交換回数が増え、製品のコスト高を招くためである
。Table 1 From Table 1, it can be seen that when the heat treatment temperature is high, the initial defect density near the wafer surface is low, and the generation of defects is suppressed. On the other hand, in order to keep the heat treatment furnace clean, it is desirable that the temperature is lower in the range of 1000 to 1250°C. This is due to the following reasons. In other words, the material of the reaction tube used in the heat treatment furnace is usually high-purity quartz or high-purity silicon carbide, but in either case, it is empirically known that the higher the temperature in the above temperature range, the faster the deterioration occurs. . Therefore, as the heat treatment temperature increases, the number of times the reaction tube must be replaced increases, leading to an increase in the cost of the product.
また、上記第1表において、熱処理温度が1250℃、
1200℃の場合、ウェハの3ケ月後の欠陥発生密度が
それぞれ40.23く個1011”)と高くなっている
ことから、劣化がゆっくりと経時的に変化し、この劣化
に起因してウェハが炉内で汚染を受けることがわかる。In addition, in Table 1 above, the heat treatment temperature is 1250°C,
In the case of 1200°C, the defect occurrence density after 3 months on the wafer is as high as 40.23 x 1011"), so the deterioration changes slowly over time, and due to this deterioration, the wafer It can be seen that there is contamination inside the furnace.
以上のことから、第2の手段では、ウェハを高温で熱処
理することは欠陥の発生を抑制するのにそれなりの効果
があるが、この手法を工業的に行おうとした場合、温度
の選択が問題となる。すなわち、1000〜1100℃
の温度範囲では欠陥の発生が十分に抑制されないのに対
し、1100℃以上では初期の欠陥の発生は十分に抑制
されているが、経時的には長期間熱処理を行なってい、
ろうちに欠陥発生が著しくなるおそれがある。 ”〔発
明の目的〕
本発明は上記事情に鑑みてなされたものであり、熱処理
炉の清浄度にかかわらずウェハ表面近傍の欠陥発生を抑
制し得るとともに、製品コストを低減できる半導体装置
の製造方法を提供しようとするものである。Based on the above, in the second method, heat-treating the wafer at high temperature has a certain effect on suppressing the occurrence of defects, but if this method is to be applied industrially, the selection of temperature is a problem. becomes. That is, 1000-1100℃
The occurrence of defects is not sufficiently suppressed in the temperature range of
There is a risk that defects will occur in the solder. ” [Object of the Invention] The present invention has been made in view of the above circumstances, and provides a method for manufacturing a semiconductor device that can suppress the occurrence of defects near the wafer surface regardless of the cleanliness of the heat treatment furnace, and can reduce product costs. This is what we are trying to provide.
本発明の半導体装置の製造方法は、半導体基゛板上に酸
化膜を形成した後、多結晶シリコン膜又はシリコン窒化
膜を堆積し、更に1150〜1250℃の温度で熱処理
することを特徴とするものである。The method for manufacturing a semiconductor device of the present invention is characterized in that after forming an oxide film on a semiconductor substrate, a polycrystalline silicon film or a silicon nitride film is deposited, and further heat treatment is performed at a temperature of 1150 to 1250°C. It is something.
このような方法によれば、多結晶シリコン膜又はシリコ
ン窒化膜が汚染に対してブロック効果を有するので、熱
処理炉の清浄度にかかわりなく長期間にわたりウェハ表
面の欠陥発生を抑制することができ、製品コストを低減
することができる。According to this method, since the polycrystalline silicon film or silicon nitride film has a blocking effect against contamination, it is possible to suppress the occurrence of defects on the wafer surface for a long period of time regardless of the cleanliness of the heat treatment furnace. Product costs can be reduced.
なお、熱処理温度を1150〜1250℃としたのは、
1150℃未満では欠陥発生を抑制する効果が小さく、
一方1250℃を超えると熱処理炉の劣化が速まったり
、熱処理炉の耐熱性の点で問題が生じるためである。The heat treatment temperature was set at 1150 to 1250°C because
Below 1150°C, the effect of suppressing defect generation is small;
On the other hand, if the temperature exceeds 1250°C, the deterioration of the heat treatment furnace will be accelerated and problems will arise in terms of heat resistance of the heat treatment furnace.
以下、本発明の実施例を第1図〜第4図を参照して説明
する。Embodiments of the present invention will be described below with reference to FIGS. 1 to 4.
まず、表面の結晶方位(100)、比抵抗20〜40Ω
・傷のN型シリコン基板1を酸素雰囲気。First, the surface crystal orientation (100), specific resistance 20-40Ω
- Place the scratched N-type silicon substrate 1 in an oxygen atmosphere.
中、950℃で熱処理し、その表面に膜厚800人の熱
酸化lI2を形成した(第1図図示)。次に、LPCV
D法により全面に膜厚1000人の多結晶シリコン膜3
を堆積した(第2図図示)。つづいて、様々な管理状況
にあり、清浄度の異なる4基の熱処理炉(A−D’)に
上記ウェハを装入し、それぞれN2雰囲気中、1200
℃で5時間熱処理を行ない、基板1の表面に低酸素層4
を形成した。更に、N2雰囲気中、700”Cで10時
間熱処理を行ない、基板1内部に酸素析出核層5をそれ
ぞれ形成したく第3図図示)。次いで、前記多結晶シリ
コン膜3をケミカルドライエツチングにより剥離した後
、熱酸化膜2を剥離し、更に基板1の表面を4pL再び
鏡面加工した(第4図図示)。A heat treatment was performed at 950° C. to form a thermally oxidized lI2 film with a thickness of 800 μm on the surface (as shown in FIG. 1). Next, LPCV
A polycrystalline silicon film 3 with a thickness of 1000 is applied to the entire surface using the D method.
was deposited (as shown in Figure 2). Next, the above-mentioned wafers were loaded into four heat treatment furnaces (A-D') under various management conditions and with different degrees of cleanliness, and each was heated for 1200 min in an N2 atmosphere.
℃ for 5 hours to form a low oxygen layer 4 on the surface of the substrate 1.
was formed. Furthermore, a heat treatment is performed at 700''C for 10 hours in an N2 atmosphere to form an oxygen precipitation nucleus layer 5 inside the substrate 1 (as shown in FIG. 3).Then, the polycrystalline silicon film 3 is peeled off by chemical dry etching. After that, the thermal oxide film 2 was peeled off, and the surface of the substrate 1 was mirror-finished again by 4 pL (as shown in FIG. 4).
その後、通常の方法により基板1表面に素子を形成し、
半導体装置を製造した。After that, elements are formed on the surface of the substrate 1 by a normal method,
Manufactured semiconductor devices.
以上の工程に対し、第4図までの工程を経たシリコン基
板の一部について、基板表面の欠陥発生密度(個/Ql
+2)を調べた。その結果を下記第2表に示す。なお、
第2表中比較例は、基板表面に熱酸化膜を形成した後、
多結晶シリコン膜を堆積する工程を除外した以外は上記
実施例と同一条件で処理した基板についての結果である
。また、第2表中比較は最初清浄に管理されていた熱処
理炉(A)を1200℃で3ケ月使用した後、この熱処
理炉(A−)を用いて1000℃の熱処理を行ったもの
である。Regarding the above process, the defect occurrence density (number/Ql
+2) was investigated. The results are shown in Table 2 below. In addition,
In the comparative example in Table 2, after forming a thermal oxide film on the substrate surface,
The results are for a substrate processed under the same conditions as in the above example except that the step of depositing a polycrystalline silicon film was omitted. In addition, the comparison in Table 2 is for heat treatment at 1000°C using the heat treatment furnace (A-) after using the heat treatment furnace (A), which was initially kept clean, at 1200°C for 3 months. .
第 2 表
第2表から明らかなように、基板上に熱酸化膜を形成し
、多結晶シリコン膜を堆積した後、高温で熱処理を行う
ことにより、熱処理炉の清浄度にかかわらず長期間にわ
たり表面欠陥密度を安定して低いレベルにすることがで
きる。Table 2 As is clear from Table 2, by forming a thermal oxide film on the substrate and depositing a polycrystalline silicon film, heat treatment is performed at high temperature for a long period of time regardless of the cleanliness of the heat treatment furnace. The surface defect density can be stably kept at a low level.
この効果の原因は、現在のところ、多結晶シリコン膜が
炉内汚染に対してなんらかのブロック効果を有するため
であると推定される。The cause of this effect is currently presumed to be that the polycrystalline silicon film has some kind of blocking effect against contamination inside the furnace.
また、熱処理炉の交換回数を減らすことができるので、
製品コストを低減することができる。In addition, the number of times the heat treatment furnace needs to be replaced can be reduced.
Product costs can be reduced.
なお、上記実施例では基板表面に酸化膜を形成した後、
全面に多結晶シリコン膜を堆積したが、多結晶シリコン
膜に限らず炉内汚染に対してブロック効果を有する他の
被膜、例えばシリコン窒化膜を形成しても同様の効果が
得られる。また、上記実施例では高温熱処理の後、低温
熱処理も行なったが、この低温熱処理は行なわなくても
本発明の効果には何等影響を及ぼさない。Note that in the above example, after forming an oxide film on the substrate surface,
Although a polycrystalline silicon film is deposited on the entire surface, the same effect can be obtained not only by forming a polycrystalline silicon film but also by forming another film having a blocking effect against contamination in the furnace, such as a silicon nitride film. Further, in the above embodiments, a low temperature heat treatment was also performed after the high temperature heat treatment, but even if this low temperature heat treatment is not performed, the effects of the present invention are not affected in any way.
以上詳述した如く本発明方法によれば、熱処理炉の清浄
度にかかわらず長期間にねたりウェハ表面近傍の欠陥発
生を抑制し得るとともに、製品コストを低減できる等顕
著な効果を奏するものである。As detailed above, the method of the present invention has remarkable effects such as suppressing long-term stagnation and the occurrence of defects near the wafer surface and reducing product costs, regardless of the cleanliness of the heat treatment furnace. be.
第1図〜第4図は本発明の実施例における半導体装置の
製造方法を示す断面図である。
1・・・P型シリコン基板、2・・・熱酸化膜、3・・
・多結晶シリコン膜、4・・・表面低酸素層、5・・・
酸素析出核層。
5 出願人代理人 弁理士 鈴江武彦
第4図1 to 4 are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present invention. 1...P-type silicon substrate, 2...thermal oxide film, 3...
・Polycrystalline silicon film, 4... surface low oxygen layer, 5...
Oxygen precipitation nucleation layer. 5 Applicant's agent Patent attorney Takehiko Suzue Figure 4
Claims (1)
膜又はシリコン窒化膜を堆積し、更に1150〜125
0℃の温度で熱処理することを特徴とする半導体装置の
製造方法。After forming an oxide film on the semiconductor substrate, a polycrystalline silicon film or a silicon nitride film is deposited, and further 1150 to 125
A method for manufacturing a semiconductor device, characterized in that heat treatment is performed at a temperature of 0°C.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25792284A JPS61135128A (en) | 1984-12-06 | 1984-12-06 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25792284A JPS61135128A (en) | 1984-12-06 | 1984-12-06 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS61135128A true JPS61135128A (en) | 1986-06-23 |
Family
ID=17313052
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25792284A Pending JPS61135128A (en) | 1984-12-06 | 1984-12-06 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS61135128A (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
US6448157B1 (en) * | 1999-02-02 | 2002-09-10 | Nec Corporation | Fabrication process for a semiconductor device |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916338A (en) * | 1982-07-19 | 1984-01-27 | Matsushita Electronics Corp | Heat treatment method for semiconductor substrate |
-
1984
- 1984-12-06 JP JP25792284A patent/JPS61135128A/en active Pending
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5916338A (en) * | 1982-07-19 | 1984-01-27 | Matsushita Electronics Corp | Heat treatment method for semiconductor substrate |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5189508A (en) * | 1988-03-30 | 1993-02-23 | Nippon Steel Corporation | Silicon wafer excelling in gettering ability and method for production thereof |
US5444001A (en) * | 1992-12-25 | 1995-08-22 | Nec Corporation | Method of manufacturing a semiconductor device readily capable of removing contaminants from a silicon substrate |
EP0635879A2 (en) * | 1993-07-22 | 1995-01-25 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
EP0635879A3 (en) * | 1993-07-22 | 1996-10-23 | Toshiba Kk | Semiconductor silicon wafer and process for producing it. |
US5738942A (en) * | 1993-07-22 | 1998-04-14 | Kabushiki Kaisha Toshiba | Semiconductor silicon wafer and process for producing it |
US6448157B1 (en) * | 1999-02-02 | 2002-09-10 | Nec Corporation | Fabrication process for a semiconductor device |
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