JPH08213403A - Semiconductor substrate and manufacture thereof - Google Patents

Semiconductor substrate and manufacture thereof

Info

Publication number
JPH08213403A
JPH08213403A JP1893395A JP1893395A JPH08213403A JP H08213403 A JPH08213403 A JP H08213403A JP 1893395 A JP1893395 A JP 1893395A JP 1893395 A JP1893395 A JP 1893395A JP H08213403 A JPH08213403 A JP H08213403A
Authority
JP
Japan
Prior art keywords
semiconductor substrate
heat treatment
sio
density
dislocations
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1893395A
Other languages
Japanese (ja)
Inventor
Koji Sueoka
浩治 末岡
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Steel Corp
Original Assignee
Sumitomo Metal Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Industries Ltd filed Critical Sumitomo Metal Industries Ltd
Priority to JP1893395A priority Critical patent/JPH08213403A/en
Publication of JPH08213403A publication Critical patent/JPH08213403A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To always effectively maintain the strength and gettering capacity by incorporating platelike SiO2 deposit due to dislocation in a specific density in a region separated at a specific distance or more from the surface of a semiconductor substrate. CONSTITUTION: A platelike SiO2 deposit 11b is contained in a density of 10<10> to 10<12> particles/cm<3> in an Si matrix 11a in a region separated at about 50μm or more from the surface of a semiconductor substrate 10, and oxygen between lattices is contained in a concentration of (8 to 12)×10<17> particles/cm<3> . Thus, a non-defect layer 12 is formed on an active region near the surface of the substrate, a defective layer 11 including the SiO2 deposit and dislocation is effectively formed therein, gettering capacity for contaminant substance is enhanced, and maintained. The decrease in the strength due to the oxygen between the lattices is prevented in the substrate. As a result, the increase in a leakage current, the decrease in an oxide film pressure resistance and the deformation can be prevented as well.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は半導体基板及びその製造
方法に関し、より詳細にはLSI等の集積回路形成用の
基板として用いられる単結晶Si(シリコン)半導体基
板及びその製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a manufacturing method thereof, and more particularly to a single crystal Si (silicon) semiconductor substrate used as a substrate for forming an integrated circuit such as an LSI and a manufacturing method thereof.

【0002】[0002]

【従来の技術】LSI等の集積回路形成用基板として用
いられている半導体基板の大部分は単結晶Siから製造
されており、この単結晶Siは石英るつぼ内に充填され
たSi溶融液を回転させながら引き上げるチョクラルス
キー法(CZ法)と呼ばれる引き上げ方法により形成さ
れている。
2. Description of the Related Art Most of semiconductor substrates used as substrates for forming integrated circuits such as LSIs are made of single crystal Si, and this single crystal Si spins a Si melt filled in a quartz crucible. It is formed by a pulling method called the Czochralski method (CZ method) of pulling up while allowing it to move.

【0003】単結晶SiをこのようなCZ法を用いて成
長させると、石英るつぼ自身がSi溶融液に溶解して酸
素を溶出し、一般的にこの酸素は固液界面からSiイン
ゴット中に(13〜17)×1017個/cm3 の濃度で
取り込まれる。
When single crystal Si is grown using such a CZ method, the quartz crucible itself dissolves in the Si melt and elutes oxygen, and this oxygen is generally introduced from the solid-liquid interface into the Si ingot ( 13 to 17 ) × 10 17 particles / cm 3 are taken in at a concentration of.

【0004】一方、例えばLSI製造時の代表的熱処理
温度である1000℃では、単結晶Si中の酸素の固溶
度は約3×1017個/cm3 であり、1000℃以下で
はさらに小さい値となっており、したがって単結晶Si
内に含有された酸素は常に飽和状態となっている。この
ため、LSI製造における熱処理時には酸素が単結晶S
i半導体基板(以下、単に半導体基板と記す)内に析出
し、SiO2 構造に変化する。すると、体積が膨張して
この周囲に歪みが生じる場合があり、歪みがある臨界値
を超えると転位が発生する。
On the other hand, for example, at 1000 ° C. which is a typical heat treatment temperature during LSI manufacturing, the solid solubility of oxygen in single crystal Si is about 3 × 10 17 pieces / cm 3 , and even below 1000 ° C. Therefore, single crystal Si
The oxygen contained therein is always saturated. For this reason, oxygen is converted into single crystal S during heat treatment in LSI manufacturing.
It is deposited in an i semiconductor substrate (hereinafter simply referred to as a semiconductor substrate) and changes into a SiO 2 structure. Then, the volume may expand and strain may occur around this, and when the strain exceeds a certain critical value, dislocation occurs.

【0005】これらのSiO2 析出物及び転位が前記半
導体基板の表面から数μmの範囲(LSI素子の活性領
域)に存在する場合、酸化膜耐圧の低下やリーク電流の
発生等が生じ、LSIにとって有害となる。他方、前記
半導体基板の表面から十分離れた内部のみに存在する場
合、前記転位がFe(鉄)、Ni(ニッケル)、Cu
(銅)等の重金属汚染物質を吸着し、この汚染物質を前
記素子の活性領域から除去するいわゆるゲッタリング作
用が働くため、高品位のLSIを製造する上で有用とな
る。
If these SiO 2 precipitates and dislocations are present within a range of several μm from the surface of the semiconductor substrate (active region of the LSI element), the breakdown voltage of the oxide film and the generation of leak current will occur, which will cause LSI failure. It is harmful. On the other hand, when the dislocations exist only inside the semiconductor substrate sufficiently distant from the surface, the dislocations are Fe (iron), Ni (nickel), Cu.
A so-called gettering action of adsorbing a heavy metal pollutant such as (copper) and removing the pollutant from the active region of the element is useful in manufacturing a high-quality LSI.

【0006】上記の理由により、前記半導体基板ではそ
の表面に前記SiO2 析出物及び転位が存在しない無欠
陥層(以下、DZ(Denuded Zone) 層と記す)を形成す
ると共に、その内部に前記SiO2 析出物及び転位が存
在する欠陥層(以下、IG(Internal Gettering) 層と
記す)を形成するための熱処理が施されている。具体的
には、例えば前記半導体基板に窒素雰囲気中1100℃
で4時間程度の熱処理を施し、酸素を外方に拡散させる
ことにより表面近傍における酸素濃度を低下させる(D
Z層の形成)。次いで窒素雰囲気中1100℃よりも低
い温度の熱処理を施し(例えば700℃で4時間加熱
後、1000℃で16時間加熱する)、前記半導体基板
の内部に前記SiO2 析出物及び転位を発生させる(I
G層の形成)。
For the above-mentioned reason, a defect-free layer (hereinafter referred to as a DZ (Denuded Zone) layer) free of the SiO 2 precipitates and dislocations is formed on the surface of the semiconductor substrate, and the SiO 2 is formed inside the layer. 2 Heat treatment is performed to form a defect layer (hereinafter, referred to as an IG (Internal Gettering) layer) in which precipitates and dislocations exist. Specifically, for example, the semiconductor substrate is heated to 1100 ° C. in a nitrogen atmosphere.
Then, heat treatment is performed for about 4 hours, and oxygen is diffused outward to reduce the oxygen concentration near the surface (D
Formation of Z layer). Then, a heat treatment at a temperature lower than 1100 ° C. is performed in a nitrogen atmosphere (for example, heating at 700 ° C. for 4 hours and then heating at 1000 ° C. for 16 hours) to generate the SiO 2 precipitates and dislocations inside the semiconductor substrate ( I
Formation of G layer).

【0007】[0007]

【発明が解決しようとする課題】上記した従来の半導体
基板及びその製造方法においては、 (1)SiO2 析出物の密度が109 個/cm3 以下と
低く、ゲッタリング能力が劣る場合がある。 (2)SiO2 析出物の密度は1010〜1012個/cm
3 と高いものの、ゲッタリング能力が劣る場合がある。 (3)ゲッタリング能力は優れる一方、半導体基板の強
度が低下し易く、デバイスプロセスのリソグラフィ工程
等に支障を生じる場合がある。という課題があった。
In the above-described conventional semiconductor substrate and the method for manufacturing the same, (1) the density of SiO 2 precipitates is as low as 10 9 pieces / cm 3 or less, and the gettering ability may be poor. . (2) Density of SiO 2 precipitates is 10 10 to 10 12 pieces / cm
Although it is as high as 3 , gettering ability may be inferior. (3) While the gettering ability is excellent, the strength of the semiconductor substrate is liable to be lowered, which may cause a hindrance to the lithography process of the device process. There was a problem.

【0008】本発明はこのような課題に鑑みなされたも
のであり、ゲッタリング能力を常時確実に維持させるこ
とができると共に、強度を維持することができ、この結
果、リーク電流の増大や酸化膜耐圧の低下を防止すると
共に、変形・破損等を防止することができる半導体基板
及びその製造方法を提供することを目的としている。
The present invention has been made in view of the above problems, and the gettering ability can be always reliably maintained and the strength can be maintained. As a result, an increase in leak current and an oxide film can be achieved. It is an object of the present invention to provide a semiconductor substrate and a method for manufacturing the same that can prevent the breakdown voltage from being lowered and can prevent deformation and damage.

【0009】[0009]

【課題を解決するための手段】上記目的を達成するため
に本発明に係る半導体基板は、酸素を含む半導体基板に
おいて、該半導体基板の表面から50μm以上離れた領
域に、転位を伴う板状のSiO2 析出物を1010〜10
12個/cm3 の密度で含有していることを特徴としてい
る。
In order to achieve the above object, a semiconductor substrate according to the present invention is a semiconductor substrate containing oxygen, which has a plate-like shape with dislocations in a region 50 μm or more away from the surface of the semiconductor substrate. SiO 2 precipitate is 10 10 to 10
It is characterized in that it is contained at a density of 12 pieces / cm 3 .

【0010】また本発明に係る半導体基板の製造方法
は、酸素を含む半導体基板に、窒素ガス雰囲気中110
0〜1200℃で2〜4時間の熱処理を施した後、温度
T(℃)、時間t(H)がそれぞれ750≦T≦95
0、8≦t≦32、及び1000≦T≦1050、8≦
t≦32の範囲にある2段階の熱処理を施すことを特徴
としている。
Further, in the method of manufacturing a semiconductor substrate according to the present invention, the semiconductor substrate containing oxygen is added to the semiconductor substrate in a nitrogen gas atmosphere at 110
After heat treatment at 0 to 1200 ° C. for 2 to 4 hours, temperature T (° C.) and time t (H) are 750 ≦ T ≦ 95, respectively.
0, 8 ≦ t ≦ 32, and 1000 ≦ T ≦ 1050, 8 ≦
The method is characterized by performing a two-step heat treatment in the range of t ≦ 32.

【0011】[0011]

【作用】本発明者は前記2段階の熱処理(第1段目の熱
処理と第2段目の熱処理)における熱処理温度T(℃)
及び時間t(H)と、板状のSiO2 析出物及び転位の
形成状態等との関係を調査した。 (1)第1段目の熱処理 (a)熱処理温度Tの影響 熱処理温度Tが750℃より低い場合、前記板状SiO
2 析出物の核の発生速度が遅いため、熱処理に長時間を
要し、生産効率が著しく低下することとなる。一方、熱
処理温度Tが950℃より高い場合、前記板状SiO2
析出物の核の発生密度が減少するため、前記第2段目の
熱処理の際、前記核より成長する前記板状SiO2 析出
物やこれに伴う転位の発生密度が小さくなり、ゲッタリ
ング能力が劣ることとなる。
The present inventor has found that the heat treatment temperature T (° C.) in the two-stage heat treatment (first-stage heat treatment and second-stage heat treatment)
And the relationship between the time t (H) and the formation state of plate-like SiO 2 precipitates and dislocations were investigated. (1) First stage heat treatment (a) Effect of heat treatment temperature T When the heat treatment temperature T is lower than 750 ° C., the plate-like SiO 2
(2 ) Since the rate of nucleation of precipitates is slow, the heat treatment requires a long time, resulting in a significant decrease in production efficiency. On the other hand, when the heat treatment temperature T is higher than 950 ° C, the plate-like SiO 2
Since the generation density of the precipitate nuclei is reduced, the generation density of the plate-like SiO 2 precipitates growing from the nuclei and the dislocations accompanied therewith becomes small during the second heat treatment, and the gettering ability is reduced. It will be inferior.

【0012】(b)熱処理時間tの影響 熱処理時間tが8Hより短い場合、前記板状SiO2
出物の核のサイズが小さいため、前記第2段目の熱処理
の際、前記核がSiマトリックス中に固溶・消失し易
い。したがってこの際に成長する該板状SiO2 析出物
やこれに伴う転位の発生密度が小さくなり、ゲッタリン
グ能力が劣ることとなる。一方、熱処理時間tが32H
より長い場合、格子間酸素濃度が低下するため、強度が
下って前記半導体基板に変形が生じ易くなると共に、生
産効率が低下することとなる。 (2)第2段目の熱処理 (a)熱処理温度Tの影響 熱処理温度Tが1000℃より低い場合、前記核を発生
源にして前記板状SiO2 析出物が所定サイズまで成長
し難く、歪みが少ないため、転位が発生し難く、例え所
定密度の前記板状SiO2 析出物が形成されても転位を
伴っていないので、ゲッタリング能力が劣ることとな
る。一方、熱処理温度Tが1050℃より高い場合、S
iO2 析出物の形状が多面体となり易く、この場合にお
ける該SiO2 析出物の周囲の歪みは小さく、転位が発
生し難いため、ゲッタリング能力が劣ることとなる。 (b)熱処理時間tの影響 熱処理時間tが8Hより短い場合、前記板状SiO2
出物が所定サイズまで成長し難く、歪みが少ないため、
転位が発生し難く、例え所定密度の前記板状SiO2
出物が形成されても転位を伴っていないので、ゲッタリ
ング能力が劣ることとなる。一方、熱処理時間tが32
Hより長い場合、格子間酸素濃度が低下するため、強度
が下って転位形成時に前記半導体基板に変形が生じると
共に、生産効率が低下することとなる。
(B) Effect of heat treatment time t When the heat treatment time t is shorter than 8H, the nuclei of the plate-like SiO 2 precipitates are small in size. It easily dissolves and disappears inside. Therefore, the density of the plate-like SiO 2 precipitates growing at this time and the dislocations accompanying it is reduced, and the gettering ability is deteriorated. On the other hand, the heat treatment time t is 32H
When the length is longer, the interstitial oxygen concentration is lowered, so that the strength is lowered, the semiconductor substrate is apt to be deformed, and the production efficiency is lowered. (2) Second stage heat treatment (a) Effect of heat treatment temperature T When the heat treatment temperature T is lower than 1000 ° C., it is difficult for the plate-like SiO 2 precipitates to grow to a predetermined size by using the nuclei as a generation source, and strain is generated. Since the dislocations are small, dislocations are hard to occur, and even if the plate-like SiO 2 precipitates of a predetermined density are formed, they are not accompanied by dislocations, resulting in poor gettering ability. On the other hand, when the heat treatment temperature T is higher than 1050 ° C, S
The shape of the iO 2 precipitate tends to be a polyhedron, the strain around the SiO 2 precipitate in this case is small, and dislocations are difficult to occur, resulting in poor gettering ability. (B) Effect of heat treatment time t When the heat treatment time t is shorter than 8H, it is difficult for the plate-like SiO 2 precipitates to grow to a predetermined size and the strain is small.
Dislocations are less likely to occur, and even if the plate-like SiO 2 precipitates of a predetermined density are formed, they do not accompany dislocations, resulting in poor gettering ability. On the other hand, the heat treatment time t is 32
When it is longer than H, the interstitial oxygen concentration is lowered, so that the strength is lowered, the semiconductor substrate is deformed at the time of dislocation formation, and the production efficiency is lowered.

【0013】上記構成の半導体基板によれば、該半導体
基板の表面から50μm以上離れた領域に、転位を伴う
板状のSiO2 析出物を1010〜1012個/cm3 の密
度で含有しているので、該SiO2 析出物の形状が板状
であるために歪みが生じ易く、この歪みにより該SiO
2 析出物の周囲にループ状の転位が発生することとな
る。このため、前記半導体基板の表面近傍におけるLS
I素子の活性領域にDZ層が構成されると共に、前記半
導体基板の内部に前記所定密度のSiO2 析出物及び転
位を含むIG層が確実に構成され、汚染物質に対するゲ
ッタリング能力が高められ、維持されることとなる。ま
た前記半導体基板の内部における格子間酸素濃度が8〜
12×1017個/cm3 程度に維持されるため、該格子
間酸素濃度の減少に伴う基板強度の低下が防止されるこ
ととなる。この結果、前記半導体基板におけるリーク電
流の増大や酸化膜耐圧の低下を防止すると共に、変形を
防止し得ることとなる。
According to the semiconductor substrate having the above structure, a plate-like SiO 2 precipitate accompanied with dislocations is contained in a region of 50 μm or more from the surface of the semiconductor substrate at a density of 10 10 to 10 12 pieces / cm 3. Since the SiO 2 precipitate has a plate-like shape, distortion is likely to occur, and this distortion causes the SiO 2
2 Loop-shaped dislocations will occur around the precipitate. Therefore, the LS near the surface of the semiconductor substrate
The DZ layer is formed in the active region of the I element, and the IG layer containing the predetermined density of SiO 2 precipitates and dislocations is surely formed inside the semiconductor substrate, and the gettering ability with respect to contaminants is enhanced. Will be maintained. Further, the interstitial oxygen concentration inside the semiconductor substrate is 8 to
Since it is maintained at about 12 × 10 17 pieces / cm 3 , it is possible to prevent the decrease in the substrate strength due to the decrease in the interstitial oxygen concentration. As a result, it is possible to prevent an increase in leak current and a decrease in breakdown voltage of the oxide film in the semiconductor substrate and prevent deformation.

【0014】また上記構成の半導体基板の製造方法によ
れば、酸素を含む半導体基板に、窒素ガス雰囲気中11
00〜1200℃で2〜4時間の熱処理(以下、前熱処
理と記す)を施した後、温度T(℃)、時間t(Hr)
がそれぞれ750≦T≦950、8≦t≦32(第1段
目の熱処理)、及び1000≦T≦1050、8≦t≦
32(第2段目の熱処理)の範囲にある2段階の熱処理
を施すので、前記前熱処理により酸素が外方に拡散し、
前記半導体基板の表面から約50μmまでの範囲にDZ
層が構成されることとなる。一方、前記前熱処理の温度
が1100℃未満では酸素の外方への拡散が生じ難く、
前記DZ層の幅が大きくならない。また1200℃を超
えると、熱処理装置からの汚染により前記半導体基板の
表面が荒れてしまう。また前記前熱処理の時間が2時間
未満の場合でも酸素の外方への拡散が生じ難く、前記D
Z層の幅が大きくならない。他方、4時間を超える前記
前熱処理を施しても、作用が飽和するので生産性が低下
することとなる。
Further, according to the method of manufacturing a semiconductor substrate having the above structure, the semiconductor substrate containing oxygen is placed in a nitrogen gas atmosphere 11
After heat treatment (hereinafter referred to as pre-heat treatment) at 00 to 1200 ° C. for 2 to 4 hours, temperature T (° C.), time t (Hr)
Are 750 ≦ T ≦ 950, 8 ≦ t ≦ 32 (first-stage heat treatment), and 1000 ≦ T ≦ 1050, 8 ≦ t ≦, respectively.
Since the two-step heat treatment in the range of 32 (second heat treatment) is performed, oxygen is diffused outward by the preheat treatment,
DZ within a range of about 50 μm from the surface of the semiconductor substrate
The layers will be composed. On the other hand, when the temperature of the preheat treatment is less than 1100 ° C., it is difficult for oxygen to diffuse outward,
The width of the DZ layer does not increase. On the other hand, when the temperature exceeds 1200 ° C., the surface of the semiconductor substrate becomes rough due to contamination from the heat treatment apparatus. Further, even if the preheat treatment time is less than 2 hours, it is difficult for oxygen to diffuse outward.
The width of the Z layer does not increase. On the other hand, even if the pre-heat treatment is performed for more than 4 hours, the action is saturated and the productivity is lowered.

【0015】また前記第1段目の熱処理により、前記半
導体基板の表面から50μm以上離れた領域に1010
1012個/cm3 の密度を有する板状のSiO2 析出物
の発生核が確実、かつ効率的に形成されると共に、格子
間酸素濃度が(8〜12)×1017個/cm3 程度に維
持されることとなる。また前記第2段目の熱処理によ
り、前記核から前記所定密度を有する板状のSiO2
出物が成長してこの周囲に局部的な歪みが生じ、かつ前
記格子間酸素の存在により強度が維持されるため、前記
半導体基板の変形が防止されつつ、前記SiO2 析出物
の周囲にループ状の転位が確実に形成されることとな
る。
[0015] The by first-stage heat treatment, 10 of 10 to the remote or 50μm from the surface of the semiconductor substrate region
Nuclei of plate-like SiO 2 precipitates having a density of 10 12 / cm 3 are formed reliably and efficiently, and the interstitial oxygen concentration is (8 to 12) × 10 17 / cm 3. Will be maintained. Further, by the heat treatment in the second step, a plate-like SiO 2 precipitate having the predetermined density grows from the nuclei to locally generate strain, and the strength is maintained by the presence of the interstitial oxygen. Therefore, while preventing the deformation of the semiconductor substrate, loop-shaped dislocations are surely formed around the SiO 2 precipitate.

【0016】[0016]

【実施例及び比較例】以下、本発明に係る半導体基板及
びその製造方法の実施例を図面に基づいて説明する。図
1は本発明に係る半導体基板の実施例を模式的に示した
断面図であり、半導体基板の断面を赤外トモグラフ法に
より撮影し、この写真をスケッチした図である。半導体
基板10の表面から約50μm以上離れた領域には、板
状のSiO2析出物11bがSiマトリックス11a中
1010〜1012個/cm3 の密度で含有されると共に、
格子間酸素(図示せず)が(8〜12)×1017個/c
3 の濃度で含有されている。また図2に示したように
SiO2 析出物11bは2枚の{100}面により囲ま
れ、厚さdが約40Åの略板形状に形成され、この周囲
にループ状の転位11cを伴っており、これらSiマト
リックス11a、板状のSiO2 析出物11b、転位1
1c、格子間酸素等を含んでIG層11が構成されてい
る。また半導体基板10の表面から約50μm以内の領
域はSiマトリックス12a中に酸素、板状のSiO2
析出物及び転位がほとんど含まれていないDZ層12と
なっている。これらIG層11、DZ層12を含んで半
導体基板10が構成されている。
EXAMPLES AND COMPARATIVE EXAMPLES Examples of a semiconductor substrate and a method of manufacturing the same according to the present invention will be described below with reference to the drawings. FIG. 1 is a cross-sectional view schematically showing an embodiment of a semiconductor substrate according to the present invention, which is a sketch of a photograph of a cross section of the semiconductor substrate taken by an infrared tomography method. In a region away from the surface of the semiconductor substrate 10 by about 50 μm or more, plate-like SiO 2 precipitates 11b are contained in the Si matrix 11a at a density of 10 10 to 10 12 pieces / cm 3 , and
Interstitial oxygen (not shown) is (8-12) × 10 17 pieces / c
It is contained at a concentration of m 3 . Further, as shown in FIG. 2, the SiO 2 precipitate 11b is surrounded by two {100} planes and is formed into a substantially plate shape having a thickness d of about 40Å, with loop-like dislocations 11c around the periphery. And these Si matrix 11a, plate-like SiO 2 precipitate 11b, dislocation 1
The IG layer 11 includes 1c, interstitial oxygen, and the like. In the region within about 50 μm from the surface of the semiconductor substrate 10, oxygen is contained in the Si matrix 12a and plate-like SiO 2 is used.
The DZ layer 12 contains almost no precipitates and dislocations. The semiconductor substrate 10 is configured to include the IG layer 11 and the DZ layer 12.

【0017】図3は実施例に係る半導体基板の製造方法
に用いる熱処理装置を模式的に示した斜視図であり、図
中21aは所定長さを有する略中空円筒形状の石英チュ
ーブを示している。石英チューブ21aの周囲には複数
個のヒータ(図示せず)が配設されており、このヒータ
により石英チューブ21a内の所定箇所がそれぞれ所定
温度に設定されるようになっている。また石英チューブ
21aにはガス供給系(図示せず)が接続され、このガ
ス供給系を介して窒素または酸素を導入することによ
り、石英チューブ21a内の雰囲気が制御されるように
なっており、これら石英チューブ21a、ヒータ、ガス
供給系等を含んで熱処理炉21が構成されている。一
方、略板形状の石英ボード22a上には略箱形状をした
石英製のトレイ22bが載置されており、トレイ22b
内には半導体基板となるSiウエハ10aが収容されて
いる。Siウエハ10aはトレイ22bの両側壁部に形
成されたスリット部22cに挿入されて縦方向に設置さ
れており、これら石英ボード22a、トレイ22bを含
んで、ウエハ支持手段22が構成されている。トレイ2
2bは熱処理炉21の入口部21bから図中矢印方向に
挿入され、石英チューブ21a内を所定の一定速度で搬
送され、入口部21bから再び取り出されるようになっ
ており、これら熱処理炉21、ウエハ支持手段22を含
んで熱処理装置20が構成されている。
FIG. 3 is a perspective view schematically showing a heat treatment apparatus used in the method of manufacturing a semiconductor substrate according to the embodiment. In the figure, reference numeral 21a indicates a substantially hollow cylindrical quartz tube having a predetermined length. . A plurality of heaters (not shown) are arranged around the quartz tube 21a, and the heaters are used to set predetermined locations in the quartz tube 21a to predetermined temperatures. A gas supply system (not shown) is connected to the quartz tube 21a, and the atmosphere inside the quartz tube 21a is controlled by introducing nitrogen or oxygen through this gas supply system. The heat treatment furnace 21 is configured to include the quartz tube 21a, a heater, a gas supply system, and the like. On the other hand, a substantially box-shaped quartz tray 22b is placed on the substantially plate-shaped quartz board 22a.
A Si wafer 10a to be a semiconductor substrate is housed inside. The Si wafer 10a is inserted into slit portions 22c formed on both side wall portions of the tray 22b and installed in the vertical direction, and the wafer supporting means 22 is constituted by including the quartz board 22a and the tray 22b. Tray 2
2b is inserted from the inlet portion 21b of the heat treatment furnace 21 in the direction of the arrow in the drawing, is conveyed in the quartz tube 21a at a predetermined constant speed, and is taken out again from the inlet portion 21b. The heat treatment apparatus 20 is configured to include the support means 22.

【0018】このように構成された装置20を用いて半
導体基板10を製造する場合、まず石英チューブ21a
内に窒素ガスを導入した後、前記ヒータへの印加電流を
制御して石英チューブ21aの温度を1100〜120
0℃に設定する。次にウエハ支持手段22に収容された
Siウエハ10aを熱処理炉21内に例えば約50mm
/minの所定速度で挿入する。そして図4の熱処理パ
ターンに示したように、ウエハ10aに1100〜12
00℃で2〜4H(時間)の前熱処理を施し、次に75
0〜950℃で8〜32Hの第1段目の熱処理を施し、
さらに1000〜1050℃で8〜32Hの第2段目の
熱処理を施した後、半導体基板10として熱処理炉21
から取り出す。
When the semiconductor substrate 10 is manufactured using the apparatus 20 having the above structure, first, the quartz tube 21a is used.
After introducing nitrogen gas into the chamber, the current applied to the heater is controlled to control the temperature of the quartz tube 21a from 1100 to 120.
Set to 0 ° C. Next, the Si wafer 10a accommodated in the wafer support means 22 is placed in the heat treatment furnace 21 for about 50 mm, for example.
Insert at a predetermined speed of / min. Then, as shown in the heat treatment pattern of FIG.
Pre-heat treatment at 00 ° C for 2-4H (hours), then 75
The first stage heat treatment of 0 to 32H at 0 to 950 ° C is performed,
After the second stage heat treatment at 1000 to 1050 ° C. for 8 to 32 H, the semiconductor substrate 10 is treated as a heat treatment furnace 21.
Take out from.

【0019】以下に実施例に係る半導体基板10におけ
る板状SiO2 析出物の密度、転位の有無、表面欠陥の
密度、格子間酸素濃度及び基板強度と、各熱処理の温度
及び時間との関係について調査した結果を説明する。ウ
エハ10aとしては直径が約150mm、厚さが約0.
63mmのSiウエハを用いた。板状SiO2 析出物の
密度はTEMを用いて複数個の試料面を観察し、板状の
SiO2 析出物の個数を数え、これを観察面積当たりの
個数に換算することにより求めた。また転位の有無は前
記した板状SiO2 析出物の密度を測定する際、同時に
観察・測定した。また表面欠陥密度は、半導体基板10
に関して窒素雰囲気中約900℃で約0.3時間のFe
(鉄)拡散処理を施し、さらに酸素雰囲気中約1100
℃で約16時間程度の酸化処理を施した試料を用いた。
そしてこの試料表面に選択エッチング処理を施し、光学
顕微鏡を用いた観察方法により表面欠陥密度を求め、こ
の表面欠陥密度が少ない場合、ゲッタリング能力が高い
と判定した。また格子間酸素濃度はFTIR(フーリエ
変換型赤外吸収法)により求めた。さらに基板強度は基
板作製後の半導体基板10の反りの大きさを厚さ計で測
定し、反りの大きさが後工程に影響を及ぼさない5μm
以下のものを「可」、5μmを超えるものを「不可」と
して評価した。
Regarding the relationship between the density of plate-like SiO 2 precipitates, the presence or absence of dislocations, the density of surface defects, the interstitial oxygen concentration and the substrate strength, and the temperature and time of each heat treatment in the semiconductor substrate 10 according to the examples below. The results of the investigation will be explained. The wafer 10a has a diameter of about 150 mm and a thickness of about 0.
A 63 mm Si wafer was used. The density of plate-like SiO 2 precipitates was obtained by observing a plurality of sample surfaces using a TEM, counting the number of plate-like SiO 2 precipitates, and converting this to the number per observed area. The presence or absence of dislocations was observed and measured at the same time when the density of the plate-like SiO 2 precipitate was measured. The surface defect density is determined by the semiconductor substrate 10
For about 0.3 hours in nitrogen atmosphere at about 900 ℃ Fe
(Iron) diffusion treatment is applied, and further in oxygen atmosphere about 1100
A sample that had been subjected to an oxidation treatment at a temperature of about 16 hours was used.
Then, the sample surface was subjected to selective etching treatment, and the surface defect density was determined by an observation method using an optical microscope. When the surface defect density was low, it was determined that the gettering ability was high. The interstitial oxygen concentration was determined by FTIR (Fourier transform infrared absorption method). Further, the substrate strength is measured by measuring the amount of warpage of the semiconductor substrate 10 after manufacturing the substrate with a thickness gauge, and the amount of warpage does not affect the subsequent steps.
The following items were evaluated as “OK” and those exceeding 5 μm were evaluated as “Fail”.

【0020】なお比較例として、前熱処理の時間が短い
もの(比較例1〜9)、前処理の時間が長いもの(比較
例10〜18)、第1段目の熱処理の温度または時間が
実施例に係る範囲から外れたもの(比較例2〜7、11
〜16、21〜26)、第2段目の熱処理の温度または
時間が実施例に係る範囲から外れたもの(比較例3〜
4、6〜9、12〜13、15〜22、24〜25)を
選んだ。実施例1〜8及び比較例1〜26に関する調査
結果を下記の表1に併せて示した。
As comparative examples, those for which the pre-heat treatment time is short (Comparative Examples 1 to 9), those for which the pre-treatment time is long (Comparative Examples 10 to 18), and the temperature or time for the first-stage heat treatment are carried out. Those outside the range of the examples (Comparative Examples 2 to 7, 11)
˜16, 21 to 26), and the temperature or time of the second stage heat treatment is out of the range according to the example (Comparative example 3 to
4, 6-9, 12-13, 15-22, 24-25) were selected. The results of the investigations relating to Examples 1 to 8 and Comparative Examples 1 to 26 are also shown in Table 1 below.

【0021】[0021]

【表1−1】 [Table 1-1]

【0022】[0022]

【表1−2】 [Table 1-2]

【0023】表1の結果から明らかなように、比較例1
〜26の方法により製造された半導体基板は、 (1)板状SiO2 析出物の密度が低く、転位を伴って
いない。 (2)SiO2 析出物の密度は高いが、該SiO2 析出
物の形状が板状でないため、転位を伴っていない。 (3)格子間酸素濃度が低い。 のいずれかの状態であるか、あるいは熱処理時間が長く
なり生産性が低下した。一方、実施例1〜8の方法によ
り製造された半導体基板10では、いずれも表面から5
0μm以上離れた領域に板状のSiO2 析出物11bが
1010〜1012個/cm3 の密度で含有されると共に、
SiO2 析出物11bは転位11cを伴っていた。また
いずれも表面欠陥密度が低く、ゲッタリング能力に優れ
ると共に、強度の低下(変形)が少なかった。
As is clear from the results shown in Table 1, Comparative Example 1
The semiconductor substrates manufactured by the methods No. 26 to (26) have a low density of plate-like SiO 2 precipitates and are free from dislocations. (2) The density of the SiO 2 precipitate is high, but the shape of the SiO 2 precipitate is not plate-like, so that it does not cause dislocation. (3) The interstitial oxygen concentration is low. Either of these states, or the heat treatment time became longer and the productivity decreased. On the other hand, in each of the semiconductor substrates 10 manufactured by the methods of Examples 1 to 8, 5
The plate-like SiO 2 precipitates 11b are contained in a region separated by 0 μm or more at a density of 10 10 to 10 12 pieces / cm 3 , and
The SiO 2 precipitate 11b was accompanied by dislocations 11c. Further, in each case, the surface defect density was low, the gettering ability was excellent, and the reduction in strength (deformation) was small.

【0024】上記結果から明らかなように、実施例に係
る半導体基板10の製造方法によれば、前熱処理により
酸素が外方に拡散され、半導体基板10の表面から約5
0μmまでの範囲に略完全なDZ層12が形成される。
また第1段目の熱処理により、半導体基板10の表面か
ら50μm以上離れた領域に1010〜1012個/cm3
の密度を有する板状のSiO2 析出物11bの発生核が
確実、かつ効率的に形成されると共に、格子間酸素濃度
が(8〜12)×1017個/cm3 程度に維持される。
また第2段目の熱処理により、発生核から所定密度を有
する板状のSiO2 析出物11bが成長してこの周囲に
局部的な歪みが生じ、かつ所定濃度の格子間酸素の存在
が維持される。またSiO2 析出物11bの周囲にルー
プ状の転位11cが確実に形成されることとなる。この
結果、実施例に係る半導体基板10では、SiO2 析出
物11bの形状が板状であるために歪みが生じ易く、こ
の歪みによりSiO2 析出物11bの周囲にループ状の
転位が発生する。このため、半導体基板10の表面近傍
におけるLSI素子の活性領域に略完全なDZ層12が
形成されると共に、半導体基板10の内部に所定密度の
SiO2 析出物11b及び転位11cを含むIG層11
が確実に形成され、Fe等の汚染物質に対するゲッタリ
ング能力が高められる。また半導体基板10の内部にお
ける格子間酸素濃度が8〜12×1017個/cm3 程度
に維持されるため、この格子間酸素濃度の減少に伴う強
度の低下が防止される。この結果、半導体基板10にお
けるリーク電流の増大や酸化膜耐圧の低下を防止すると
共に、変形を防止することができる。
As is clear from the above results, according to the method of manufacturing the semiconductor substrate 10 of the example, oxygen is diffused outward by the pre-heat treatment, and about 5% of oxygen is diffused from the surface of the semiconductor substrate 10.
A substantially complete DZ layer 12 is formed in the range of 0 μm.
Further, by the first-stage heat treatment, 10 10 to 10 12 pieces / cm 3 are formed in a region 50 μm or more away from the surface of the semiconductor substrate 10.
The generation nuclei of the plate-like SiO 2 precipitates 11b having a density of 1 are reliably and efficiently formed, and the interstitial oxygen concentration is maintained at about (8 to 12) × 10 17 pieces / cm 3 .
Further, by the second stage heat treatment, a plate-like SiO 2 precipitate 11b having a predetermined density grows from the generated nuclei, a local strain is generated around this, and the existence of interstitial oxygen of a predetermined concentration is maintained. It Further, loop-shaped dislocations 11c are surely formed around the SiO 2 precipitates 11b. As a result, in the semiconductor substrate 10 according to the example, strain is likely to occur because the SiO 2 precipitate 11b has a plate shape, and this strain causes loop-shaped dislocations around the SiO 2 precipitate 11b. Therefore, a substantially complete DZ layer 12 is formed in the active region of the LSI element near the surface of the semiconductor substrate 10, and the IG layer 11 containing SiO 2 precipitates 11b and dislocations 11c of a predetermined density is formed inside the semiconductor substrate 10.
Are reliably formed, and the gettering ability for contaminants such as Fe is enhanced. Further, since the interstitial oxygen concentration inside the semiconductor substrate 10 is maintained at about 8 to 12 × 10 17 oxygen atoms / cm 3 , the decrease in strength due to the reduction in the interstitial oxygen concentration is prevented. As a result, it is possible to prevent an increase in leak current in the semiconductor substrate 10 and a decrease in breakdown voltage of the oxide film, and also to prevent deformation.

【0025】なお、上記実施例に係る製造方法では、石
英チューブ21aが内蔵された形式の熱処理炉21を用
いた場合について説明したが、何らこの形式の熱処理炉
に限定されるものではなく、所定の熱処理の雰囲気、温
度及び時間とが制御し得るものであればよい。
In the manufacturing method according to the above-described embodiment, the case where the heat treatment furnace 21 of the type having the quartz tube 21a built therein is used has been described, but the heat treatment furnace of the type is not limited to the heat treatment furnace of a predetermined type. The heat treatment atmosphere, temperature and time may be controlled.

【0026】また、上記実施例に係る製造方法では、ウ
エハ10aがウエハ支持手段22に収容された場合につ
いて説明したが、何らこの構造のウエハ支持手段に限定
されるものではなく、ウエハ10aに応力が掛からず、
ウエハ10aと雰囲気ガスとが十分に接触し、ウエハ1
0aが均一に加熱される構造のものであればよい。
Further, in the manufacturing method according to the above-described embodiment, the case where the wafer 10a is housed in the wafer supporting means 22 has been described. However, the wafer supporting means 22 is not limited to the wafer supporting means having this structure, and the stress is applied to the wafer 10a. Does not take
The wafer 10a and the atmospheric gas are sufficiently contacted, and the wafer 1
Any structure may be used as long as 0a is uniformly heated.

【0027】また、上記実施例に係る製造方法では、ウ
エハ10aが約50mm/minの速度で熱処理炉21
内に挿入される場合について説明したが、何ら50mm
/minには限定されるものではない。
Further, in the manufacturing method according to the above-described embodiment, the wafer 10a is heat-treated in the heat treatment furnace 21 at a speed of about 50 mm / min.
The case where it was inserted into the inside was explained, but there is no 50mm.
It is not limited to / min.

【0028】[0028]

【発明の効果】以上詳述したように本発明に係る半導体
基板にあっては、該半導体基板の表面から50μm以上
離れた領域に、転位を伴う板状のSiO2 析出物を10
10〜1012個/cm3 の密度で含有しているので、該S
iO2 析出物の形状が板状であるために歪みが生じ易
く、この歪みにより該SiO2 析出物の周囲にループ状
の転位が発生する。このため、前記半導体基板の表面近
傍におけるLSI素子の活性領域にDZ層が構成される
と共に、前記半導体基板の内部に前記所定密度のSiO
2 析出物及び転位を含むIG層が確実に構成され、汚染
物質に対するゲッタリング能力が高められ、維持され
る。また前記半導体基板の内部における格子間酸素濃度
が8〜12×1017個/cm3 程度に維持されるため、
該格子間酸素濃度の減少に伴う強度の低下が防止され
る。この結果、前記半導体基板におけるリーク電流の増
大や酸化膜耐圧の低下を防止すると共に、変形を防止す
ることができる。
As described above in detail, in the semiconductor substrate according to the present invention, a plate-like SiO 2 precipitate accompanied by dislocations is formed in the region of 50 μm or more from the surface of the semiconductor substrate.
Since it is contained at a density of 10 to 10 12 pieces / cm 3 , the S
Since the shape of the iO 2 precipitate is plate-like, distortion is likely to occur, and this distortion causes loop-shaped dislocations around the SiO 2 precipitate. Therefore, the DZ layer is formed in the active region of the LSI element near the surface of the semiconductor substrate, and the SiO 2 having the predetermined density is formed inside the semiconductor substrate.
2 The IG layer containing precipitates and dislocations is surely formed, and the gettering ability for contaminants is enhanced and maintained. Further, since the interstitial oxygen concentration inside the semiconductor substrate is maintained at about 8 to 12 × 10 17 oxygen atoms / cm 3 ,
A decrease in strength due to a decrease in the interstitial oxygen concentration is prevented. As a result, it is possible to prevent the increase of the leak current and the decrease of the withstand voltage of the oxide film in the semiconductor substrate and the deformation.

【0029】また本発明に係る半導体基板の製造方法に
あっては、酸素を含む半導体基板に、窒素ガス雰囲気中
1100〜1200℃で2〜4時間の前熱処理を施した
後、温度T(℃)、時間t(Hr)がそれぞれ750≦
T≦950、8≦t≦32(第1段目の熱処理)、及び
1000≦T≦1050、8≦t≦32(第2段目の熱
処理)の範囲にある2段階の熱処理を施すので、前記前
熱処理により酸素が外方に拡散し、前記半導体基板の表
面から約50μmまでの範囲にDZ層が構成される。ま
た前記第1段目の熱処理により、前記半導体基板の表面
から50μm以上離れた領域に1010〜1012個/cm
3 の密度を有する板状のSiO2 析出物の発生核が確
実、かつ効率的に形成されると共に、格子間酸素濃度が
(8〜12)×1017個/cm3 程度に維持される。ま
た前記第2段目の熱処理により、前記核から前記所定密
度を有する板状のSiO2 析出物が成長してこの周囲に
局部的な歪みが生じ、かつ前記格子間酸素の存在により
強度が維持されるため、前記半導体基板の変形が防止さ
れつつ、前記SiO2 析出物の周囲にループ状の転位が
確実に形成される。
Further, in the method of manufacturing a semiconductor substrate according to the present invention, the semiconductor substrate containing oxygen is preheated in a nitrogen gas atmosphere at 1100 to 1200 ° C. for 2 to 4 hours, and then the temperature T (° C. ), And time t (Hr) is 750 ≦
Since the two-stage heat treatment in the range of T ≦ 950, 8 ≦ t ≦ 32 (first-stage heat treatment) and 1000 ≦ T ≦ 1050, 8 ≦ t ≦ 32 (second-stage heat treatment) is performed, Oxygen is diffused outward by the pre-heat treatment, and a DZ layer is formed within a range of about 50 μm from the surface of the semiconductor substrate. Further, by the first-stage heat treatment, 10 10 to 10 12 pieces / cm 2 are formed in a region 50 μm or more away from the surface of the semiconductor substrate.
Generation nuclei of plate-like SiO 2 precipitates having a density of 3 are formed reliably and efficiently, and the interstitial oxygen concentration is maintained at (8-12) × 10 17 pieces / cm 3 . Further, by the heat treatment in the second step, a plate-like SiO 2 precipitate having the predetermined density grows from the nuclei to locally generate strain, and the strength is maintained by the presence of the interstitial oxygen. Therefore, the semiconductor substrate is prevented from being deformed, and loop-shaped dislocations are surely formed around the SiO 2 precipitate.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る半導体基板の実施例を模式的に示
した断面図であり、半導体基板の断面を赤外トモグラフ
法により撮影し、この写真をスケッチした図である。
FIG. 1 is a cross-sectional view schematically showing an embodiment of a semiconductor substrate according to the present invention, in which a cross-section of a semiconductor substrate is photographed by an infrared tomography method and this photograph is sketched.

【図2】実施例に係る半導体基板内部に形成された板状
のSiO2 析出物と転位とを示した模式図であり、TE
M(等価型電子顕微鏡)により撮影した写真をスケッチ
した図である。
FIG. 2 is a schematic view showing plate-like SiO 2 precipitates and dislocations formed inside a semiconductor substrate according to an example.
It is the figure which sketched the photograph image | photographed by M (equivalent electron microscope).

【図3】実施例に係る半導体基板の製造方法に用いる熱
処理装置を模式的に示した斜視図である。
FIG. 3 is a perspective view schematically showing a heat treatment apparatus used in the method for manufacturing a semiconductor substrate according to the example.

【図4】実施例に係る半導体基板の製造方法における熱
処理パターンを示した模式図である。
FIG. 4 is a schematic view showing a heat treatment pattern in a method for manufacturing a semiconductor substrate according to an example.

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 酸素を含む半導体基板において、該半導
体基板の表面から50μm以上離れた領域に、転位を伴
う板状のSiO2 析出物を1010〜1012個/cm3
密度で含有していることを特徴とする半導体基板。
1. A semiconductor substrate containing oxygen, containing plate-like SiO 2 precipitates accompanied with dislocations at a density of 10 10 to 10 12 / cm 3 in a region 50 μm or more away from the surface of the semiconductor substrate. A semiconductor substrate characterized in that.
【請求項2】 酸素を含む半導体基板に、窒素ガス雰囲
気中1100〜1200℃で2〜4時間の熱処理を施し
た後、温度T(℃)、時間t(H)がそれぞれ750≦
T≦950、8≦t≦32、及び1000≦T≦105
0、8≦t≦32の範囲にある2段階の熱処理を施すこ
とを特徴とする請求項1記載の半導体基板の製造方法。
2. A semiconductor substrate containing oxygen is subjected to heat treatment at 1100 to 1200 ° C. for 2 to 4 hours in a nitrogen gas atmosphere, and then temperature T (° C.) and time t (H) are each 750 ≦.
T ≦ 950, 8 ≦ t ≦ 32, and 1000 ≦ T ≦ 105
2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the heat treatment is performed in two stages within a range of 0, 8≤t≤32.
JP1893395A 1995-02-07 1995-02-07 Semiconductor substrate and manufacture thereof Pending JPH08213403A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1893395A JPH08213403A (en) 1995-02-07 1995-02-07 Semiconductor substrate and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1893395A JPH08213403A (en) 1995-02-07 1995-02-07 Semiconductor substrate and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH08213403A true JPH08213403A (en) 1996-08-20

Family

ID=11985448

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1893395A Pending JPH08213403A (en) 1995-02-07 1995-02-07 Semiconductor substrate and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH08213403A (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2002049091A1 (en) * 2000-12-13 2002-06-20 Shin-Etsu Handotai Co., Ltd. Anneal wafer manufacturing method and anneal wafer
US7081422B2 (en) 2000-12-13 2006-07-25 Shin-Etsu Handotai Co., Ltd. Manufacturing process for annealed wafer and annealed wafer
EP1928016A1 (en) * 2006-12-01 2008-06-04 Siltronic AG Silicon wafer and method for manufacturing the same
JP2008166721A (en) * 2006-12-07 2008-07-17 Siltronic Ag Silicon wafer and manufacturing method thereof
WO2008136500A1 (en) 2007-05-02 2008-11-13 Siltronic Ag Silicon wafer and method for manufacturing the same
EP2345753A1 (en) * 2009-12-29 2011-07-20 Siltronic AG Silicon wafer and production method therefor
US8197594B2 (en) 2006-09-20 2012-06-12 Siltronic Ag Silicon wafer for semiconductor and manufacturing method thereof
KR101345641B1 (en) * 2005-11-29 2013-12-30 제이엔씨 주식회사 Production process for high purity polycrystal silicon and production apparatus for the same
JP2018046107A (en) * 2016-09-13 2018-03-22 信越半導体株式会社 Method for heat treatment of silicon wafer and method for manufacturing silicon wafer

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002184779A (en) * 2000-12-13 2002-06-28 Shin Etsu Handotai Co Ltd Annealed wafer and method of manufacturing the same
US7081422B2 (en) 2000-12-13 2006-07-25 Shin-Etsu Handotai Co., Ltd. Manufacturing process for annealed wafer and annealed wafer
WO2002049091A1 (en) * 2000-12-13 2002-06-20 Shin-Etsu Handotai Co., Ltd. Anneal wafer manufacturing method and anneal wafer
KR101345641B1 (en) * 2005-11-29 2013-12-30 제이엔씨 주식회사 Production process for high purity polycrystal silicon and production apparatus for the same
US8197594B2 (en) 2006-09-20 2012-06-12 Siltronic Ag Silicon wafer for semiconductor and manufacturing method thereof
US8142885B2 (en) 2006-12-01 2012-03-27 Siltronic Ag Silicon wafer and method for manufacturing the same
EP1928016A1 (en) * 2006-12-01 2008-06-04 Siltronic AG Silicon wafer and method for manufacturing the same
JP2008166721A (en) * 2006-12-07 2008-07-17 Siltronic Ag Silicon wafer and manufacturing method thereof
US8382894B2 (en) 2007-05-02 2013-02-26 Siltronic Ag Process for the preparation of silicon wafer with reduced slip and warpage
WO2008136500A1 (en) 2007-05-02 2008-11-13 Siltronic Ag Silicon wafer and method for manufacturing the same
JP2011155258A (en) * 2009-12-29 2011-08-11 Siltronic Ag Silicon wafer and production method therefor
CN102148155A (en) * 2009-12-29 2011-08-10 硅电子股份公司 Silicon wafer and production method therefor
US8357939B2 (en) 2009-12-29 2013-01-22 Siltronic Ag Silicon wafer and production method therefor
EP2345753A1 (en) * 2009-12-29 2011-07-20 Siltronic AG Silicon wafer and production method therefor
JP2018046107A (en) * 2016-09-13 2018-03-22 信越半導体株式会社 Method for heat treatment of silicon wafer and method for manufacturing silicon wafer
WO2018051728A1 (en) * 2016-09-13 2018-03-22 信越半導体株式会社 Silicon wafer heat-treatment method and manufacturing method for silicon wafer

Similar Documents

Publication Publication Date Title
US6599815B1 (en) Method and apparatus for forming a silicon wafer with a denuded zone
JPH08213403A (en) Semiconductor substrate and manufacture thereof
JPH09199416A (en) Semiconductor substrate and manufacture thereof
KR100847925B1 (en) Anneal wafer manufacturing method and anneal wafer
WO2010131412A1 (en) Silicon wafer and method for producing the same
JP5097332B2 (en) Method for producing single crystal silicon wafer, silicon wafer of this kind and use thereof
JPH09190954A (en) Semiconductor substrate and its manufacture
JPS60247935A (en) Manufacture of semiconductor wafer
JPH08148552A (en) Semiconductor thermal treatment jig and its surface treatment method
US7659216B2 (en) Method for producing annealed wafer and annealed wafer
JPH10144698A (en) Silicon wafer and its manufacture
JP6848900B2 (en) A method for evaluating the gettering ability of a semiconductor wafer and a method for manufacturing a semiconductor wafer using the evaluation method.
JP2008227060A (en) Method of manufacturing annealed wafer
JPH09199507A (en) Semiconductor substrate and its manufacture
JPH06295913A (en) Manufacture of silicon wafer and silicon wafer
JPS63198334A (en) Manufacture of semiconductor silicon wafer
JPH0521303A (en) Semiconductor substrate and manufacture thereof
JPH0897222A (en) Manufacture of silicon wafer, and silicon wafer
JPH0897221A (en) Manufacture of silicon wafer, and silicon wafer
JP2001102386A (en) Munufacturing method of semiconductor wafer
JPS61135128A (en) Manufacture of semiconductor device
JPH0897220A (en) Manufacture of silicon epitaxial wafer, and silicon epitaxial wafer
JPH04171827A (en) Manufacture of semiconductor device
JPH088263A (en) Semiconductor substrate
JP2022135030A (en) Silicon wafer and manufacturing method for the same