JPS60136218A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPS60136218A
JPS60136218A JP24330883A JP24330883A JPS60136218A JP S60136218 A JPS60136218 A JP S60136218A JP 24330883 A JP24330883 A JP 24330883A JP 24330883 A JP24330883 A JP 24330883A JP S60136218 A JPS60136218 A JP S60136218A
Authority
JP
Japan
Prior art keywords
layer
substrate
defectless
epitaxial layer
defect
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24330883A
Other languages
Japanese (ja)
Inventor
Kenzo Yamanari
山成 謙造
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP24330883A priority Critical patent/JPS60136218A/en
Publication of JPS60136218A publication Critical patent/JPS60136218A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02367Substrates
    • H01L21/0237Materials
    • H01L21/02373Group 14 semiconducting materials
    • H01L21/02381Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/0257Doping during depositing
    • H01L21/02573Conductivity type
    • H01L21/02576N-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)

Abstract

PURPOSE:To improve manufacturing yield and reliability and to contrive a high density by reducing leakage current by generating crystal defects in a semiconductor substrate and forming a defectless layer on a surface of the substrate and forming semiconductor elements in an epitaxial layer arranged in the defectless layer. CONSTITUTION:After treating an N type Si substrate 1 with high temperature, a low temperature treatment is performed step by step to generate a plurality of crystal defects 3 inside the Si substrate. At this time, a defectless layer 2 of about 3 pieces/cm<-2> or less is formed on a surface of the Si substrate 1 by IG effect. Oxygen concentration is desirably reduced to about 1-5X10<17>cm<-3> in a surface defectless layer after performing the heat treatment even if it is of about 16X10<17>cm<-3> in the Si substrate at the beginning. Next, an N type epitaxial layer 5 is formed on the defectless layer 2. The epitaxial layer 5 does not include oxygen so that minute defects caused by oxygen as in the Si substrate 1 are not generated and the layer becomes a defectless layer. Next, after solid state image pick-up element are formed in the epitaxial layer 5, a solid state image pick-up device is completed according to a common method.

Description

【発明の詳細な説明】 〔発明の属する技術分野〕 本発明はリーク電流の極めて少ない半導体装置およびそ
の製造方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention relates to a semiconductor device with extremely low leakage current and a method for manufacturing the same.

半導体基板の表面やエピタキシアル層の活性領域に発生
する微小欠陥はデバイスの電気特性を悪化させることは
よく知られており、との微小欠陥を効果的に抑制するこ
とが半導体素子の歩留シ向上につながっている。
It is well known that micro-defects that occur on the surface of semiconductor substrates and in the active region of epitaxial layers deteriorate the electrical characteristics of devices, and effectively suppressing micro-defects is a key factor in the yield rate of semiconductor devices. This leads to improvement.

この微小欠陥を発生させる主な原因としては半導体基板
(以下シリコン基板について説明する)中に存在する転
移、積層欠陥等の結晶欠陥と、素子の製造工程中に発生
する重金属元素による汚染が考えられておシ、種々の抑
制方法、いわゆるゲッタリング方法が半導体装置の製造
工程に導入されている。
The main causes of these microdefects are believed to be crystal defects such as dislocations and stacking faults existing in the semiconductor substrate (silicon substrate will be explained below) and contamination by heavy metal elements generated during the device manufacturing process. In addition, various suppression methods, so-called gettering methods, have been introduced into the manufacturing process of semiconductor devices.

従来知られているゲッタリング方法としては、(1)サ
ンドブラスト法等によシ機械的に高密度の欠陥をシリコ
ン基板の裏面に形成する方法、(2)高濃度のリンある
いはホウ素等の不純物をシリコン基板の不要部分に拡散
する方法、(3)イオン注入によυ高密度の欠陥をシリ
コン基板の不要部分に形成する方法、(4)シリコン基
板内部の結晶欠陥を利用したイントリンシックゲッタリ
ング効果(以下IG効果という)を用いる方法、が一般
的であシ、これらの方法によシ微小欠陥の抑制という目
的はある程度達成されている。
Conventionally known gettering methods include (1) mechanically forming high-density defects on the back surface of a silicon substrate by sandblasting, etc., and (2) applying impurities such as high concentrations of phosphorus or boron. (3) Method of forming υ high-density defects in unnecessary parts of a silicon substrate by ion implantation; (4) Intrinsic gettering effect using crystal defects inside a silicon substrate (hereinafter referred to as the IG effect) are common, and the purpose of suppressing micro defects has been achieved to some extent by these methods.

しかしながら、最近の半導体デバイスの高密度化、結晶
の大口径化、高品質化、低価格化等の要求からシリコン
基板の活性領域中の微小欠陥の抑制はますます重要とな
ってきている。特に最近開発が進められている固体撮像
装置においては、広いチップ面積中に多数の絵素を高密
度に形成する必要があシ、1個の微小欠陥でも絵素中に
存在する場合はリーク電流が発生し自きす不良の原因と
なる。このため活性領域に欠陥のない高品質のシリコン
基板が要求されているが、第1図(al、 (b)に示
すように、従来のゲッタリング方法を用いた半導体の製
造方法においては活性領域から微小欠陥を完全に除去す
るまでには至っていない、すなわち、第1図(a)に示
すようにCz法で製造したシリコン基板1を1200°
03時間の高温処理後550℃〜800℃30時間の低
温処理を行なうと内部に多数の結晶欠陥3が発生すると
共に、シリコン基板10表面にはIG効果によシ無欠陥
層2が形成される。しかしながら、この表面の無欠陥層
2に半導体素子を形成した場合は第1図(b)に示すよ
うに活性領域4には製造工程中に発生したわずかな微小
欠陥3′が認められた。
However, due to recent demands for higher density semiconductor devices, larger diameter crystals, higher quality, lower prices, etc., it has become increasingly important to suppress micro defects in the active region of a silicon substrate. In particular, in solid-state imaging devices, which are being developed recently, it is necessary to form a large number of picture elements at high density in a large chip area, and if even one microscopic defect exists in a picture element, leakage current will occur. occurs, causing a defective surface. For this reason, a high-quality silicon substrate with no defects in the active region is required. However, as shown in Figure 1 (al) and (b), in the semiconductor manufacturing method using the conventional gettering method, the active region In other words, as shown in FIG. 1(a), the silicon substrate 1 manufactured by the Cz method is heated at 1200 degrees.
When low-temperature treatment is performed for 30 hours at 550° C. to 800° C. after 3 hours of high-temperature treatment, many crystal defects 3 are generated inside the silicon substrate 10, and a defect-free layer 2 is formed on the surface of the silicon substrate 10 due to the IG effect. . However, when a semiconductor element was formed in the defect-free layer 2 on the surface, a few minute defects 3' generated during the manufacturing process were observed in the active region 4, as shown in FIG. 1(b).

また第2図(a)に示すように、シリコン基板1上に欠
陥のないエピタキシアル層5を形成したのち。
Further, as shown in FIG. 2(a), after forming a defect-free epitaxial layer 5 on the silicon substrate 1.

このエピタキシアル層5に半導体素子を形成した場合に
おいても、第2図(b)に示されるように活性領域6に
はわずかな微小欠陥3′が発生していた。
Even when a semiconductor element was formed in this epitaxial layer 5, a few minute defects 3' were generated in the active region 6, as shown in FIG. 2(b).

このように、従来の半導体装置製造方法に2いては、活
性領域を所期の目的とする欠陥レベル以下のものとする
ことができないため良好な電気特性を有する半導体装置
、特に固体撮像装置が歩留シよ〈得られないという欠点
があった。
As described above, in the conventional semiconductor device manufacturing method 2, it is not possible to reduce the active region to a defect level below the desired level, so it is difficult to manufacture semiconductor devices with good electrical characteristics, especially solid-state imaging devices. Rushi, there was a drawback of not being able to obtain it.

〔発明の目的〕[Purpose of the invention]

本発明の目的は、上記欠点を除去し、無欠陥層を有する
半導体表面にエピタキシアル層を形成し、このエピタキ
シアル層に半導体素子を形成することによシリーク電流
が極めて少なく、製造歩留シ、信頼性等の改善された高
密度の半導体装置およびその製造方法を提供することに
ある。
An object of the present invention is to eliminate the above-mentioned drawbacks, form an epitaxial layer on a semiconductor surface having a defect-free layer, and form a semiconductor element on this epitaxial layer, thereby reducing leakage current to an extremely low level and improving manufacturing yield. An object of the present invention is to provide a high-density semiconductor device with improved reliability and a method for manufacturing the same.

〔発明の構成〕[Structure of the invention]

本発明の半導体装置は、表面に無欠陥層を有する半導体
基板と、該半導体基板の無欠陥層上に形成されたエピタ
キシアル層と、該エピタキシアル層に設けられた半導体
素子とを含んで構成される。
A semiconductor device of the present invention includes a semiconductor substrate having a defect-free layer on its surface, an epitaxial layer formed on the defect-free layer of the semiconductor substrate, and a semiconductor element provided on the epitaxial layer. be done.

また、本発明の半導体装置の製造方法は、半導体基板内
に結晶欠陥を形成する工程と、前記半導体基板を熱処理
しその表面に無欠陥層を形成する工程と、前記半導体基
板の無欠陥層上にエピタキシアル層を形成する工程とを
含んで構成される。
Further, the method for manufacturing a semiconductor device of the present invention includes a step of forming crystal defects in a semiconductor substrate, a step of heat-treating the semiconductor substrate to form a defect-free layer on the surface thereof, and a step of forming a defect-free layer on the surface of the semiconductor substrate. and forming an epitaxial layer.

〔実施例の説明〕[Explanation of Examples]

次に、本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.

第3図(a)〜(C)は本発明の一実施例を説明するた
めの主要工程における断面図である。
FIGS. 3(a) to 3(C) are cross-sectional views of main steps for explaining an embodiment of the present invention.

まず、第3図(a)に示すようにC2法によシ製造され
たN型シリコン基板1を1200℃3時間の高温処理を
行ったのち、段階的に550°C〜750℃で3θ時間
の低温処理を行ないシリコン基板1の内部に多数の結晶
欠陥3を発生させる。この時、シリコン基板lの表面に
はIG効果により3ケス−2程度以下の無欠陥層2が形
成される。
First, as shown in FIG. 3(a), an N-type silicon substrate 1 manufactured by the C2 method was subjected to high temperature treatment at 1200°C for 3 hours, and then heated in stages at 550°C to 750°C for 3θ hours. A large number of crystal defects 3 are generated inside the silicon substrate 1 by performing the low temperature treatment. At this time, a defect-free layer 2 of about 3 cass-2 or less is formed on the surface of the silicon substrate 1 due to the IG effect.

酸素濃度は初期のシリコン基板において16×3 101′IcIrL 程度のものであっても該熱処理を
行った後の表面無欠陥層においては1〜5 X 101
7crrc−”程度に減少していることが望ましい。
Even if the oxygen concentration is about 16 x 3 101'IcIrL in the initial silicon substrate, it will be 1 to 5 x 101 in the surface defect-free layer after the heat treatment.
It is desirable that the reduction is about 7crrc-''.

次に第3図(b)に示すように、無欠陥層2上に厚さ約
35μmのN型エビタキ7つ゛ル層5を形成する。この
エピタキシアル層5には酸素が含まれないためシリコン
基板1内のように酸素に起因する微小欠陥は発生しない
ため無欠陥層となる。
Next, as shown in FIG. 3(b), on the defect-free layer 2, a layer 5 with seven N-type layers 5 having a thickness of about 35 μm is formed. Since this epitaxial layer 5 does not contain oxygen, minute defects caused by oxygen do not occur as in the silicon substrate 1, so that it becomes a defect-free layer.

次に第3図(C)に示すように、エピタキシアル層5に
固体撮像素子を形成後常法に従って固体撮像装置を完成
させる。然るときは無欠陥層2にはわずかな微小欠陥3
′が発生する場合もあるが、固体撮像素子が形成された
エピタキシアル層の活性領域6内には微小欠陥は認めら
れない。これはシリコン基板1内の結晶欠陥によるIG
効果によるためである。
Next, as shown in FIG. 3(C), a solid-state imaging device is formed on the epitaxial layer 5, and then a solid-state imaging device is completed according to a conventional method. In such a case, there are only a few minute defects 3 in the defect-free layer 2.
' may occur, but no microdefects are observed in the active region 6 of the epitaxial layer in which the solid-state imaging device is formed. This is caused by IG due to crystal defects in the silicon substrate 1.
This is due to the effect.

このように本発明0製造方法によれば、半導体素子が形
成きれる活性領域は、シリコン基板中に形成された結晶
欠陥によるIG効果と、シリコン基板表面に形成された
無欠陥層による欠陥移転の阻止効果とによシ、無欠陥状
態が保たれるため、半導体装置のリーク電流は極めて少
ないものとなる。
As described above, according to the manufacturing method of the present invention, the active region in which a semiconductor element can be formed is formed by the IG effect due to crystal defects formed in the silicon substrate and by the prevention of defect transfer by the defect-free layer formed on the surface of the silicon substrate. In addition to the effects, since a defect-free state is maintained, the leakage current of the semiconductor device becomes extremely small.

〔発明の効果〕〔Effect of the invention〕

以上詳細に説明したように、本発明によれば、半導体基
板内に結晶欠陥を発生させてその表面に無欠陥層を形成
し、この無欠陥層上に設けたエピタキシアル層に半導体
素子を形成することによシリーク電流が極めて少なく、
製造歩留シ、信頼性等の改善された高密度の半導体装置
およびその製造方法が得られるのでその効果は大きい。
As explained in detail above, according to the present invention, crystal defects are generated in a semiconductor substrate to form a defect-free layer on the surface thereof, and a semiconductor element is formed in an epitaxial layer provided on the defect-free layer. By doing so, the leakage current is extremely low.
The effect is great because a high-density semiconductor device and its manufacturing method with improved manufacturing yield, reliability, etc. can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は従来の半導体装置の製造方法を説明
するための断面図、第3図は本発明の一実施例を説明す
るだめの工程断面図である。 l・・・・・・シリコン基板、2・・・・・・無欠陥層
、3・川・・結晶欠陥、3′・・・・・・微小欠陥、4
・・・・・・活性領域、5・・・・・・エピタキシアル
層、6・・・・・・活性領域。 篤 7 図 躬 3 図
1 and 2 are cross-sectional views for explaining a conventional method of manufacturing a semiconductor device, and FIG. 3 is a process cross-sectional view for explaining an embodiment of the present invention. l... Silicon substrate, 2... Defect-free layer, 3... Crystal defect, 3'... Micro defect, 4
... Active region, 5 ... Epitaxial layer, 6 ... Active region. Atsushi 7 Illustration 3 Illustration

Claims (2)

【特許請求の範囲】[Claims] (1)表面に無欠陥層を有する半導体基板と、該半導体
基板の無欠陥層上に形成されたエピタキシアル層と、該
エピタキシアル層に設けら糺た半導体素子とを含むこと
を特徴とする半導体装置。
(1) A semiconductor substrate having a defect-free layer on its surface, an epitaxial layer formed on the defect-free layer of the semiconductor substrate, and a semiconductor element bonded to the epitaxial layer. Semiconductor equipment.
(2)半導体基板内に結晶欠陥を形成する工程と、前記
半導体基板を熱処理しその表面に無欠陥層を形成する工
程と、前記半導体基板の無欠陥層上にエピタキシアル層
を形成する工程とを含むととを特徴とする半導体装置の
製造方法。
(2) a step of forming crystal defects in a semiconductor substrate; a step of heat-treating the semiconductor substrate to form a defect-free layer on its surface; and a step of forming an epitaxial layer on the defect-free layer of the semiconductor substrate. A method of manufacturing a semiconductor device, comprising:
JP24330883A 1983-12-23 1983-12-23 Semiconductor device and manufacture thereof Pending JPS60136218A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24330883A JPS60136218A (en) 1983-12-23 1983-12-23 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24330883A JPS60136218A (en) 1983-12-23 1983-12-23 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPS60136218A true JPS60136218A (en) 1985-07-19

Family

ID=17101898

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24330883A Pending JPS60136218A (en) 1983-12-23 1983-12-23 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPS60136218A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62131566A (en) * 1985-12-03 1987-06-13 Matsushita Electronics Corp Solid-state image pickup device
US5327007A (en) * 1991-11-18 1994-07-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor substrate having a gettering layer
US5923071A (en) * 1992-06-12 1999-07-13 Seiko Instruments Inc. Semiconductor device having a semiconductor film of low oxygen concentration
JP2004224694A (en) * 1998-10-14 2004-08-12 Memc Electron Materials Inc Epitaxial silicon wafer not substantially having crystal growth transfer defect
KR100622622B1 (en) * 1998-05-22 2006-09-11 신에쯔 한도타이 가부시키가이샤 A method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer
WO2013105179A1 (en) * 2012-01-11 2013-07-18 信越半導体株式会社 Silicon single crystal wafer manufacturing method and electronic device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167335A (en) * 1980-05-29 1981-12-23 Nec Corp Manufacture of semiconductor device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56167335A (en) * 1980-05-29 1981-12-23 Nec Corp Manufacture of semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0715981B2 (en) * 1985-12-03 1995-02-22 松下電子工業株式会社 Solid-state imaging device
JPS62131566A (en) * 1985-12-03 1987-06-13 Matsushita Electronics Corp Solid-state image pickup device
US5327007A (en) * 1991-11-18 1994-07-05 Mitsubishi Denki Kabushiki Kaisha Semiconductor substrate having a gettering layer
US5539245A (en) * 1991-11-18 1996-07-23 Mitsubishi Materials Silicon Corporation Semiconductor substrate having a gettering layer
US5923071A (en) * 1992-06-12 1999-07-13 Seiko Instruments Inc. Semiconductor device having a semiconductor film of low oxygen concentration
US6100570A (en) * 1992-06-12 2000-08-08 Seiko Instruments Inc. Semiconductor device having a semiconductor film of low oxygen concentration
KR100622622B1 (en) * 1998-05-22 2006-09-11 신에쯔 한도타이 가부시키가이샤 A method for producing an epitaxial silicon single crystal wafer and the epitaxial silicon single crystal wafer
JP2004224694A (en) * 1998-10-14 2004-08-12 Memc Electron Materials Inc Epitaxial silicon wafer not substantially having crystal growth transfer defect
WO2013105179A1 (en) * 2012-01-11 2013-07-18 信越半導体株式会社 Silicon single crystal wafer manufacturing method and electronic device
JP2013143504A (en) * 2012-01-11 2013-07-22 Shin Etsu Handotai Co Ltd Silicon single crystal wafer manufacturing method and electronic device
CN104040702A (en) * 2012-01-11 2014-09-10 信越半导体株式会社 Silicon single crystal wafer manufacturing method and electronic device
KR20140109945A (en) * 2012-01-11 2014-09-16 신에쯔 한도타이 가부시키가이샤 Silicon single crystal wafer manufacturing method and electronic device
US9252025B2 (en) 2012-01-11 2016-02-02 Shin-Etsu Handotai Co., Ltd. Method for manufacturing silicon single crystal wafer and electronic device

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