JPH0582525A - Simox substrate and manufacture thereof - Google Patents
Simox substrate and manufacture thereofInfo
- Publication number
- JPH0582525A JPH0582525A JP23851391A JP23851391A JPH0582525A JP H0582525 A JPH0582525 A JP H0582525A JP 23851391 A JP23851391 A JP 23851391A JP 23851391 A JP23851391 A JP 23851391A JP H0582525 A JPH0582525 A JP H0582525A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- heat treatment
- single crystal
- silicon single
- oxide film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 89
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 239000013078 crystal Substances 0.000 claims abstract description 52
- 239000001301 oxygen Substances 0.000 claims abstract description 32
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 32
- 238000010438 heat treatment Methods 0.000 claims abstract description 31
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 29
- 238000005247 gettering Methods 0.000 claims abstract description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims abstract description 18
- -1 oxygen ions Chemical class 0.000 claims abstract description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 27
- 230000007547 defect Effects 0.000 claims description 25
- 238000005468 ion implantation Methods 0.000 claims description 18
- 238000001556 precipitation Methods 0.000 claims description 15
- 239000000463 material Substances 0.000 claims description 7
- 230000008021 deposition Effects 0.000 claims description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 2
- 238000005488 sandblasting Methods 0.000 claims description 2
- 241001168730 Simo Species 0.000 claims 1
- 239000010408 film Substances 0.000 description 34
- 230000015572 biosynthetic process Effects 0.000 description 13
- 239000012535 impurity Substances 0.000 description 8
- 239000000356 contaminant Substances 0.000 description 7
- 230000000694 effects Effects 0.000 description 7
- 238000011109 contamination Methods 0.000 description 5
- 239000002244 precipitate Substances 0.000 description 5
- 230000001133 acceleration Effects 0.000 description 4
- 238000009792 diffusion process Methods 0.000 description 4
- 229910001385 heavy metal Inorganic materials 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 3
- 239000010409 thin film Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 239000002344 surface layer Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000010410 layer Substances 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000001953 recrystallisation Methods 0.000 description 1
- 239000013074 reference sample Substances 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000007711 solidification Methods 0.000 description 1
- 230000008023 solidification Effects 0.000 description 1
- 230000006641 stabilisation Effects 0.000 description 1
- 238000011105 stabilization Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Liquid Deposition Of Substances Of Which Semiconductor Devices Are Composed (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体基板及びその製造
方法に関し、特にＳＯＩ（ＳＩＬＩＣＯＮ−ＯＮ−ＩＮ
ＳＵＬＡＴＯＲ）基板の一種のＳＩＭＯＸ（ＳＥＰＡＲ
ＥＴＩＯＮＢＹ ＩＭＰＬＡＮＴＥＤ ＯＸＹＧＥＮ）
基板の構造とその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor substrate and a method for manufacturing the same, and more particularly to SOI (SILICON-ON-IN).
A type of SIMOX (SEPAR)
ETIONBY IMPLANTED OXYGEN)
The present invention relates to a structure of a substrate and a manufacturing method thereof.
【０００２】[0002]
【従来の技術】今日の大規模集積回路は、動作速度の高
速化の要請により種々の改善がなされているが、更に高
速化を図るには、大幅な寄生容量の低減が不可欠とされ
ている。この様な寄生容量の低減には、絶縁物層上にシ
リコン単結晶薄膜を形成し、このシリコン単結晶薄膜を
素子形成領域とするＳＯＩ技術が有望と考えられてい
る。2. Description of the Related Art Today's large-scale integrated circuits have undergone various improvements in response to the demand for higher operating speeds, but in order to achieve even higher speeds, it is essential to significantly reduce parasitic capacitance. . In order to reduce such parasitic capacitance, an SOI technique in which a silicon single crystal thin film is formed on an insulating layer and the silicon single crystal thin film is used as an element formation region is considered to be promising.
【０００３】ＳＩＭＯＸ基板は、この様なＳＯＩ基板の
一種であり、例えば、吉野明他により、電子情報通信学
会，技術研究報告，ＳＤＭ８７−３９，７３ページ，１
９８７年に報告されている。これは図１１に示すよう
に、シリコン単結晶基板２１全面に酸素をイオン注入し
た後１２００℃以上の高温熱処理を施して埋め込み酸化
膜２３とし、ＳＯＩ構造としたものである。ＳＩＭＯＸ
基板は、大面積で且つ結晶性の良好な素子形成領域２２
を容易に得る事ができるため、最も有望なＳＯＩ基板の
ひとつと考えられている。The SIMOX substrate is a kind of such an SOI substrate, and for example, by Akira Yoshino et al., IEICE, Technical Research Report, SDM 87-39, page 73, 1.
It was reported in 987. As shown in FIG. 11, this is one in which oxygen is ion-implanted into the entire surface of the silicon single crystal substrate 21 and then a high temperature heat treatment of 1200 ° C. or higher is applied to form a buried oxide film 23, which has an SOI structure. SIMOX
The substrate is an element formation region 22 having a large area and good crystallinity.
Therefore, it is considered to be one of the most promising SOI substrates.
【０００４】[0004]
【発明が解決しようとする課題】従来のＳＩＭＯＸ基板
は、埋め込み酸化膜がシリコン単結晶基板全面にわたっ
て形成されるため、素子形成領域を汚染する重金属等の
不純物を除去するゲッタリング技術の応用が困難という
問題があった。In the conventional SIMOX substrate, since the buried oxide film is formed over the entire surface of the silicon single crystal substrate, it is difficult to apply the gettering technique for removing impurities such as heavy metals contaminating the element formation region. There was a problem.
【０００５】ゲッタリングとは、素子形成領域以外に結
晶欠陥等のゲッタリングサイトを形成し、これに汚染不
純物を捕獲，固着する技術であり、通常、このゲッタリ
ングサイトはシリコン単結晶基板の裏面もしくはバルク
に形成される。従って、基板表面（素子形成領域）に付
着し取り込まれた汚染不純物を、付着した部位からゲッ
タリングサイトまで拡散させる必要がある。しかしなが
ら、ＳＩＭＯＸ基板では素子形成領域と基板バルクもし
くは基板裏面との間にシリコン酸化膜が存在するため、
汚染不純物の拡散が著しく妨げられる。これは、一般的
な不純物の拡散係数が、シリコン酸化膜中ではシリコン
単結晶中より極めて小さい値をとることによる。（例え
ば、９００℃におけるシリコン酸化膜中の金の拡散係数
は、シリコン単結晶中の拡散係数の１０-7以下となる。Gettering is a technique for forming a gettering site such as a crystal defect in a region other than the element formation region and capturing and fixing contaminant impurities in the gettering site. Usually, the gettering site is the back surface of the silicon single crystal substrate. Alternatively, it is formed in bulk. Therefore, it is necessary to diffuse the contaminant impurities adhering to and taken in on the substrate surface (element forming region) from the adhering portion to the gettering site. However, in the SIMOX substrate, since the silicon oxide film exists between the element forming region and the substrate bulk or the back surface of the substrate,
Diffusion of contaminant impurities is significantly hindered. This is because the diffusion coefficient of general impurities takes a value extremely smaller in the silicon oxide film than in the silicon single crystal. (For example, the diffusion coefficient of gold in a silicon oxide film at 900 ° C. is 10 −7 or less of the diffusion coefficient in a silicon single crystal.
【０００６】以上の様に、ＳＩＭＯＸ基板ではゲッタリ
ング技術の適用が困難であり、素子形成領域に汚染不純
物が残留しやすく、これらの汚染不純物による素子特性
（接合リーク、耐圧）の劣化が生じやすい。As described above, it is difficult to apply the gettering technique to the SIMOX substrate, contaminant impurities are likely to remain in the element formation region, and the element characteristics (junction leakage, breakdown voltage) are likely to be deteriorated by these contaminant impurities. ..
【０００７】[0007]
【課題を解決するための手段】本発明のＳＩＭＯＸ基板
は、部分的に埋め込み酸化膜が形成されない領域を有
し、且つ、基板バルクもしくは基板裏面は何らかのゲッ
タリング手段が付与された構造となっている事を特徴と
している。The SIMOX substrate of the present invention has a structure in which a buried oxide film is not partially formed and the substrate bulk or the back surface of the substrate is provided with some gettering means. It is characterized by being.
【０００８】この構造を実現するため、シリコン単結晶
基板表面に酸素イオンの注入を遮蔽するマスク材を部分
的に配して酸素イオンを注入し、高温熱処理を行った後
に何らかのゲッタリング手段を基板裏面もしくは基板バ
ルクに付与する工程をとる。In order to realize this structure, a mask material for blocking the implantation of oxygen ions is partially arranged on the surface of the silicon single crystal substrate, oxygen ions are implanted, and high temperature heat treatment is performed, and then some gettering means is provided on the substrate. Take the step of applying to the back surface or bulk of the substrate.
【０００９】[0009]
【作用】上述のように、部分的に埋め込み酸化膜の無い
領域を設ける事により、素子形成領域となる基板表面と
ゲッタリングサイトを有する基板バルクもしくは基板裏
面とが単結晶シリコンのみでつながるため、素子形成領
域に付着した重金属等の汚染原子は容易にゲッタリング
サイトまで拡散する事が可能となる。As described above, by providing a region without a buried oxide film in part, the substrate surface to be the element formation region and the substrate bulk having the gettering site or the substrate back surface are connected by only single crystal silicon. Contaminant atoms such as heavy metals attached to the element formation region can easily diffuse to the gettering site.
【００１０】[0010]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１１】図１は本発明の第１の実施例におけるＳＩ
ＭＯＸ基板構造の縦断面概略図である。シリコン単結晶
基板１の表面には、素子形成領域２が形成される。素子
形成領域２の直下には、酸素イオン注入と高温熱処理で
形成された埋め込みシリコン酸化膜３がある。この埋め
込みシリコン酸化膜３には所望の位置に貫通孔４が設け
られており、素子形成領域２は、この貫通孔４を介して
基板バルク５と単結晶シリコンでつながれている。基板
１裏面には、ゲッタリングサイトとなる結晶欠陥もしく
は結晶歪６が導入されている。これは、一般に、ＥＧ
（ＥＸＴＲＩＮＳＩＣ ＧＥＴＴＥＲＩＮＧ）と称され
る手法で採用される欠陥導入法（例えば、サンドブラス
トによる機械的損傷，レーザ照射による溶融・固化，希
ガス等のイオン注入，多結晶シリコン膜の堆積等）がと
られていれば良い。FIG. 1 shows the SI in the first embodiment of the present invention.
It is a vertical cross-sectional schematic diagram of a MOX substrate structure. An element formation region 2 is formed on the surface of the silicon single crystal substrate 1. Immediately below the element formation region 2 is a buried silicon oxide film 3 formed by oxygen ion implantation and high temperature heat treatment. The buried silicon oxide film 3 is provided with a through hole 4 at a desired position, and the element forming region 2 is connected to the substrate bulk 5 with single crystal silicon through the through hole 4. On the back surface of the substrate 1, crystal defects or crystal strains 6 which become gettering sites are introduced. This is generally
The defect introduction method adopted by the method called (EXTRINSIC GETTERING) (for example, mechanical damage by sandblasting, melting / solidification by laser irradiation, ion implantation of rare gas, deposition of polycrystalline silicon film, etc.) is adopted. It's fine.
【００１２】図２は、本実施例の構造を実現するための
製造工程を示す縦断面概略図である。FIG. 2 is a schematic vertical sectional view showing a manufacturing process for realizing the structure of this embodiment.
【００１３】まず、図２（ａ）に示すように、シリコン
単結晶基板１上にシリコン酸化膜を形成し、通常の光リ
ソグラフィー技術を用いて所望の形状のシリコン酸化膜
マスク７を形成する。この時、シリコン酸化膜の厚さ
は、後の工程でイオン注入される酸素の注入深さを考慮
し、シリコン酸化膜マスク７が充分な酸素の遮蔽効果を
有する様に設定される。例えば、酸素のイオン注入が加
速エネルギー１８０ｋｅＶ，ドーズ量１．５×１０18／
ｃｍ2 で行われる場合、厚さは１μｍ程度あればよい。
また、シリコン酸化膜マスク７の形状は、後に素子が形
成されない領域（例えば、スクライブ線領域あるいは素
子分離領域）に対応する形状とする。First, as shown in FIG. 2A, a silicon oxide film is formed on a silicon single crystal substrate 1, and a silicon oxide film mask 7 having a desired shape is formed by using a normal photolithography technique. At this time, the thickness of the silicon oxide film is set so that the silicon oxide film mask 7 has a sufficient oxygen shielding effect in consideration of the implantation depth of oxygen ion-implanted in a later step. For example, oxygen ion implantation has an acceleration energy of 180 keV and a dose amount of 1.5 × 10 18 /
When it is performed in cm 2 , the thickness may be about 1 μm.
The shape of the silicon oxide film mask 7 is a shape corresponding to a region (for example, a scribe line region or an element isolation region) where an element will not be formed later.
【００１４】次に、図２（ｂ）に示すように、高加速エ
ネルギー・高ドーズ量で酸素をイオン注入（例えば加速
エネルギー１８０ｋｅＶ，ドーズ量１．５×１０18／ｃ
ｍ2 ）し、埋め込み酸化膜３を形成する。この時、シリ
コン酸化膜マスク７の直下には酸素は注入されない。続
いて、図２（ｃ）に示すようにシリコン酸化膜マスク７
を除去し、一般にＳＩＭＯＸ基板製造で行われる高温熱
処理（例えば、１２５０℃，２時間程度）を施し、イオ
ン注入により非晶質化した表面層の再結晶化，イオン注
入による結晶欠陥の除去，埋め込み酸化膜３の安定化を
行う。Next, as shown in FIG. 2B, oxygen is ion-implanted at a high acceleration energy and a high dose amount (for example, acceleration energy 180 keV, dose amount 1.5 × 10 18 / c).
m 2 ), and the buried oxide film 3 is formed. At this time, oxygen is not injected just below the silicon oxide film mask 7. Then, as shown in FIG. 2C, the silicon oxide film mask 7 is formed.
Is removed, and high temperature heat treatment (for example, about 1250 ° C. for about 2 hours) generally performed in SIMOX substrate manufacturing is performed to recrystallize the surface layer made amorphous by ion implantation, remove crystal defects by ion implantation, and embed. The oxide film 3 is stabilized.
【００１５】最後に、図２（ｄ）に示すように、基板１
裏面にレーザ照射（例えば、５Ｊ／ｃｍ2 程度のエネル
ギー密度のエキシマレーザ照射）を行い、基板１裏面の
みに結晶欠陥もしくは結晶歪６を導入し、ゲッタリング
サイトとする。Finally, as shown in FIG. 2D, the substrate 1
Laser irradiation (for example, excimer laser irradiation with an energy density of about 5 J / cm 2 ) is performed on the back surface to introduce crystal defects or crystal strain 6 only on the back surface of the substrate 1 to form gettering sites.
【００１６】なお、本実施例では、基板裏面への結晶欠
陥導入にレーザ照射を用いたが、他にイオン注入，サン
ドブラスト等のＥＧ技術として適用可能な手法であれば
いかなる方法でもよく、欠陥密度は１０2 〜１０6 個／
ｃｍ2 の範囲が望ましい。１０2 個／ｃｍ2 未満では、
図３に示すように、ゲッタリング効果が小さく、素子形
成領域２である基板表面の汚染起因結晶欠陥の発生を充
分に抑制できない。また１０6 個／ｃｍ2 を越える値で
は、図４に示すように、基板１全体が塑性変形し大きく
反ってしまう。In this embodiment, laser irradiation was used to introduce crystal defects into the back surface of the substrate. However, any other method that can be applied as an EG technique such as ion implantation and sandblast may be used, and the defect density 10 2 to 10 6 pieces /
A range of cm 2 is desirable. Below 10 2 pieces / cm 2 ,
As shown in FIG. 3, the gettering effect is small, and it is not possible to sufficiently suppress the occurrence of crystal defects due to contamination on the substrate surface which is the element forming region 2. On the other hand, when the value exceeds 10 6 / cm 2 , the entire substrate 1 is plastically deformed and largely warped as shown in FIG.
【００１７】図５は本発明の第２の実施例におけるＳＩ
ＭＯＸ基板構造の縦断面概略図である。素子形成領域２
の直下には、酸素イオン注入と高温熱処理で形成された
埋め込みシリコン酸化膜３がある。この埋め込みシリコ
ン酸化膜３には所望の位置に貫通孔４が設けられてお
り、素子形成領域２は、この貫通孔４を介して基板バル
ク１５と単結晶シリコンでつながれている。基板バルク
１５には、格子間酸素の析出核もしくは析出物８が形成
されている。これらの析出核もしくは析出物８は結晶欠
陥（転位，積層欠陥）を発生させる作用を有する。これ
らの結晶欠陥は、一般にＩＧ（ＩＮＴＲＩＮＳＩＣ Ｇ
ＥＴＴＥＲＩＮＧ）と称されるゲッタリング技術におい
てゲッタリングサイトの役割を果たすものである。FIG. 5 shows the SI in the second embodiment of the present invention.
It is a vertical cross-sectional schematic diagram of a MOX substrate structure. Element formation area 2
Immediately below is a buried silicon oxide film 3 formed by oxygen ion implantation and high temperature heat treatment. The buried silicon oxide film 3 is provided with a through hole 4 at a desired position, and the element forming region 2 is connected to the substrate bulk 15 with single crystal silicon through the through hole 4. Interstitial oxygen precipitation nuclei or precipitates 8 are formed on the substrate bulk 15. These precipitation nuclei or precipitates 8 have a function of generating crystal defects (dislocations, stacking faults). These crystal defects are generally caused by IG (INTRINSIC G
It plays a role of a gettering site in a gettering technology called ETTERING).
【００１８】図６は、本実施例の構造を実現するための
製造工程を示す縦断面概略図である。FIG. 6 is a schematic vertical sectional view showing a manufacturing process for realizing the structure of this embodiment.
【００１９】まず、図６（ａ）に示すように、チョクラ
ルスキー法により製造され、格子間酸素を含有するシリ
コン単結晶基板（ＣＺ基板）１１上にシリコン酸化膜を
形成し、通常の光リソグラフィー技術を用いて所望の形
状のシリコン酸化膜マスク７を形成する。シリコン酸化
膜マスク７の形状は、後に素子が形成されない領域に対
応する形状とする。First, as shown in FIG. 6A, a silicon oxide film is formed on a silicon single crystal substrate (CZ substrate) 11 which is manufactured by the Czochralski method and contains interstitial oxygen. A silicon oxide film mask 7 having a desired shape is formed by using a lithography technique. The silicon oxide film mask 7 has a shape corresponding to a region where an element will not be formed later.
【００２０】次に、図６（ｂ）に示すように、高加速エ
ネルギー・高ドーズ量でイオン注入し、埋め込み酸化膜
３を形成する。この時、シリコン酸化膜マスク７の直下
には酸素は注入されない。Next, as shown in FIG. 6B, ion implantation is performed with high acceleration energy and high dose to form a buried oxide film 3. At this time, oxygen is not injected just below the silicon oxide film mask 7.
【００２１】続いて、図６（ｃ）に示すように、シリコ
ン酸化膜マスク７を除去し、１２５０℃／３時間の高温
熱処理を施し、イオン注入により非晶質化した表面層の
再結晶化，イオン注入による結晶欠陥の除去，埋め込み
シリコン酸化膜３の安定化を行うと共に、ＣＺ基板１１
の表面及び裏面から格子間酸素を基板１１外へと外方拡
散させる。この高温熱処理は、一般にＳＩＭＯＸ基板製
造において採用されている１２００〜１３５０℃／１〜
１０時間程度でよく、イオン注入による結晶欠陥の除去
が充分達成出来る条件であれば特に制約はない。Subsequently, as shown in FIG. 6C, the silicon oxide film mask 7 is removed, high temperature heat treatment is performed at 1250 ° C. for 3 hours, and recrystallization of the surface layer amorphized by ion implantation is performed. , Removal of crystal defects by ion implantation, stabilization of the buried silicon oxide film 3, and CZ substrate 11
Interstitial oxygen is diffused out of the substrate 11 from the front and back surfaces of the substrate. This high-temperature heat treatment is performed at 1200 to 1350 ° C./1 to which is generally adopted in SIMOX substrate manufacturing.
It may be about 10 hours, and there is no particular limitation as long as it is a condition that the removal of crystal defects by ion implantation can be sufficiently achieved.
【００２２】次いで、７００℃の第１熱処理により、図
６（ｄ）に示すように、基板バルク１５に格子間酸素の
析出核８ａを形成する。第１熱処理は５００〜９００℃
の範囲で行われる事が望ましい。これは、図７に示すよ
うに、おもにこの温度範囲のみで析出核の発生・成長が
おこることによる。第１熱処理の時間について時に制約
はないが、先述の埋め込み酸化膜形成のための高温熱処
理と第１熱処理の組合せで析出核の密度が１０6 〜１０
9 個／ｃｃの範囲になる様調整される事が望ましい。こ
れは図８に示すように、１０6 個／ｃｃ未満では、ゲッ
タリング効果が小さく、素子形成領域である基板表面の
汚染起因結晶欠陥の発生を充分に抑制できない。また１
０9 個／ｃｃを越える値では、図９に示すように、基板
１１全体が塑性変形し大きく反ってしまうことになる。Next, as shown in FIG. 6D, interstitial oxygen precipitation nuclei 8a are formed in the substrate bulk 15 by the first heat treatment at 700.degree. The first heat treatment is 500-900 ° C
It is desirable to be carried out in the range of. This is mainly due to the generation and growth of precipitation nuclei only in this temperature range, as shown in FIG. Although there is no restriction on the time of the first heat treatment, the density of precipitation nuclei is 10 6 to 10 6 by the combination of the above-described high temperature heat treatment for forming the buried oxide film and the first heat treatment.
It is desirable to adjust it so that it is within the range of 9 pieces / cc. As shown in FIG. 8, when the number is less than 10 6 / cc, the gettering effect is small and the generation of contamination-induced crystal defects on the substrate surface, which is an element forming region, cannot be sufficiently suppressed. Again 1
When the value exceeds 09 pieces / cc, as shown in FIG. 9, the entire substrate 11 is plastically deformed and largely warped.
【００２３】更に、図６（ｅ）に示すように、１０００
〜１１５０℃の第２熱処理により析出核８ａを、酸素の
析出物８ｂに大きく成長させ、転位，積層欠陥の発生を
安定化させてもよい。処理時間については特に制約はな
いが、あまり長時間の熱処理は、過度の格子間酸素析出
を起して基板の機械的強度が低下し塑性変形しやすくな
る為、図１０に示すように、基板バルクに残存する格子
間酸素濃度が７×１０18原子／ｃｍ3 以上となる様調整
する必要がある。Further, as shown in FIG.
By the second heat treatment at ˜1150 ° C., the precipitation nuclei 8a may be grown to oxygen precipitates 8b to stabilize the generation of dislocations and stacking faults. The treatment time is not particularly limited, but if the heat treatment for a too long time causes excessive interstitial oxygen precipitation, the mechanical strength of the substrate is lowered, and the substrate is easily plastically deformed. Therefore, as shown in FIG. It is necessary to adjust the interstitial oxygen concentration remaining in the bulk to 7 × 10 18 atoms / cm 3 or more.
【００２４】なお、格子間酸素析出は素子製造工程にお
いても生じることから、第２熱処理は省略することも可
能である。Since the interstitial oxygen precipitation also occurs in the element manufacturing process, the second heat treatment can be omitted.
【００２５】上述の２つの実施例では、酸素イオン注入
のマスク材としてシリコン酸化膜を用いたが、酸素イオ
ンに対し充分な遮蔽効果を有するものであれば、材質に
関する制限はなく、シリコン窒化膜、光感光性樹脂、金
属薄膜等、あらゆる材料を選択する事が可能である。In the above-mentioned two embodiments, the silicon oxide film was used as the mask material for oxygen ion implantation, but there is no limitation on the material as long as it has a sufficient shielding effect against oxygen ions, and the silicon nitride film is not limited. It is possible to select any material such as a photosensitive resin, a metal thin film, etc.
【００２６】上述の第１，第２の実施例の様に作製した
ＳＩＭＯＸ基板のゲッタリング効果を検証するため、通
常の従来技術によるＳＩＭＯＸ基板を参照サンプルとし
て、重金属の定量汚染による基板表面の結晶欠陥発生量
の比較実験をおこなった。各々のＳＩＭＯＸ基板に５×
１０12原子／ｃｍ2 の銅及びニッケルを塗布し、１１５
０℃及び１０００℃の２段階熱処理を施した後、一般的
な選択エッチング（ライトエッチ等）手法で表面欠陥密
度を測定した。その結果、本発明の第１，第２の実施例
によるＳＩＭＯＸ基板では０〜〈１０個／ｃｍ2 と表面
欠陥はほとんど認められなかったのに対し、従来技術の
ＳＩＭＯＸ基板では１０5 〜１０6 個／ｃｍ2 のピット
及び積層欠陥が観察された。この結果は、本発明により
ＳＩＭＯＸ基板に高いゲッタリング効果を付与できたこ
とを示すものである。In order to verify the gettering effect of the SIMOX substrate manufactured as in the above-mentioned first and second embodiments, the SIMOX substrate according to the conventional prior art was used as a reference sample and crystals on the substrate surface due to quantitative contamination of heavy metals. A comparative experiment of the amount of defects generated was performed. 5x on each SIMOX substrate
Applying 10 12 atoms / cm 2 of copper and nickel, 115
After the two-step heat treatment at 0 ° C. and 1000 ° C., the surface defect density was measured by a general selective etching (light etching etc.) method. As a result, the SIMOX substrate according to the first and second embodiments of the present invention showed almost no surface defects of 0 to <10 / cm 2 , whereas the SIMOX substrate of the prior art had a surface defect of 10 5 to 10 6. The number of pits / cm 2 and stacking faults were observed. This result shows that the present invention can impart a high gettering effect to the SIMOX substrate.
【００２７】[0027]
【発明の効果】以上説明したように本発明は、埋め込み
シリコン酸化膜を所望の位置に部分的に設け、基板裏面
もしくはバルクに設けたゲッタリングサイトと素子形成
領域とがつながった構造のＳＩＭＯＸ基板及びその製造
方法を提供したものであり、重金属等の汚染不純物の素
子形成領域外への除去を可能にし、ＳＩＭＯＸ基板上に
形成される素子の特性及び製造歩留りを大幅に改善でき
る効果を有する。As described above, the present invention provides a SIMOX substrate having a structure in which a buried silicon oxide film is partially provided at a desired position and a gettering site provided on the back surface or bulk of the substrate and an element formation region are connected. And a method for manufacturing the same, which enables removal of contaminant impurities such as heavy metals to the outside of the element formation region, and has the effect of significantly improving the characteristics and manufacturing yield of elements formed on a SIMOX substrate.
【図１】本発明の第１の実施例の構造を示す縦断面図で
ある。FIG. 1 is a vertical cross-sectional view showing the structure of a first embodiment of the present invention.
【図２】本発明の第１の実施例の製造工程を示す縦断面
概略図である。FIG. 2 is a schematic vertical cross-sectional view showing a manufacturing process of the first embodiment of the present invention.
【図３】本発明の第１の実施例における裏面結晶欠陥密
度と表面の汚染起因結晶欠陥密度との相関を示すグラフ
である。FIG. 3 is a graph showing the correlation between the back surface crystal defect density and the surface contamination-induced crystal defect density in the first example of the present invention.
【図４】本発明の第１の実施例における裏面結晶欠陥密
度と基板の反りとの相関を示すグラフである。FIG. 4 is a graph showing a correlation between back surface crystal defect density and substrate warpage in the first example of the present invention.
【図５】本発明の第２の実施例の構造を示す縦断面概略
図である。FIG. 5 is a schematic vertical sectional view showing the structure of the second embodiment of the present invention.
【図６】本発明の第２の実施例の製造工程を示す縦断面
概略図である。FIG. 6 is a schematic vertical sectional view showing a manufacturing process of the second embodiment of the present invention.
【図７】本発明の第２の実施例における熱処理温度と発
生する析出核密度との相関を示すグラフである。FIG. 7 is a graph showing the correlation between the heat treatment temperature and the generated precipitation nucleus density in the second example of the present invention.
【図８】本発明の第２の実施例における析出核密度と表
面の汚染起因結晶欠陥密度との相関を示すグラフであ
る。FIG. 8 is a graph showing a correlation between a precipitation nucleus density and a surface contamination-induced crystal defect density in the second example of the present invention.
【図９】本発明の第２の実施例における析出核密度と基
板の反りとの相関を示すグラフである。FIG. 9 is a graph showing the correlation between the precipitation nucleus density and the warp of the substrate in the second example of the present invention.
【図１０】本発明の第２の実施例における残存格子間酸
素濃度と基板の反りとの相関を示すグラフである。FIG. 10 is a graph showing a correlation between residual interstitial oxygen concentration and substrate warpage in the second example of the present invention.
【図１１】従来技術によるＳＩＭＯＸ基板の縦断面概略
図である。FIG. 11 is a schematic vertical cross-sectional view of a SIMOX substrate according to the related art.
１，１１，２１ シリコン単結晶基板 ２，２２ 素子形成領域 ３，２３ 埋め込みシリコン酸化膜 ４ 貫通孔 ５，１５ 基板バルク ６ 結晶欠陥もしくは結晶歪 ７ シリコン酸化膜マスク ８ 析出核もしくは析出物 ８ａ 析出核 ８ｂ 析出物 1,11,21 Silicon single crystal substrate 2,22 Element formation region 3,23 Embedded silicon oxide film 4 Through hole 5,15 Substrate bulk 6 Crystal defect or crystal strain 7 Silicon oxide film mask 8 Precipitation nucleus or precipitate 8a Precipitation nucleus 8b precipitate
Claims (8)
ン注入と高温熱処理とにより形成された埋め込みシリコ
ン酸化膜上にシリコン単結晶層を有するＳＩＭＯＸ基板
において、 前記埋め込みシリコン酸化膜が部分的に形成されない領
域を有し、 シリコン単結晶基板バルクもしくはシリコン単結晶基板
裏面に、結晶欠陥もしくは結晶歪によるゲッタリング手
段が付与された構造を有することを特徴とするＳＩＭＯ
Ｘ基板。1. A SIMOX substrate having a silicon single crystal layer on a buried silicon oxide film formed by ion implantation of oxygen into a silicon single crystal substrate and high-temperature heat treatment, wherein a region where the buried silicon oxide film is not partially formed. SIMO having a structure in which gettering means due to a crystal defect or a crystal strain is added to the bulk of the silicon single crystal substrate or the back surface of the silicon single crystal substrate.
X board.
ン注入と高温熱処理により埋め込みシリコン酸化膜と該
埋め込みシリコン酸化膜上にシリコン単結晶層とを形成
するＳＩＭＯＸ基板の製造方法において、 該シリコン単結晶基板の表面の所望の位置に、注入され
る酸素イオンを遮蔽するマスク材を部分的に配置した
後、所望の条件で酸素イオン注入を行う工程と、 前記酸素イオン注入の後、前記マスク材を除去して、前
記高温熱処理を施す工程と、 前記高温熱処理の後、前記シリコン単結晶基板の裏面に
結晶欠陥もしくは結晶歪を導入する工程と、 を含むことを特徴とするＳＩＭＯＸ基板の製造方法。2. A method for manufacturing a SIMOX substrate, wherein a buried silicon oxide film and a silicon single crystal layer are formed on the buried silicon oxide film by ion implantation of oxygen into the silicon single crystal substrate and high-temperature heat treatment. A step of partially arranging a mask material that shields implanted oxygen ions at a desired position on the surface of, and then performing oxygen ion implantation under desired conditions; and after the oxygen ion implantation, removing the mask material And then performing the high temperature heat treatment, and introducing a crystal defect or a crystal strain into the back surface of the silicon single crystal substrate after the high temperature heat treatment.
る前記結晶欠陥もしくは前記結晶歪は、レーザ照射もし
くはイオン注入もしくはサンドブラストもしくは多結晶
シリコン膜堆積によって行われることを特徴とする請求
項２記載のＳＩＭＯＸ基板の製造方法。3. The crystal defect or the crystal strain introduced into the back surface of the silicon single crystal substrate is performed by laser irradiation, ion implantation, sand blasting, or polycrystalline silicon film deposition. Method of manufacturing SIMOX substrate.
を除去して、１２００〜１３５０℃，１〜１０時間の高
温熱処理を施す工程と、 前記高温熱処理の後、５００〜９００℃で第１の熱処理
を施す工程と、 を含むことを特徴とする請求項２，または請求項３記載
のＳＩＭＯＸ基板の製造方法。4. A step of removing the mask material after the oxygen ion implantation and performing a high temperature heat treatment at 1200 to 1350 ° C. for 1 to 10 hours; and a first step at 500 to 900 ° C. after the high temperature heat treatment. The method of manufacturing a SIMOX substrate according to claim 2 or claim 3, further comprising:
５０℃で第２の熱処理を施す工程を含むことを特徴とす
る請求項４記載のＳＩＭＯＸ基板の製造方法。5. After the first heat treatment, 1000 to 11
The method for manufacturing a SIMOX substrate according to claim 4, further comprising a step of performing a second heat treatment at 50 ° C.
の組合せで１０6〜１０9 個／ｃｃの範囲で格子間酸素
の析出核を形成できるよう、その処理時間が調整される
ことを特徴とする請求項４，または請求項５記載のＳＩ
ＭＯＸ基板の製造方法。6. The treatment time of the first heat treatment is adjusted so that precipitation nuclei of interstitial oxygen can be formed in the range of 10 6 to 10 9 pieces / cc in combination with the high temperature heat treatment. SI of Claim 4 or Claim 5 characterized by the above-mentioned.
MOX substrate manufacturing method.
第１の熱処理との組合せで１０6 〜１０9 個／ｃｃの範
囲で格子間酸素の析出核を形成できるよう、その処理時
間が調整されることを特徴とする請求項４，または請求
項５，または請求項６記載のＳＩＭＯＸ基板の製造方
法。7. The treatment time of the second heat treatment is such that a combination of the high temperature heat treatment and the first heat treatment can form interstitial oxygen precipitation nuclei in the range of 10 6 to 10 9 pieces / cc. 7. The method of manufacturing a SIMOX substrate according to claim 4, or claim 5, or claim 6, which is adjusted.
キー法で製造されたシリコン単結晶から製造されている
ことを特徴とする請求項４，請求項５，請求項６，また
は請求項７記載のＳＩＭＯＸ基板の製造方法。8. The silicon single crystal substrate according to claim 4, claim 5, claim 6, or claim 7, wherein the silicon single crystal substrate is manufactured from a silicon single crystal manufactured by the Czochralski method. Method of manufacturing SIMOX substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3238513A JP2998330B2 (en) | 1991-09-19 | 1991-09-19 | SIMOX substrate and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3238513A JP2998330B2 (en) | 1991-09-19 | 1991-09-19 | SIMOX substrate and method of manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0582525A true JPH0582525A (en) | 1993-04-02 |
| JP2998330B2 JP2998330B2 (en) | 2000-01-11 |
Family
ID=17031372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3238513A Expired - Fee Related JP2998330B2 (en) | 1991-09-19 | 1991-09-19 | SIMOX substrate and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2998330B2 (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07193072A (en) * | 1993-12-27 | 1995-07-28 | Nec Corp | Manufacture of semiconductor device |
| US6252294B1 (en) | 1999-05-07 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and semiconductor storage device |
| JP2005079601A (en) * | 2003-09-03 | 2005-03-24 | Internatl Business Mach Corp <Ibm> | SUBSTANTIALLY METASTABLE SiGe LAYER AND MANUFACTURING METHOD THEREFOR |
| US6875643B2 (en) | 2002-12-24 | 2005-04-05 | Sumitomo Mitsubishi Silicon Corporation | SOI substrate and manufacturing method thereof |
| JP2005175151A (en) * | 2003-12-10 | 2005-06-30 | Fuji Electric Holdings Co Ltd | Silicon on insulator wafer, manufacturing method thereof, and manufacturing method of semiconductor device using the same |
| JP2005286282A (en) * | 2004-03-01 | 2005-10-13 | Sumco Corp | Method of manufacturing simox substrate and simox substrate resulting from same |
| EP1122788A4 (en) * | 1999-07-02 | 2006-05-17 | Mitsubishi Material Silicon | Soi substrate, method of manufacture thereof, and semiconductor device using soi substrate |
| JP2007322298A (en) * | 2006-06-02 | 2007-12-13 | Dainippon Printing Co Ltd | Acceleration sensor and its manufacturing method |
| JP2008091935A (en) * | 2007-11-02 | 2008-04-17 | Seiko Instruments Inc | Integrated circuit |
| JP2008270592A (en) * | 2007-04-23 | 2008-11-06 | Shin Etsu Handotai Co Ltd | Manufacturing method of soi substrate |
| US7537989B2 (en) | 2005-11-18 | 2009-05-26 | Sumco Corporation | Method for manufacturing SOI substrate |
| US7943497B2 (en) | 2005-11-18 | 2011-05-17 | Sumco Corporation | Method for manufacturing an SOI substrate |
| US8294282B2 (en) | 2009-09-24 | 2012-10-23 | Kabushiki Kaisha Toshiba | Semiconductor device and adhesive sheet |
-
1991
- 1991-09-19 JP JP3238513A patent/JP2998330B2/en not_active Expired - Fee Related
Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07193072A (en) * | 1993-12-27 | 1995-07-28 | Nec Corp | Manufacture of semiconductor device |
| US6252294B1 (en) | 1999-05-07 | 2001-06-26 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device and semiconductor storage device |
| EP1122788A4 (en) * | 1999-07-02 | 2006-05-17 | Mitsubishi Material Silicon | Soi substrate, method of manufacture thereof, and semiconductor device using soi substrate |
| US6875643B2 (en) | 2002-12-24 | 2005-04-05 | Sumitomo Mitsubishi Silicon Corporation | SOI substrate and manufacturing method thereof |
| JP2005079601A (en) * | 2003-09-03 | 2005-03-24 | Internatl Business Mach Corp <Ibm> | SUBSTANTIALLY METASTABLE SiGe LAYER AND MANUFACTURING METHOD THEREFOR |
| JP4732725B2 (en) * | 2003-09-03 | 2011-07-27 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Substantially metastable SiGe layer and method for forming the same |
| JP2005175151A (en) * | 2003-12-10 | 2005-06-30 | Fuji Electric Holdings Co Ltd | Silicon on insulator wafer, manufacturing method thereof, and manufacturing method of semiconductor device using the same |
| JP2005286282A (en) * | 2004-03-01 | 2005-10-13 | Sumco Corp | Method of manufacturing simox substrate and simox substrate resulting from same |
| US7811878B2 (en) | 2005-11-18 | 2010-10-12 | Sumco Corporation | Method of manufacturing SOI substrate |
| US7537989B2 (en) | 2005-11-18 | 2009-05-26 | Sumco Corporation | Method for manufacturing SOI substrate |
| US7943497B2 (en) | 2005-11-18 | 2011-05-17 | Sumco Corporation | Method for manufacturing an SOI substrate |
| JP2007322298A (en) * | 2006-06-02 | 2007-12-13 | Dainippon Printing Co Ltd | Acceleration sensor and its manufacturing method |
| JP2008270592A (en) * | 2007-04-23 | 2008-11-06 | Shin Etsu Handotai Co Ltd | Manufacturing method of soi substrate |
| US7799660B2 (en) | 2007-04-23 | 2010-09-21 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing SOI substrate |
| JP2008091935A (en) * | 2007-11-02 | 2008-04-17 | Seiko Instruments Inc | Integrated circuit |
| US8294282B2 (en) | 2009-09-24 | 2012-10-23 | Kabushiki Kaisha Toshiba | Semiconductor device and adhesive sheet |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2998330B2 (en) | 2000-01-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100875909B1 (en) | Method for manufacturing SIO wafers and SIO wafers obtained by this method | |
| KR100319413B1 (en) | Method for manufacturing semiconductor silicon epitaxial wafer and semiconductor device | |
| US20080044669A1 (en) | Method for Manufacturing Simox Substrate and Simox Substrate Obtained by the Method | |
| JPS6124240A (en) | Semiconductor substrate | |
| JP2998330B2 (en) | SIMOX substrate and method of manufacturing the same | |
| JP3381816B2 (en) | Semiconductor substrate manufacturing method | |
| JP2005268792A (en) | Method of manufacturing semiconductor device, semiconductor device and apparatus | |
| JPH03108716A (en) | Heat treating method for semiconductor integrated circuit device | |
| JPS6142855B2 (en) | ||
| JP3810168B2 (en) | Manufacturing method of semiconductor substrate | |
| JPH0410544A (en) | Manufacture of semiconductor device | |
| JPH05235005A (en) | Semiconductor substrate and manufacture thereof | |
| JP3638424B2 (en) | Semiconductor device manufacturing method and semiconductor manufacturing apparatus | |
| JP3452122B2 (en) | Method for manufacturing SOI substrate | |
| JP2943369B2 (en) | Semiconductor substrate manufacturing method | |
| JP2005026644A (en) | Soi substrate, semiconductor substrate, and its manufacturing method | |
| JP3583870B2 (en) | Semiconductor substrate and method of manufacturing the same | |
| JPH0590272A (en) | Semiconductor device and manufacture thereof | |
| JPH05152304A (en) | Manufacture of semiconductor substrate | |
| JPH05129309A (en) | Pasted substrate | |
| JP3024193B2 (en) | Semiconductor substrate manufacturing method | |
| JPH03201440A (en) | Formation of rear distortion of semiconductor substrate | |
| JPH11145146A (en) | Semiconductor substrate and its manufacture | |
| JPH0661234A (en) | Production of semiconductor device | |
| JPH0396223A (en) | Forming method for soi structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 19991005 |
|
| LAPS | Cancellation because of no payment of annual fees |