JPH07193072A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH07193072A JPH07193072A JP5329365A JP32936593A JPH07193072A JP H07193072 A JPH07193072 A JP H07193072A JP 5329365 A JP5329365 A JP 5329365A JP 32936593 A JP32936593 A JP 32936593A JP H07193072 A JPH07193072 A JP H07193072A
- Authority
- JP
- Japan
- Prior art keywords
- heat treatment
- temperature
- oxygen
- wafer
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 11
- 239000004065 semiconductor Substances 0.000 title claims description 5
- 238000010438 heat treatment Methods 0.000 claims abstract description 35
- 238000000034 method Methods 0.000 claims abstract description 28
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 21
- 239000001301 oxygen Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 18
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 15
- 239000010703 silicon Substances 0.000 claims abstract description 15
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims abstract description 13
- -1 oxygen ions Chemical class 0.000 claims abstract description 8
- 239000012299 nitrogen atmosphere Substances 0.000 claims abstract description 6
- 239000013078 crystal Substances 0.000 claims description 7
- 239000012298 atmosphere Substances 0.000 claims description 6
- 230000001965 increasing effect Effects 0.000 claims description 6
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 229910052739 hydrogen Inorganic materials 0.000 claims description 4
- 239000001257 hydrogen Substances 0.000 claims description 4
- 230000007547 defect Effects 0.000 abstract description 22
- 230000000694 effects Effects 0.000 abstract description 13
- 238000005247 gettering Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 230000003028 elevating effect Effects 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 description 25
- 230000000052 comparative effect Effects 0.000 description 9
- 238000005468 ion implantation Methods 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- 238000010586 diagram Methods 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910001385 heavy metal Inorganic materials 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000002244 precipitate Substances 0.000 description 3
- 238000000151 deposition Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 125000004432 carbon atom Chemical group C* 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 238000012827 research and development Methods 0.000 description 1
- 238000005488 sandblasting Methods 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 239000007790 solid phase Substances 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26533—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
- H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
- H01L21/3226—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering of silicon on insulator
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Element Separation (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明はシリコン半導体基板の製
造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a silicon semiconductor substrate.
【０００２】[0002]
【従来の技術】現在、シリコン超ＬＳＩはＤＲＡＭを例
にとると、４Ｍビットが量産の全盛であるが、１６Ｍビ
ットの量産も開始されている。さらに６４Ｍビットのサ
ンプル供給も発表され、高集積化は着実に進展してい
る。このまま推移していけば最小寸法０．１〜０．１５
μｍの１ＧビットＤＲＡＭが出現することも時間の問題
であろう。2. Description of the Related Art At present, for a silicon VLSI, taking a DRAM as an example, a mass production of 4M bits is the most popular, but mass production of 16M bits has also started. Furthermore, the supply of 64 Mbit samples has been announced, and high integration is steadily progressing. The minimum size is 0.1 to 0.15
The emergence of μm 1 Gbit DRAMs will also be a matter of time.
【０００３】１Ｇビット時代のトランジスタが構築され
るシリコン基板は、一段と高品質が要求され、また極限
にまで微細化されたデバイスの機能をフルに引き出すた
めには、ＳＯＩ（Ｓｉｌｉｃｏｎ ｏｎ Ｉｎｓｕｌａ
ｔｏｒ）構造が最適であると言われている。ＳＯＩとし
ては、ＳＩＭＯＸ（Ｓｅｐａｒａｔｉｏｎ ｂｙ Ｉｍ
ｐｌａｎｔｅｄ Ｏｘｙｇｅｎ）、貼り合わせウェー
ハ、固相エピウェーハなどについて研究開発が進められ
ているが、ＳＩＭＯＸ技術はイオン注入と高温熱処理を
繰り返すことで、表面単結晶領域の結晶性が近年著しく
向上し、厚さ０．１μｍ程度のシリコン単結晶層を形成
することも容易になりつつあり、最も有望なＳＯＩの一
つである。A silicon substrate on which a transistor in the 1 G-bit era is constructed is required to have higher quality, and in order to fully bring out the function of a device which is miniaturized to the limit, SOI (Silicon on Insula) is required.
(tor) structure is said to be optimal. As SOI, SIMOX (Separation by Im)
Although research and development are being carried out on such as bonded oxygen), bonded wafers, and solid-phase epi-wafers, SIMOX technology has improved the crystallinity of the surface single crystal region significantly in recent years by repeating ion implantation and high-temperature heat treatment. It is becoming easier to form a silicon single crystal layer of about 0.1 μm, and it is one of the most promising SOIs.
【０００４】一方、高品質化について言及すれば、集積
度の増大とともに、デバイス形成領域の欠陥密度を指数
関数的に低減しなければならない。On the other hand, regarding the improvement of quality, it is necessary to exponentially reduce the defect density in the device formation region as the degree of integration increases.
【０００５】[0005]
【発明が解決しようとする課題】この欠陥生成には重金
属不純物が深く関わっており、デバイス形成領域から重
金属不純物を除去・低減するゲッタリング技術が極めて
重要になっている。したがってＧビット時代にはＳＩＭ
ＯＸ基板のゲッタリング技術を確率することが必須であ
る。Heavy metal impurities are deeply involved in the generation of defects, and a gettering technique for removing and reducing heavy metal impurities from the device formation region is extremely important. Therefore SIM in the G-bit era
It is essential to establish gettering technology for OX substrates.
【０００６】本発明の目的はＳＩＭＯＸ基板のゲッタリ
ング効果を高める製造方法を提供することである。通常
ＳＩＭＯＸ基板の製造はイオン注入と熱処理で行われ。
例えば１５０ＫｅＶの加速エネルギでドーズ量２×１０
18／ｃｍ2 の酸素イオンをシリコン基板表面から注入
し、表面から少し内部へ入った領域にＳｉＯ2 層からな
る絶縁層（Ｉｎｓｕｌａｔｏｒ）を形成する。次いで、
このイオン注入により生成された微少な転移ループ等の
格子欠陥を消滅させるために、１３００°Ｃ程度の高温
で熱処理を行う。An object of the present invention is to provide a manufacturing method for enhancing the gettering effect of a SIMOX substrate. Normally, SIMOX substrates are manufactured by ion implantation and heat treatment.
For example, with an acceleration energy of 150 KeV, a dose amount of 2 × 10
Oxygen ions of 18 / cm 2 are implanted from the surface of the silicon substrate, and an insulating layer (Insulator) made of a SiO 2 layer is formed in a region slightly inside the surface. Then
In order to eliminate lattice defects such as minute transition loops generated by this ion implantation, heat treatment is performed at a high temperature of about 1300 ° C.
【０００７】一方、ゲッタリング技術としては、ウェー
ハ裏面にサンドブラストで歪をつける方法、多結晶シリ
コン膜を堆積する方法、高濃度のＰ（リン）を注入する
方法などがあるが、シリコンウェーハ内部に析出した酸
素析出物に起因する結晶欠陥の歪場を利用するイントリ
ンシック・ゲッタリング（ＩＧ）が量産性に優れ、クリ
ーンなゲッタリング方法として一部では量産に用いられ
ている。On the other hand, as the gettering technique, there are a method of applying strain to the back surface of the wafer by sandblasting, a method of depositing a polycrystalline silicon film, a method of implanting high-concentration P (phosphorus), and the like. Intrinsic gettering (IG), which utilizes the strain field of crystal defects caused by precipitated oxygen precipitates, has excellent mass productivity and is partially used for mass production as a clean gettering method.
【０００８】ＳＩＭＯＸはイオン注入後１３００°Ｃ程
度の高温熱処理を施すため、ＩＧ効果が期待できないと
言われている。これはＳｉＯ2 析出物などの結晶欠陥に
捕捉された重金属不純物が高温熱処理で再び溶解し、ウ
ェーハ内に拡散してしまうからである。また高温熱処理
によりＳｉＯ2 析出物が再溶解し、ゲッタリング能力が
低下するからでもある。そのためＳＩＭＯＸでは裏面に
多結晶シリコン膜を堆積する方法や、デバイス形成領域
の極く近傍にカーボン原子などをイオン注入し、その歪
場でゲッタリングする方法などが検討されている。しか
しながらこれらの方法は低温プロセス化の時代にはそぐ
わないものであり、またコストの増大、技術的な問題な
ど多くの難点があるのに対して、ＩＧ技術は優れたゲッ
タリング方法であり、ウェーハ製造コストも比較的安
く、Ｇビット時代に適した方法である。Since SIMOX is subjected to high temperature heat treatment at about 1300 ° C. after ion implantation, it is said that the IG effect cannot be expected. This is because the heavy metal impurities captured by crystal defects such as SiO 2 precipitates are dissolved again by the high temperature heat treatment and diffused into the wafer. Further, this is also because the SiO 2 precipitate is redissolved by the high temperature heat treatment and the gettering ability is lowered. Therefore, in SIMOX, a method of depositing a polycrystalline silicon film on the back surface, a method of ion-implanting carbon atoms or the like in the immediate vicinity of a device formation region, and a method of gettering in the strain field are being studied. However, these methods are not suitable for the era of low temperature process, and there are many drawbacks such as increase in cost and technical problems, while IG technology is an excellent gettering method and wafer manufacturing. The cost is relatively low, and this method is suitable for the G-bit era.
【０００９】したがってＳＩＭＯＸに適したＩＧ効果を
実現するための熱処理方法を開発しなければならない。Therefore, it is necessary to develop a heat treatment method for realizing the IG effect suitable for SIMOX.
【００１０】[0010]
【課題を解決するための手段】本発明は、シリコン単結
晶基板に酸素イオンを高エネルギで加速して注入したの
ち、該基板を水素雰囲気または酸素を少量含む窒素雰囲
気中で、１２００〜１３００°Ｃの温度で６〜１２時間
の熱処理を施したのち、低温から高温へ段階的または連
続的に温度を上昇させて熱処理を施すことを特徴とす
る。According to the present invention, oxygen ions are accelerated and implanted into a silicon single crystal substrate at a high energy, and then the substrate is heated to 1200 to 1300 ° in a hydrogen atmosphere or a nitrogen atmosphere containing a small amount of oxygen. The heat treatment is performed at a temperature of C for 6 to 12 hours, and then the heat treatment is performed by gradually or continuously increasing the temperature from a low temperature to a high temperature.
【００１１】段階的な熱処理方法としては、５００°Ｃ
から出発し、５０〜１００°Ｃの段階で順次上昇させ、
最終温度を８５０°Ｃまでとする。The stepwise heat treatment method is 500 ° C.
Starting from, the temperature rises in steps of 50-100 ° C,
Bring the final temperature up to 850 ° C.
【００１２】また連続的な熱処理方法としては、５００
°Ｃから出発し、０．２°Ｃ／ｍｉｎ〜１．０°Ｃ／ｍ
ｉｎの勾配で、最終温度を８５０°Ｃとする。Further, as a continuous heat treatment method, 500
Starting from ° C, 0.2 ° C / min to 1.0 ° C / m
A final temperature of 850 ° C with an in gradient.
【００１３】[0013]
【実施例】以下実施例を図面を用いて詳細に説明する。
イオン注入プロセスと熱処理プロセスの組合せ及び二通
りの熱処理を施した。Embodiments will be described in detail below with reference to the drawings.
A combination of an ion implantation process and a heat treatment process and two heat treatments were performed.
【００１４】実施例１ まず図１に示すように２００ＫｅＶの加速エネルギでド
ーズ量２×１０18／ｃｍ2 の酸素イオンＯ+ をＰ型（１
００）シリコンウェーハ１に注入した。イオン注入前の
シリコンウェーハの格子間酸素濃度は旧ＡＳＴＭの係数
で１５×１０17ａｔｏｍｓ／ｃｍ3 であった。次いで１
３００°Ｃ，６Ｈの熱処理を酸素３％を含む窒素雰囲気
中で施した。その結果厚さ４０００ＡのＳｉＯ2 層１０
がウェーハ表面から０．３μｍ直下に形成された。次い
で５００°Ｃから出発し、１００°Ｃ毎に熱処理温度を
順次上昇させ、最終段階の温度として８００°Ｃを用
い、多段階熱処理を施して内部欠陥２０を形成した。多
段階熱処理の各段階での処理時間は８Ｈとし、乾燥酸素
雰囲気で行なった。これらのフローを図１に示す。また
評価のため一部のウェーハに１１４０°Ｃ，２Ｈ，湿式
酸素雰囲気中で熱処理を行った。Example 1 First, as shown in FIG. 1, oxygen ions O + with a dose amount of 2 × 10 18 / cm 2 were accelerated to a P-type (1
00) Implanted in a silicon wafer 1. The interstitial oxygen concentration of the silicon wafer before ion implantation was 15 × 10 17 atoms / cm 3 as a coefficient according to old ASTM. Then 1
A heat treatment at 300 ° C. and 6 H was performed in a nitrogen atmosphere containing 3% oxygen. As a result, a 4000 A thick SiO 2 layer 10
Was formed just under 0.3 μm from the wafer surface. Then, starting from 500 ° C., the heat treatment temperature was sequentially increased every 100 ° C., and 800 ° C. was used as the final temperature, and multi-stage heat treatment was performed to form the internal defects 20. The treatment time in each stage of the multi-stage heat treatment was 8H, and the treatment was performed in a dry oxygen atmosphere. These flows are shown in FIG. For evaluation, some wafers were heat-treated in a wet oxygen atmosphere at 1140 ° C. for 2H.
【００１５】比較例１ 基本的には実施例１と同様なフローであるが、多段階熱
処理の代りに８００°Ｃ，１６Ｈの熱処理を施した。フ
ローを図２に示す。Comparative Example 1 Basically, the flow is the same as in Example 1, but heat treatment at 800 ° C. and 16H is performed instead of the multi-step heat treatment. The flow is shown in FIG.
【００１６】比較例２ 酸素イオンを注入する前にＩＧ効果のための熱処理を施
した。まずシリコンウェーハ表面から酸素を外方拡散さ
せるために、図３に示すように１１５０°Ｃ，８Ｈ，酸
素を３％含む窒素雰囲気中で熱処理を行い、次いで実施
例１と同様に酸素イオンを注入し、結晶欠陥回復のため
の熱処理を１３００°Ｃ，６Ｈ行った。Comparative Example 2 Before implanting oxygen ions, heat treatment for the IG effect was performed. First, in order to diffuse oxygen outward from the silicon wafer surface, as shown in FIG. 3, heat treatment is performed in a nitrogen atmosphere containing 1150 ° C., 8H, and 3% oxygen, and then oxygen ions are implanted in the same manner as in Example 1. Then, heat treatment for recovering crystal defects was performed at 1300 ° C. for 6 hours.
【００１７】以上の３つの例についてＩＧ効果の能力を
評価した。まずウェーハをヘキ開し、その断面をライト
液でエッチングし内部欠陥密度を測定した。実施例１の
ウェーハは５×１０5 個／ｃｍ2 の内部欠陥が観察され
たが、比較例１のウェーハは２×１０4 個／ｃｍ2 ，比
較例２のウェーハは１×１０4 個／ｃｍ2 であり、実施
例１のウェーハではＩＧ効果に必要な内部欠陥が十分残
存していることが分った。しかしながら比較例１，２の
ウェーハの内部欠陥密度は低くＩＧ効果には不十分であ
ることが推定された。図４に各々の例での内部欠陥密度
を示す。次に表面欠陥を評価するために１１４０°Ｃ，
２Ｈ，湿式酸素中で熱処理したウェーハを３つの例とも
ジルトル液でエッチングした。シャローピットとして観
察される表面欠陥密度は実施例１のウェーハではほぼ０
個／ｃｍ2 ，比較例１のウェーハは５×１０4 個／ｃｍ
2 ，比較例２のウェーハでは１×１０5 個／ｃｍ2 で、
後二者はゲッタリングが不十分であった。図５に各例で
の表面欠陥密度を示す。The ability of the IG effect was evaluated for the above three examples. First, the wafer was cleaved and its cross section was etched with a Wright solution to measure the internal defect density. Although internal defects of the wafer of 5 × 10 5 cells / cm 2 in Example 1 was observed, the wafer of Comparative Example 1 is 2 × 10 4 cells / cm 2, the wafer of Comparative Example 2 1 × 10 4 cells / cm 2, and the wafer of example 1 was found to internal defects necessary for IG effect is sufficiently remained. However, it was estimated that the internal defect densities of the wafers of Comparative Examples 1 and 2 were low and were insufficient for the IG effect. FIG. 4 shows the internal defect density in each example. Next, to evaluate surface defects, 1140 ° C,
Wafers that had been heat-treated in 2H wet oxygen were etched with a dilute solution in all three examples. The surface defect density observed as shallow pits is almost 0 in the wafer of Example 1.
Wafers / cm 2 , the wafer of Comparative Example 1 is 5 × 10 4 wafers / cm 2 .
2 , the wafer of Comparative Example 2 was 1 × 10 5 pieces / cm 2 ,
The latter two did not getter enough. FIG. 5 shows the surface defect density in each example.
【００１８】実施例２ 次に多段階熱処理の代りに５００°Ｃから８００°Ｃま
で０．５°Ｃ／ｍｉｎの勾配で湿度を上昇させた。各実
施例のウェーハとも内部欠陥湿度及び表面欠陥密度は定
性的に実施例１を同様な傾向を示した。温度上昇の勾配
は０．１°Ｃ／ｍｉｎから２°Ｃ／ｍｉｎまで行った
が、ＩＧ効果に必要な内部欠陥を生成するためには０．
２°Ｃ／ｍｉｎ〜１．０°Ｃ／ｍｉｎが最適であった。
また最終温度は８５０°Ｃまで上げることができる。Example 2 Next, instead of the multi-step heat treatment, the humidity was increased at a gradient of 0.5 ° C / min from 500 ° C to 800 ° C. The internal defect humidity and the surface defect density of the wafers of the respective examples were qualitatively similar to those of the example 1. The gradient of the temperature rise was from 0.1 ° C / min to 2 ° C / min, but it was 0.degree. C. in order to generate internal defects necessary for the IG effect.
2 ° C / min to 1.0 ° C / min was optimal.
Also, the final temperature can be increased to 850 ° C.
【００１９】なおイオン注入後の高温処理温度及び雰囲
気についても検討したが、１２００°Ｃの場合は１２Ｈ
程度が望ましく、また１３００°Ｃでは６Ｈで十分であ
り、雰囲気については水素及び少量の酸素を含む窒素雰
囲気とが大差はなかった。また実施例１では１００°Ｃ
きざみで多段階熱処理をしたが、きざみは、５０〜１０
０°Ｃの範囲ならよく、最終温度も８５０°Ｃまではよ
い。The high temperature processing temperature and the atmosphere after the ion implantation were also examined.
6H is sufficient at 1300 ° C, and the atmosphere is not much different from the nitrogen atmosphere containing hydrogen and a small amount of oxygen. In Example 1, 100 ° C
Multi-step heat treatment was performed in the steps, but the steps were 50 to 10
The temperature may be in the range of 0 ° C, and the final temperature may be up to 850 ° C.
【００２０】[0020]
【発明の効果】以上述べたように、イオン注入後適切な
低温から高温への熱処理を施すことにより、ＳＩＭＯＸ
ウェーハにＩＧ効果を附与することができ、従来言われ
ていたＳＩＭＯＸでＩＧ効果を期待することは難しいと
いう考えが否定され、Ｇビット時代へ向けての高品質Ｓ
ＯＩウェーハの製造方法が確立された。As described above, SIMOX can be obtained by performing heat treatment from an appropriate low temperature to a high temperature after ion implantation.
The idea that the IG effect can be added to the wafer and it is difficult to expect the IG effect with SIMOX, which was said to have been denied, is rejected, and high quality S for the G-bit era
A method for manufacturing an OI wafer has been established.
【図１】実施例１のプロセスフローの図である。FIG. 1 is a diagram of a process flow of Example 1.
【図２】比較例１のプロセスフローの図である。2 is a process flow diagram of Comparative Example 1. FIG.
【図３】比較例２のプロセスフローの図である。FIG. 3 is a diagram of a process flow of Comparative Example 2.
【図４】図１〜３の例の代表的な内部欠陥密度の図であ
る。FIG. 4 is a diagram of representative internal defect densities for the examples of FIGS.
【図５】図１〜３の例の代表的な表面欠陥密度の図であ
る。FIG. 5 is a diagram of representative surface defect densities for the examples of FIGS.
１ シリコンウェーハ １０ ＳｉＯ2 層 ２０ 内部欠陥1 Silicon wafer 10 SiO 2 layer 20 Internal defects
Claims (3)
ネルギで加速して注入したのち、該基板を水素雰囲気ま
たは酸素を少量含む窒素雰囲気中で、１２００〜１３０
０°Ｃの温度で６〜１２時間の熱処理を施したのち、低
温から高温へ段階的または連続的に温度を上昇させて熱
処理を施すことを特徴とする半導体基板の製造方法。1. A silicon single crystal substrate is implanted with oxygen ions accelerated at a high energy, and then the substrate is exposed to hydrogen in a hydrogen atmosphere or a nitrogen atmosphere containing a small amount of oxygen in a range of 1200 to 130.
A method for manufacturing a semiconductor substrate, which comprises performing a heat treatment at a temperature of 0 ° C. for 6 to 12 hours and then increasing the temperature stepwise or continuously from a low temperature to a high temperature to perform the heat treatment.
Ｃから出発し、５０〜１００°Ｃの段階で順次上昇さ
せ、最終温度を８５０°Ｃまでとすることを特徴とする
請求項１記載の半導体基板の製造方法。2. The stepwise heat treatment method is 500 °
2. The method of manufacturing a semiconductor substrate according to claim 1, wherein the temperature starts from C and is gradually increased at a temperature of 50 to 100 [deg.] C. until the final temperature reaches 850 [deg.] C.
Ｃから出発し、０．２°Ｃ／ｍｉｎ〜１．０°Ｃ／ｍｉ
ｎの勾配で、最終温度を８５０°Ｃとすることを特徴と
する請求項１記載の半導体基板の製造方法。3. A continuous heat treatment method includes 500 ° C.
Starting from C, 0.2 ° C / min to 1.0 ° C / mi
The method for manufacturing a semiconductor substrate according to claim 1, wherein the final temperature is 850 ° C. with a gradient of n.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5329365A JPH07193072A (en) | 1993-12-27 | 1993-12-27 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5329365A JPH07193072A (en) | 1993-12-27 | 1993-12-27 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH07193072A true JPH07193072A (en) | 1995-07-28 |
Family
ID=18220646
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5329365A Pending JPH07193072A (en) | 1993-12-27 | 1993-12-27 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH07193072A (en) |
Cited By (7)
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|---|---|---|---|---|
| WO2002097892A1 (en) * | 2001-05-29 | 2002-12-05 | Nippon Steel Corporation | Soi substrate |
| WO2005020307A1 (en) * | 2003-08-14 | 2005-03-03 | Ibis Technology Corporation | Internal gettering in simox soi silicon substrates |
| JP2005286282A (en) * | 2004-03-01 | 2005-10-13 | Sumco Corp | Method of manufacturing simox substrate and simox substrate resulting from same |
| JP2005340348A (en) * | 2004-05-25 | 2005-12-08 | Sumco Corp | Manufacturing method of simox substrate and simox substrate obtained thereby |
| WO2006009148A1 (en) * | 2004-07-20 | 2006-01-26 | Sumco Corporation | Simox substrate manufacturing method |
| JP2007067321A (en) * | 2005-09-02 | 2007-03-15 | Sumco Corp | Simox substrate and its manufacturing method |
| JP2010062503A (en) * | 2008-09-08 | 2010-03-18 | Sumco Corp | Method for reducing crystal defect of simox wafer and simox wafer |
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| JPH0582525A (en) * | 1991-09-19 | 1993-04-02 | Nec Corp | Simox substrate and manufacture thereof |
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| JPS5721825A (en) * | 1980-07-14 | 1982-02-04 | Nec Corp | Increasing method for gettering effect due to internal defect in semiconductor substrate |
| JPH03166733A (en) * | 1989-11-27 | 1991-07-18 | Olympus Optical Co Ltd | Manufacture of semiconductor device |
| JPH0461341A (en) * | 1990-06-29 | 1992-02-27 | Kyushu Electron Metal Co Ltd | Method of forming oxygen deposit at semiconductor wafer |
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7084459B2 (en) | 2001-05-29 | 2006-08-01 | Nippon Steel Corporation | SOI substrate |
| WO2002097892A1 (en) * | 2001-05-29 | 2002-12-05 | Nippon Steel Corporation | Soi substrate |
| WO2005020307A1 (en) * | 2003-08-14 | 2005-03-03 | Ibis Technology Corporation | Internal gettering in simox soi silicon substrates |
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| JP2005286282A (en) * | 2004-03-01 | 2005-10-13 | Sumco Corp | Method of manufacturing simox substrate and simox substrate resulting from same |
| JP2005340348A (en) * | 2004-05-25 | 2005-12-08 | Sumco Corp | Manufacturing method of simox substrate and simox substrate obtained thereby |
| WO2005117122A1 (en) * | 2004-05-25 | 2005-12-08 | Sumitomo Mitsubishi Silicon Corporation | Process for producing simox substrate and simox substrate produced by the process |
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| US7560363B2 (en) | 2004-07-20 | 2009-07-14 | Sumco Corporation | Manufacturing method for SIMOX substrate |
| JP4706199B2 (en) * | 2004-07-20 | 2011-06-22 | 株式会社Ｓｕｍｃｏ | SIMOX substrate manufacturing method |
| JP2007067321A (en) * | 2005-09-02 | 2007-03-15 | Sumco Corp | Simox substrate and its manufacturing method |
| JP2010062503A (en) * | 2008-09-08 | 2010-03-18 | Sumco Corp | Method for reducing crystal defect of simox wafer and simox wafer |
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